CN113628650B - SRAM cell structure and SRAM - Google Patents
SRAM cell structure and SRAM Download PDFInfo
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- CN113628650B CN113628650B CN202110687647.6A CN202110687647A CN113628650B CN 113628650 B CN113628650 B CN 113628650B CN 202110687647 A CN202110687647 A CN 202110687647A CN 113628650 B CN113628650 B CN 113628650B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The application discloses a static random access memory cell structure and a static random access memory. The static random access memory cell structure comprises a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS transistor and a fourth fully depleted silicon-on-insulator NMOS transistor; the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the input end of the first inverter; the source electrode/drain electrode of the third full-depletion silicon-on-insulator NMOS tube is connected with the output end of the first phase inverter, and the drain electrode/source electrode of the third full-depletion silicon-on-insulator NMOS tube is connected with the write bit line; and the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter. The fully-depleted silicon-on-insulator MOS transistor is adopted, so that static noise margin in a holding state can be ensured, anti-interference capability in a reading state is improved, and the speed of reading and writing of the memory is improved under the condition of high-density integration.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a sram cell structure and a sram.
Background
Static Random Access Memory (SRAM) is an integral part of integrated circuits, mainly for data storage and data computation in a short time. Generally, SRAM is a circuit module with the most severe design rule, the most densely arranged components, the fastest operation speed and the highest operation power consumption in a chip circuit. Conventional SRAM memory uses a 6T (6 transistor) structure or an 8T (8 transistor) structure to store 1bit or 2bit data.
The development of microelectronics technology has placed demands on SRAM for higher density, higher operating speed, lower power consumption, i.e., high energy efficiency. A very efficient solution is to enable the power consumption of the cell to be reduced in square by reducing the operating voltage Vdd of the SRAM. However, lowering the operating voltage presents many challenges to the conventional 6T/8T structure, with the more serious challenge being that the noise margin window (SNM) of the memory cells is shrinking, such that new types of memory cells are susceptible to being lost by interference, as shown in fig. 1. The SRAM stores information in the form of voltages at storage node Q and storage node Qb. The better SNM ensures that the voltages at storage node Q and storage node Qb are as designed to be expected without logic errors. SRAM has three common modes of operation, namely Write operation (Write), read operation (Read), hold operation (Hold). When writing operation is performed, a Word Line (WL) is started, external voltage is applied through Vbl, VQ and VQB can reach expected voltage, at the moment, the PMOS pull-up capability influences noise margin when writing, and normally VQ and VQB can reach 0 and Vdd respectively; during the holding operation, the voltage is stabilized through the inverter pair, the VQ and the VQB can be maintained at 0 and Vdd, and the SNM is mainly influenced by the threshold voltage; in a read operation, the voltage at Q, qb needs to be redistributed between two turned-on NMOS transistors, VQ and VQB are at intermediate voltages, and are very prone to be disturbed to logic errors. Therefore, in general, the SNM in the read operation is the worst, and the SNM in the write operation is generally the best in the hold state. In low power designs, the immunity to noise decreases as Vdd decreases (as shown in fig. 1 and 2), where the short plate where the read operation is SNM will be more pronounced.
Disclosure of Invention
The present application is directed to a sram cell structure and a sram. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to one aspect of embodiments of the present application, there is provided a static random access memory cell structure comprising a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS transistor, and a fourth fully depleted silicon-on-insulator NMOS transistor;
the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the input end of the first inverter;
the source electrode/drain electrode of the third fully depleted silicon-on-insulator NMOS tube is connected with the output end of the first phase inverter, the drain electrode/source electrode of the third fully depleted silicon-on-insulator NMOS tube is connected with a write bit line, and the grid electrode and the back grid of the third fully depleted silicon-on-insulator NMOS tube are respectively connected with a write word line;
the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the back grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with a read word line; the drain/source of the fourth fully depleted silicon-on-insulator NMOS tube is connected with a read bit line, and the source/drain of the fourth fully depleted silicon-on-insulator NMOS tube is connected with a read word line.
Further, the sram cell structure further comprises a fifth fully depleted silicon-on-insulator NMOS transistor;
the grid electrode and the back grid electrode of the fifth fully-depleted silicon-on-insulator NMOS tube are respectively connected with a writing line, the source electrode/drain electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with a writing bit line.
Further, the first inverter comprises a first fully depleted silicon-on-insulator PMOS transistor and a first fully depleted silicon-on-insulator NMOS transistor, wherein the drain of the first fully depleted silicon-on-insulator PMOS transistor is connected with the drain of the first fully depleted silicon-on-insulator NMOS transistor, the gate of the first fully depleted silicon-on-insulator PMOS transistor is connected with the gate of the first fully depleted silicon-on-insulator NMOS transistor, the gate of the first fully depleted silicon-on-insulator PMOS transistor is connected with the input end of the first inverter, and the drain of the first fully depleted silicon-on-insulator PMOS transistor is connected with the output end of the first inverter.
Further, the back gate of the first fully depleted silicon-on-insulator PMOS is connected to the source of the first fully depleted silicon-on-insulator PMOS.
Further, the back gate of the first fully depleted silicon-on-insulator NMOS tube is connected with the source of the first fully depleted silicon-on-insulator NMOS tube.
Further, the second inverter includes a second fully depleted silicon on insulator PMOS and a second fully depleted silicon on insulator NMOS, the drain of the second fully depleted silicon on insulator PMOS is connected to the drain of the second fully depleted silicon on insulator NMOS, the gate of the second fully depleted silicon on insulator PMOS is connected to the gate of the second fully depleted silicon on insulator NMOS, the gate of the second fully depleted silicon on insulator PMOS is connected to the input of the second inverter, and the drain of the second fully depleted silicon on insulator PMOS is connected to the output of the second inverter.
Further, the back gate of the second fully depleted silicon-on-insulator PMOS is connected to the source of the second fully depleted silicon-on-insulator PMOS.
Further, the back gate of the second fully depleted silicon-on-insulator NMOS tube is connected with the source of the second fully depleted silicon-on-insulator NMOS tube.
According to another aspect of the embodiments of the present application, there is provided a sram, including a plurality of sram cell structures described above.
According to another aspect of the embodiments of the present application, there is provided a memory device including the sram described above.
One of the technical solutions provided in one aspect of the embodiments of the present application may include the following beneficial effects:
the static random access memory unit structure provided by the embodiment of the application adopts the fully-depleted silicon-on-insulator MOS tube, can ensure static noise margin in a holding state, improve the anti-interference capability in a reading state, improve the speed of reading and writing of the memory under the condition of high-density integration, and realize the operation of the SRAM unit structure under low voltage.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a bit line voltage butterfly line schematic diagram of a prior art SRAM cell structure;
FIG. 2 illustrates a data storage point voltage plot of a prior art SRAM cell structure during a read operation phase and a state retention phase;
FIG. 3 shows a circuit diagram of an SRAM cell structure of one embodiment of the present application;
FIG. 4 shows a circuit diagram of an SRAM cell structure of another embodiment of the present application;
FIG. 5 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator PMOS tube;
figure 6 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator NMOS tube.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
One embodiment of the present application provides a static random access memory cell structure comprising a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS transistor, and a fourth fully depleted silicon-on-insulator NMOS transistor;
the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the input end of the first inverter;
the source/drain of the third fully depleted silicon-on-insulator NMOS is connected to the output of the first inverter,
the drain electrode/source electrode of the third fully depleted silicon NMOS tube is connected with a write bit line, and the grid electrode and the back grid electrode of the third fully depleted silicon NMOS tube are respectively connected with a write word line;
the grid electrode of the fourth fully-depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the back grid electrode of the fourth fully-depleted silicon-on-insulator NMOS tube is connected with the read word line; the drain/source of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read bit line, and the source/drain of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line.
The P-type transistors in the embodiments of the present application are all fully depleted silicon-on-insulator PMOS transistors, and the N-type transistors are all fully depleted silicon-on-insulator NMOS transistors.
An SRAM cell structure of the embodiment shown in fig. 3 employs a 6T structure, an FDSOI structure, and a structure topology and back bias (body bias) voltage optimization. The SRAM memory cell is composed of 6 field effect transistors, including 2P-type transistors P1 and P2, and 4N-type transistors N1, N2, N3 and N4.
P1 and N1 form an inverter, called a first inverter; p2 and N2 form an inverter, called a second inverter; the output of the first inverter is used as the input of the second inverter, and the output of the second inverter is used as the input of the first inverter, so that the first inverter and the second inverter form a cross-coupling structure, a first storage node Q and a second storage node Qb are formed, the first storage node Q is the output end of the first inverter, and the second storage node Qb is the output end of the second inverter.
The source electrode (or drain electrode) of the N3 is connected with the output end of the first inverter; the output of the second inverter is connected to the gate of N4. The first inverter and the second inverter share the same power supply and ground. N3 has a gate connected to the Write Word Line (WWL), a drain connected to the Write Bit Line (WBL), and N4 has a source connected to the Read Word Line (RWL) and a drain connected to the Read Bit Line (RBL). N3 is used for control of write operations and N4 is used for control of read operations.
Due to the adoption of the FDSOI structure, compared with a traditional bulk silicon structure, the static current and the power consumption of the node are lower.
The read operation can be separated from the write operation (decouping) by N4 and N3. When the readout operation is performed, the Q or Qb terminal is connected to the gate of N4, so that the voltage at Q, qb can be maintained at the ground terminal or the high voltage terminal, and the readout SNM is improved.
When the write operation is performed, the write voltage can be transferred to the inverter pair consisting of the first inverter and the second inverter by controlling N3 to be turned on by WWL.
Preferably, N3 is introduced into the high-voltage back bias, so that the threshold voltage (to 0) of N3 can be effectively reduced, and as shown in fig. 5, no-damage transmission of N3 voltage (whether high voltage or low voltage) can be realized. And meanwhile, the driving capability of N3 is stronger, thereby being beneficial to faster writing.
Preferably, N4 is introduced into the back bias RWL, and when the write operation is performed, the N4 threshold can be lowered, and the driving capability of N4 can be improved, so that the read rate can be improved without affecting SNM at the time of read.
In some embodiments, the sram cell structure further comprises a fifth fully depleted silicon-on-insulator NMOS transistor; the grid electrode and the back grid electrode of the fifth fully-depleted silicon-on-insulator NMOS tube are respectively connected with a write word line, the source electrode/drain electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with a write bit line.
An SRAM cell structure of the embodiment shown in fig. 4 employs a 7T structure, an FDSOI structure, and a structure topology and back bias (body bias) voltage optimization. Meanwhile, the possible threshold loss during the reading operation is considered, a symmetrical writing structure is adopted, and the SNM during writing is ensured as much as possible.
The SRAM memory cell is composed of 7 field effect transistors, including 2P-type transistors P1 and P2, and 4N-type transistors N1, N2, N3, N4 and N5.
P1 and N1 form an inverter, called a first inverter; p2 and N2 form an inverter, called a second inverter; the output of the first inverter is used as the input of the second inverter, and the output of the second inverter is used as the input of the first inverter, so that the first inverter and the second inverter form a cross-coupling structure, a first storage node Q and a second storage node Qb are formed, the first storage node Q is the output end of the first inverter, and the second storage node Qb is the output end of the second inverter.
The source electrode (or drain electrode) of the N3 is connected with the output end of the first inverter; the output of the second inverter is connected to the gate of N4. The first inverter and the second inverter share the same power supply and ground. N3 has a gate connected to the Write Word Line (WWL), a drain connected to the Write Bit Line (WBL), and N4 has a source connected to the Read Word Line (RWL) and a drain connected to the Read Bit Line (RBL). N3 is used for control of write operations and N4 is used for control of read operations.
The source (or drain) of N5 is connected with the output end of the second inverter, the grid of N5 is connected with WWL, and the third end of N5 is connected with WBL. P1 and P2 adopt the same electrical parameters, N1 and N2 adopt the same electrical parameters, and N3 and N4 adopt the same electrical parameters. N1, N3, N5 may take different electrical parameters, such as transistor threshold voltages. FIG. 5 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator PMOS tube, showing substrate 1, N-well layer 2, insulating layer 3, back gate 4, gate 5, source 6 and drain 7; fig. 6 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator NMOS transistor, showing substrate 1, deep N-well layer 8, insulating layer 3, back gate 4, gate 5, source 6 and drain 7.
In some embodiments, the first inverter comprises a first fully depleted silicon-on-insulator PMOS transistor and a first fully depleted silicon-on-insulator NMOS transistor, the drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to the drain of the first fully depleted silicon-on-insulator NMOS transistor, the gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to the gate of the first fully depleted silicon-on-insulator NMOS transistor, the gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to the input of the first inverter, and the drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to the output of the first inverter.
In some embodiments, the back gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to the source of the first fully depleted silicon-on-insulator PMOS transistor.
In some embodiments, the back gate of the first fully depleted silicon-on-insulator NMOS transistor is connected to the source of the first fully depleted silicon-on-insulator NMOS transistor.
In some embodiments, the second inverter comprises a second fully depleted silicon-on-insulator PMOS transistor and a second fully depleted silicon-on-insulator NMOS transistor, the drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to the drain of the second fully depleted silicon-on-insulator NMOS transistor, the gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to the gate of the second fully depleted silicon-on-insulator NMOS transistor, the gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to the input of the second inverter, and the drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to the output of the second inverter.
In some embodiments, the back gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to the source of the second fully depleted silicon-on-insulator PMOS transistor.
In some embodiments, the back gate of the second fully depleted silicon-on-insulator NMOS transistor is connected to the source of the second fully depleted silicon-on-insulator NMOS transistor.
In order to enable the SRAM to work under low voltage and even work under the subthreshold of a device, the embodiment of the application provides an SRAM unit structure based on an FDSOI (Fully DepletedSilicon On Insulator ) field effect transistor, a read state and a write state are separated through optimization of circuit topology, meanwhile, the static noise margin in a holding state can be ensured, the anti-interference capability in a read state is improved, the speed of reading and writing of a memory is improved under the condition of high-density integration, and the SRAM unit structure works under the low voltage.
Another embodiment of the present application provides a sram comprising a plurality of sram cell structures according to any one of the above embodiments.
Another embodiment of the present application provides a memory device including a sram according to any one of the above embodiments.
Compared with the traditional bulk silicon SRAM structure, the embodiment of the application adopts the FDSOI structure SRAM, and through optimization of circuit topology and optimization of back bias, the SRAM can improve the noise capacity of a read state under the condition of ensuring the static noise margin, and meanwhile, the writing and reading speeds of the SRAM are improved under the condition of not sacrificing the anti-interference capability. Meanwhile, since a 6T or 7T structure is adopted, the increase in the cell area is not significant.
It should be noted that:
the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance. It should also be understood that, although the terms "first," "second," "third," etc. are used in the text to describe various objects in some embodiments of the present application, these objects should not be limited by these terms. These terms are only used to distinguish between various objects.
The foregoing examples merely represent embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (6)
1. A static random access memory cell structure comprising a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS and a fourth fully depleted silicon-on-insulator NMOS;
the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the input end of the first inverter;
the source electrode/drain electrode of the third fully depleted silicon-on-insulator NMOS tube is connected with the output end of the first phase inverter, the drain electrode/source electrode of the third fully depleted silicon-on-insulator NMOS tube is connected with a write bit line, and the grid electrode and the back grid of the third fully depleted silicon-on-insulator NMOS tube are respectively connected with a write word line;
the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the back grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with a read word line; the drain electrode/source electrode of the fourth fully-depleted silicon-on-insulator NMOS tube is connected with a read bit line, and the source electrode/drain electrode of the fourth fully-depleted silicon-on-insulator NMOS tube is connected with a read word line;
the first inverter comprises a first fully depleted silicon-on-insulator PMOS tube and a first fully depleted silicon-on-insulator NMOS tube, wherein the back gate of the first fully depleted silicon-on-insulator PMOS tube is connected with the source electrode of the first fully depleted silicon-on-insulator PMOS tube, and the back gate of the first fully depleted silicon-on-insulator NMOS tube is connected with the source electrode of the first fully depleted silicon-on-insulator NMOS tube;
the second inverter comprises a second fully depleted silicon-on-insulator PMOS tube and a second fully depleted silicon-on-insulator NMOS tube, wherein the back gate of the second fully depleted silicon-on-insulator PMOS tube is connected with the source electrode of the second fully depleted silicon-on-insulator PMOS tube, and the back gate of the second fully depleted silicon-on-insulator NMOS tube is connected with the source electrode of the second fully depleted silicon-on-insulator NMOS tube.
2. The sram cell structure of claim 1, further comprising a fifth fully depleted silicon-on-insulator NMOS tube;
the grid electrode and the back grid electrode of the fifth fully-depleted silicon-on-insulator NMOS tube are respectively connected with a writing line, the source electrode/drain electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully-depleted silicon-on-insulator NMOS tube is connected with a writing bit line.
3. The sram cell structure of claim 1, wherein a drain of said first fully depleted silicon-on-insulator PMOS transistor is connected to a drain of said first fully depleted silicon-on-insulator NMOS transistor, a gate of said first fully depleted silicon-on-insulator PMOS transistor is connected to a gate of said first fully depleted silicon-on-insulator NMOS transistor, a gate of said first fully depleted silicon-on-insulator PMOS transistor is connected to an input of said first inverter, and a drain of said first fully depleted silicon-on-insulator PMOS transistor is connected to an output of said first inverter.
4. The sram cell structure of claim 1, wherein a drain of said second fully depleted silicon-on-insulator PMOS transistor is connected to a drain of said second fully depleted silicon-on-insulator NMOS transistor, a gate of said second fully depleted silicon-on-insulator PMOS transistor is connected to a gate of said second fully depleted silicon-on-insulator NMOS transistor, a gate of said second fully depleted silicon-on-insulator PMOS transistor is connected to an input of said second inverter, and a drain of said second fully depleted silicon-on-insulator PMOS transistor is connected to an output of said second inverter.
5. A sram comprising a plurality of sram cell structures as claimed in any one of claims 1 to 4.
6. A memory device comprising the sram of claim 5.
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| CN109741777A (en) * | 2018-12-28 | 2019-05-10 | 上海新储集成电路有限公司 | A kind of memory for improving speed and keeping data time |
| CN111145810A (en) * | 2019-12-19 | 2020-05-12 | 华东师范大学 | Static random access memory based on FDSOI device back gate structure |
| CN112382325A (en) * | 2020-12-11 | 2021-02-19 | 北京中科芯蕊科技有限公司 | Sub-threshold SRAM read-write auxiliary circuit |
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