CN113628650A - Static random access memory unit structure and static random access memory - Google Patents
Static random access memory unit structure and static random access memory Download PDFInfo
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- 238000005457 optimization Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The application discloses a static random access memory unit structure and a static random access memory. The static random access memory unit structure comprises a first phase inverter, a second phase inverter, a third fully depleted silicon-on-insulator NMOS tube and a fourth fully depleted silicon-on-insulator NMOS tube; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the first phase inverter; the source/drain of the third fully depleted silicon-on-insulator NMOS tube is connected with the output end of the first phase inverter, and the drain/source of the third fully depleted silicon-on-insulator NMOS tube is connected with the write bit line; and the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second inverter. The application adopts the fully depleted silicon-on-insulator MOS tube, can ensure the static noise margin in a holding state, improve the anti-interference capability in a reading state, and improve the reading and writing speeds of the memory under the condition of high-density integration.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to a cell structure of a static random access memory and a static random access memory.
Background
Static Random Access Memory (SRAM) is an indispensable part of integrated circuits, and is mainly used for data storage and data calculation in a short time. Generally, the SRAM is a circuit module with the most stringent design rule, the most dense layout of components, the fastest operation speed, and the highest operation power consumption in a chip circuit. The traditional SRAM memory adopts a 6T (6 transistors) structure or an 8T (8 transistors) structure to store 1bit or 2bit data.
The development of microelectronic technology has put demands on higher density, higher operation speed, and lower power consumption, i.e., high energy efficiency, on SRAM. One very effective solution is to reduce the power consumption of the cell by a square factor by reducing the operating voltage Vdd of the SRAM. However, reducing the operating voltage presents many challenges to the conventional 6T/8T structure, and a more serious challenge is that the noise margin window (SNM) of the memory cell is reduced, so that the new type of memory cell stored in the SRAM cell is easily disturbed and lost, as shown in fig. 1. The SRAM stores information in the form of voltages of the storage node Q and the storage node Qb. The better SNM can ensure that the voltages of the storage node Q and the storage node Qb are as expected by design without logic errors. Three common operating modes of SRAM are Write operation (Write), Read operation (Read), Hold operation (Hold). During the write operation, the Word Line (WL) is turned on, and the VQ and VQB can reach the expected voltage by applying external high and low voltages through Vbl, at the moment, the pull-up capability of PMOS will affect the noise margin during the write, and usually VQ and VQB can reach 0 and Vdd respectively; during holding operation, voltage stabilization is realized through an inverter, VQ and VQB can be maintained at 0 and Vdd, and SNM is mainly influenced by threshold voltage; during a read operation, the voltage at Q, Qb needs to be redistributed by two turned-on NMOS transistors, and VQ and VQB are at an intermediate voltage and are very easy to be disturbed to cause logic errors. Therefore, in general, the SNM in the read operation is the worst, the SNM in the write operation is general, and the SNM in the hold state is the optimum. In a low power design, when Vdd is reduced, the interference rejection capability is reduced (as shown in fig. 1 and 2), and it is more obvious that the read operation is a short plate of SNM.
Disclosure of Invention
The present application provides a cell structure of a static random access memory and a static random access memory. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a sram cell structure, including a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS transistor, and a fourth fully depleted silicon-on-insulator NMOS transistor;
the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the first phase inverter;
the source/drain of the third fully depleted silicon-on-insulator NMOS transistor is connected with the output end of the first inverter, the drain/source of the third fully depleted silicon-on-insulator NMOS transistor is connected with a write bit line, and the gate and the back gate of the third fully depleted silicon-on-insulator NMOS transistor are respectively connected with a write word line;
the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the back gate of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line; and the drain/source of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read bit line, and the source/drain of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line.
Further, the SRAM unit structure further comprises a fifth fully depleted silicon-on-insulator NMOS transistor;
the grid electrode and the back gate of the fifth fully depleted silicon-on-insulator NMOS tube are respectively connected with a write word line, the source electrode/drain electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with a write bit line.
Further, the first phase inverter comprises a first fully depleted silicon-on-insulator PMOS tube and a first fully depleted silicon-on-insulator NMOS tube, a drain of the first fully depleted silicon-on-insulator PMOS tube is connected with a drain of the first fully depleted silicon-on-insulator NMOS tube, a gate of the first fully depleted silicon-on-insulator PMOS tube is connected with a gate of the first fully depleted silicon-on-insulator NMOS tube, the gate of the first fully depleted silicon-on-insulator PMOS tube is connected with an input end of the first phase inverter, and the drain of the first fully depleted silicon-on-insulator PMOS tube is connected with an output end of the first phase inverter.
Further, the back gate of the first fully depleted silicon-on-insulator PMOS transistor is connected with the source of the first fully depleted silicon-on-insulator PMOS transistor.
Further, the back gate of the first fully depleted silicon-on-insulator NMOS transistor is connected with the source of the first fully depleted silicon-on-insulator NMOS transistor.
Further, the second inverter comprises a second fully depleted silicon-on-insulator PMOS transistor and a second fully depleted silicon-on-insulator NMOS transistor, a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to a drain of the second fully depleted silicon-on-insulator NMOS transistor, a gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to a gate of the second fully depleted silicon-on-insulator NMOS transistor, the gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to an input terminal of the second inverter, and a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to an output terminal of the second inverter.
Further, the back gate of the second fully depleted silicon-on-insulator PMOS transistor is connected with the source of the second fully depleted silicon-on-insulator PMOS transistor.
Further, the back gate of the second fully depleted silicon-on-insulator NMOS transistor is connected with the source of the second fully depleted silicon-on-insulator NMOS transistor.
According to another aspect of the present invention, an sram is provided, which includes a plurality of the above sram cell structures.
According to another aspect of the embodiments of the present application, there is provided a memory device including the above-mentioned sram.
The technical scheme provided by one aspect of the embodiment of the application can have the following beneficial effects:
the SRAM unit structure provided by the embodiment of the application adopts the fully depleted silicon-on-insulator MOS tube, can ensure static noise margin in a holding state, improves the anti-interference capability in a reading state, improves the reading and writing speeds of the memory under the condition of high-density integration, and realizes the operation of the SRAM unit structure under low voltage.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 illustrates a bit line voltage butterfly line schematic of a prior art SRAM cell structure;
FIG. 2 shows a graph of data storage point voltages for a prior art SRAM cell structure during a read operation phase and a state retention phase;
FIG. 3 shows a circuit diagram of an SRAM cell structure of one embodiment of the present application;
FIG. 4 is a circuit diagram of an SRAM cell structure of another embodiment of the present application;
FIG. 5 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator PMOS transistor;
figure 6 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator NMOS transistor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
One embodiment of the present application provides a static random access memory cell structure, comprising a first inverter, a second inverter, a third fully depleted silicon-on-insulator NMOS transistor, and a fourth fully depleted silicon-on-insulator NMOS transistor;
the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the first phase inverter;
the source/drain of the third fully depleted silicon-on-insulator NMOS transistor is connected to the output of the first inverter,
the drain/source of the third fully depleted silicon-on-insulator NMOS transistor is connected with a write bit line, and the gate and the back gate of the third fully depleted silicon-on-insulator NMOS transistor are respectively connected with a write word line;
the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second inverter, and the back gate of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line; and the drain/source of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read bit line, and the source/drain of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line.
The P-type transistors in the embodiments of the present application are all fully depleted silicon-on-insulator PMOS transistors, and the N-type transistors are all fully depleted silicon-on-insulator NMOS transistors.
An SRAM cell structure according to the embodiment shown in fig. 3 adopts a 6T structure, an FDSOI structure, and a structure topology and back bias (back bias) voltage optimization. The SRAM memory cell is composed of 6 field effect transistors, wherein the 6 field effect transistors comprise 2P type transistors P1 and P2, and 4N type transistors N1, N2, N3 and N4.
P1 and N1 form an inverter, which is called a first inverter; p2 and N2 form an inverter, called the second inverter; the output of the first inverter is used as the input of the second inverter, and the output of the second inverter is used as the input of the first inverter, so that the first inverter and the second inverter form a cross-coupled structure, and a first storage node Q and a second storage node Qb are formed, wherein the first storage node Q is the output end of the first inverter, and the second storage node Qb is the output end of the second inverter.
The source (or drain) of N3 is connected with the output end of the first inverter; the output of the second inverter is connected to the gate of N4. The first inverter shares the same power and ground with the second inverter. The gate of N3 is connected to the Write Word Line (WWL), the drain is connected to the Write Bit Line (WBL), and the source of N4 is connected to the Read Word Line (RWL), the drain is connected to the Read Bit Line (RBL). N3 is used for control of write operations and N4 is used for control of read operations.
Due to the adoption of the FDSOI structure, compared with the traditional bulk silicon structure, the quiescent current and the power consumption of the node are lower.
The read operation can be separated from the write operation by N4 and N3 (decoupling). When the read operation is performed, the Q or Qb terminal is connected with the gate of N4, the voltage division competition of two transistors in the traditional structure can not occur, the voltage at Q, Qb can be maintained at the ground terminal or the high-voltage terminal, and the read SNM is improved.
When a write operation is performed, a write voltage can be applied to an inverter pair including a first inverter and a second inverter by opening WWL control N3.
Preferably, the introduction of N3 into the high voltage back bias can effectively reduce the threshold voltage of N3 (to 0), and as shown in fig. 5, the lossless transfer of N3 voltage (regardless of high voltage and low voltage) can be realized. Meanwhile, the driving capability of the N3 is stronger, which is beneficial to faster writing.
Preferably, the introduction of N4 into the back bias RWL can lower the N4 threshold and raise the driving capability of N4 when performing a write operation, thereby increasing the read rate without affecting the SNM during read.
In some embodiments, the sram cell structure further comprises a fifth fully depleted silicon-on-insulator NMOS transistor; the grid electrode and the back gate of the fifth fully depleted silicon-on-insulator NMOS tube are respectively connected with a write word line, the source electrode/drain electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with a write bit line.
An SRAM cell structure according to the embodiment shown in fig. 4 adopts a 7T structure, an FDSOI structure, and a structure topology and back bias (back bias) voltage optimization. Meanwhile, the threshold loss possibly existing in the read-out operation is considered, a symmetrical write-in structure is adopted, and the SNM in the write-in process is ensured as much as possible.
The SRAM memory cell is composed of 7 field effect transistors, wherein the 7 field effect transistors comprise 2P type transistors P1 and P2, and 4N type transistors N1, N2, N3, N4 and N5.
P1 and N1 form an inverter, which is called a first inverter; p2 and N2 form an inverter, called the second inverter; the output of the first inverter is used as the input of the second inverter, and the output of the second inverter is used as the input of the first inverter, so that the first inverter and the second inverter form a cross-coupled structure, and a first storage node Q and a second storage node Qb are formed, wherein the first storage node Q is the output end of the first inverter, and the second storage node Qb is the output end of the second inverter.
The source (or drain) of N3 is connected with the output end of the first inverter; the output of the second inverter is connected to the gate of N4. The first inverter shares the same power and ground with the second inverter. The gate of N3 is connected to the Write Word Line (WWL), the drain is connected to the Write Bit Line (WBL), and the source of N4 is connected to the Read Word Line (RWL), the drain is connected to the Read Bit Line (RBL). N3 is used for control of write operations and N4 is used for control of read operations.
The source (or drain) of N5 is connected to the output terminal of the second inverter, the gate of N5 is connected to WWL, and the third terminal of N5 is connected to WBL. The same electrical parameters are adopted for P1 and P2, the same electrical parameters are adopted for N1 and N2, and the same electrical parameters are adopted for N3 and N4. N1, N3, N5 may employ different electrical parameters, such as transistor threshold voltages. Fig. 5 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator PMOS transistor, showing the substrate 1, the nwell layer 2, the insulating layer 3, the back gate 4, the gate 5, the source 6 and the drain 7; fig. 6 shows a schematic cross-sectional view of a fully depleted silicon-on-insulator NMOS transistor, showing the substrate 1, the deep N-well layer 8, the insulating layer 3, the back gate 4, the gate 5, the source 6 and the drain 7.
In some embodiments, the first inverter includes a first fully depleted silicon-on-insulator PMOS transistor and a first fully depleted silicon-on-insulator NMOS transistor, a drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to a drain of the first fully depleted silicon-on-insulator NMOS transistor, a gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to a gate of the first fully depleted silicon-on-insulator NMOS transistor, a gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to an input of the first inverter, and a drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to an output of the first inverter.
In some embodiments, the back gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to the source of the first fully depleted silicon-on-insulator PMOS transistor.
In some embodiments, the back gate of the first fully depleted silicon-on-insulator NMOS transistor is connected to the source of the first fully depleted silicon-on-insulator NMOS transistor.
In some embodiments, the second inverter includes a second fully depleted silicon-on-insulator PMOS transistor and a second fully depleted silicon-on-insulator NMOS transistor, a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to a drain of the second fully depleted silicon-on-insulator NMOS transistor, a gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to a gate of the second fully depleted silicon-on-insulator NMOS transistor, a gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to an input of the second inverter, and a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to an output of the second inverter.
In some embodiments, the back gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to the source of the second fully depleted silicon-on-insulator PMOS transistor.
In some embodiments, the back gate of the second fully depleted silicon-on-insulator NMOS transistor is connected to the source of the second fully depleted silicon-on-insulator NMOS transistor.
In order to enable the SRAM to work under low voltage, even under a device subthreshold, the embodiment of the present application provides an SRAM cell structure based On an FDSOI (Fully depleted silicon On Insulator) field effect transistor, and separates read and write states through optimization of a circuit topology, and simultaneously, by using a back bias design, a static noise margin in a holding state can be ensured, an anti-interference capability in a read state can be improved, a speed of reading and writing of a memory can be improved under a high density integration condition, and the SRAM cell structure can work under low voltage.
Another embodiment of the present application provides an sram including a plurality of sram cell structures according to any one of the above embodiments.
Another embodiment of the present application provides a memory device including the sram of any one of the above embodiments.
Compared with the traditional bulk silicon SRAM structure, the embodiment of the application adopts the SRAM with the FDSOI structure, and can improve the noise capacity of a read-out state under the condition of ensuring the static noise tolerance of the SRAM through the optimization of circuit topology and the optimization of back bias, and simultaneously improve the writing-in and reading-out speeds of the SRAM under the condition of not sacrificing the anti-interference capacity. Meanwhile, the increase of the unit area is not obvious due to the adoption of a 6T or 7T structure.
It should be noted that:
the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance. It should also be understood that, although the terms "first," "second," "third," etc. may be used herein in some of the present application embodiments to describe various objects, these objects should not be limited by these terms. These terms are used only to distinguish various objects.
The above-mentioned embodiments only express the embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A static random access memory unit structure is characterized by comprising a first phase inverter, a second phase inverter, a third fully depleted silicon-on-insulator NMOS tube and a fourth fully depleted silicon-on-insulator NMOS tube;
the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the first phase inverter;
the source/drain of the third fully depleted silicon-on-insulator NMOS transistor is connected with the output end of the first inverter, the drain/source of the third fully depleted silicon-on-insulator NMOS transistor is connected with a write bit line, and the gate and the back gate of the third fully depleted silicon-on-insulator NMOS transistor are respectively connected with a write word line;
the grid electrode of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the back gate of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line; and the drain/source of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read bit line, and the source/drain of the fourth fully depleted silicon-on-insulator NMOS tube is connected with the read word line.
2. The sram cell structure of claim 1, further comprising a fifth fully depleted silicon-on-insulator NMOS transistor;
the grid electrode and the back gate of the fifth fully depleted silicon-on-insulator NMOS tube are respectively connected with a write word line, the source electrode/drain electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with the output end of the second phase inverter, and the drain electrode/source electrode of the fifth fully depleted silicon-on-insulator NMOS tube is connected with a write bit line.
3. The SRAM cell structure of claim 1, wherein the first inverter comprises a first fully depleted silicon-on-insulator PMOS transistor and a first fully depleted silicon-on-insulator NMOS transistor, a drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to a drain of the first fully depleted silicon-on-insulator NMOS transistor, a gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to a gate of the first fully depleted silicon-on-insulator NMOS transistor, a gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to an input of the first inverter, and a drain of the first fully depleted silicon-on-insulator PMOS transistor is connected to an output of the first inverter.
4. The SRAM cell structure of claim 3, wherein the back gate of the first fully depleted silicon-on-insulator PMOS transistor is connected to the source of the first fully depleted silicon-on-insulator PMOS transistor.
5. The SRAM cell structure of claim 3, wherein the back gate of the first fully depleted silicon-on-insulator NMOS transistor is connected to the source of the first fully depleted silicon-on-insulator NMOS transistor.
6. The SRAM cell structure of claim 1, wherein the second inverter comprises a second fully depleted silicon-on-insulator PMOS transistor and a second fully depleted silicon-on-insulator NMOS transistor, a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to a drain of the second fully depleted silicon-on-insulator NMOS transistor, a gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to a gate of the second fully depleted silicon-on-insulator NMOS transistor, a gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to an input of the second inverter, and a drain of the second fully depleted silicon-on-insulator PMOS transistor is connected to an output of the second inverter.
7. The SRAM cell structure of claim 6, wherein a back gate of the second fully depleted silicon-on-insulator PMOS transistor is connected to a source of the second fully depleted silicon-on-insulator PMOS transistor.
8. The SRAM cell structure of claim 6, wherein the back gate of the second fully depleted silicon-on-insulator NMOS transistor is connected to the source of the second fully depleted silicon-on-insulator NMOS transistor.
9. SRAM comprising a number of SRAM cell structures as claimed in any one of claims 1 to 8.
10. A memory device comprising the sram of claim 9.
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| US20140016402A1 (en) * | 2012-07-13 | 2014-01-16 | James D. Burnett | Sram bit cell with reduced bit line pre-charge voltage |
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