CN110232941B - Hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement - Google Patents
Hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement Download PDFInfo
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The invention discloses a mixed 10T TFET-MOSFET SRAM unit circuit with low power consumption and write enhancement, which uses a bi-directional conduction NMOSFET to replace a TFET as an access tube of the SRAM unit. The method utilizes the characteristics of bidirectional conduction of the MOSFET, has the advantages of lower threshold voltage, smaller leakage current, lower turn-off current, higher switching current ratio and the like compared with the MOSFET, reduces the static power consumption of the SRAM of the TFET, and simultaneously reduces the unit leakage current in a holding state; the storage node is separated from the reading path by utilizing read-write separation, so that the reading stability is improved; from the simulation result of the writing speed of the unit, the lower the working voltage of the unit is, the faster the writing speed is; the static power consumption of the TFET SRAM unit structure is reduced by at least 2 orders of magnitude compared with that of the 6T TFET SRAM unit structure under the same working voltage, such as 0.4V to 0.9V, the writing margin of the TFET SRAM unit is improved, the static power consumption of the unit is reduced, and the writing capability and writing speed of the unit are improved.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a mixed 10T TFET-MOSFET SRAM unit circuit with low power consumption and write enhancement.
Background
With the rapid development of the integrated circuit industry and the wide application of the SOC (System On Chip) system, the current market demands for low-power devices are becoming serious. Most of the digital integrated circuits and analog integrated circuit devices are composed of metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFETs), which are not ideal in the low power consumption field all the time with the update of microelectronics technology and the continuous improvement of semiconductor device technology. The subthreshold swing of the MOSFET cannot be lower than 60mv/decade at room temperature, which seriously affects the switching rate of the MOSFET device under the corresponding gate voltage, so that the static leakage current of the MOSFET increases exponentially along with the reduction of the power supply voltage, and the static power consumption increases exponentially. In the memory chips used in various SOCs, however, SRAM occupies a proportion of about 70% and consumes most of its static power consumption due to its unique advantages.
Based on the above drawbacks of MOSFETs, methods for reducing static power consumption of SRAM have been explored. For example, the working voltage is reduced, the size of a MOSFET is reduced, the switching current ratio is reduced, the leakage current is increased, and along with the great reduction of the power supply voltage, the influence of environmental parameters and process deviation on the performance of a subthreshold circuit is also exponentially changed, so that fatal functional errors of a memory cell with a traditional structure are extremely easy to occur; the MOSFET process size is reduced, and the turn-off capability of the MOSFET is weakened under the subthreshold working voltage due to the short channel effect, so that the static leakage current and the static power consumption of the circuit are increased. Compared with a MOSFET, a Tunneling Field Effect Transistor (TFET) process is short in manufacturing period and low in working voltage, current is generated through a band-to-band Tunneling effect, the current is formed in a mode that the current is different from a mode that a traditional MOSFET depends on carrier drift diffusion, and the static power consumption of the TFET is very small due to the unique device structure. These advantages of TFETs with lower subthreshold swing and higher switching current ratio than MOSFETs make TFETs potentially showing great potential to replace MOSFETs in low power consumption applications. However, the unidirectional conduction (unidirectional conduction) characteristic of the TFET limits the application of the TFET in the SRAM, when a forward bias voltage is applied to the gate of the TFET tube, the TFET tube can generate forward leakage current which is not controlled by the gate voltage, and the forward leakage current can occur when the TFET is applied to the SRAM as an access tube, so that the static power consumption of the SRAM is increased. And thus affect the retention, reading, etc. of the cell, which may cause serious damage to SRAM circuit performance.
As shown in fig. 1, in the conventional 6T TFET SRAM cell structure, the sources of the two TFET access transistors are respectively connected to the bit lines BL and BLB, and due to the unidirectional conduction characteristics of the TFETs, the conventional 6T TFET SRAM is difficult to achieve ideal read, write and hold functions, and the conventional 6T TFET SRAM structure has good write capability, but the read operation is poor, even resulting in read errors and unreadable operations.
Disclosure of Invention
The invention aims to provide a mixed 10T TFET-MOSFET SRAM unit circuit with low power consumption and enhanced writing, which uses an NMOSFET transistor as an access tube, thereby improving the reading and writing capacity of the SRAM unit, avoiding the problem of forward leakage current when the TFET is used as the SRAM access tube, reducing the static power consumption of the SRAM unit and improving the writing capacity and writing speed of the SRAM unit.
The invention aims at realizing the following technical scheme:
a hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement, comprising: five NTFET transistors, three PTFET transistors, and two MOSFET transistors; five NTFET transistors are sequentially marked as N1-N5, three PTFET transistors are sequentially marked as P1-P3, and two MOSFET transistors are respectively marked as N6 and N7; wherein:
VDD and the sources of PTFET transistors P1 and P3 are electrically connected, and the source of PTFET transistor P1 is electrically connected to the source of PTFET transistor P3;
the drain of PTFET transistor P1 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P2 is electrically connected to the drain of NTFET transistor N2;
a drain of the PTFET transistor P3 is electrically connected to a drain of the NTFET transistor N3 and a gate of the NTFET transistor N4;
the drain of NTFET transistor N1 is electrically connected to the source of NTFET transistor N2;
the drain of NTFET transistor N4 is electrically connected to the source of NTFET transistor N5;
the drain electrode of the NMOSFET transistor N6 is electrically connected with the source electrode of the NMOSFET transistor N7;
the sources of the NTFET transistors N1, N3, and N4 are all electrically connected to GND.
According to the technical scheme provided by the invention, the advantages of the conventional MOSFET in bidirectional conduction and the advantages of smaller subthreshold swing and higher switching current ratio than the MOSFET of the TFET are combined, so that the problem of high static power consumption of the conventional 6T TFET SRAM is solved, and the writing speed and writing capacity of the TFET SRAM are improved. At the same operating voltage, such as 0.4V to 0.9V, the static power consumption is reduced by at least 2 orders of magnitude compared with the traditional 6T TFET SRAM, and at 0.7V, the static power consumption is reduced by at least 5 orders of magnitude. The write margin of the TFET SRAM unit is improved; the forward bias leakage current problem when the TFET is used as an SRAM cell access tube is avoided, the static power consumption of the TFET SRAM cell is reduced, and the writing capacity and writing speed of the cell are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a circuit structure of a conventional 6T TFET SRAM cell provided by the background of the invention;
FIG. 2 is a schematic diagram of a low power, write-enhanced hybrid 10T TFET-MOSFET SRAM cell circuit according to an embodiment of the present invention;
fig. 3 is a data diagram comparing a write margin of a hybrid 10T TFET SRAM cell circuit with a write margin of a 6T TFET SRAM cell provided by an embodiment of the present invention;
fig. 4 is a data diagram comparing a retention margin of a hybrid 10T TFET SRAM cell circuit with a retention margin of a 6T TFET SRAM cell provided by an embodiment of the present invention;
fig. 5 is a data diagram comparing static power consumption of a hybrid 10T TFET SRAM cell circuit with static power consumption of a 6T TFET SRAM cell provided by an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The basic devices used in the traditional 6T TFET SRAM cell circuit are TFET, and the basic devices used in the mixed 10T TFET SRAM cell circuit provided by the invention are Tunneling Field Effect Transistors (TFET) and Metal Oxide Semiconductor Field Effect Transistors (MOSFET). The static power consumption of the SRAM is increased by the forward bias current of the TFET as an access tube of the SRAM due to its forward bias voltage while in a retention state. The unidirectional conduction characteristics of TFETs make them unsuitable for use as access tubes for SRAMs, as this can make it difficult for conventional 6T SRAM structures to simultaneously maintain good read and write operations, and conventional 6T SRAMs require access tubes with bidirectional conduction capabilities. The mixed 10T TFET SRAM unit circuit with low power consumption and enhanced writing not only improves the reading and writing capability of the TFET SRAM, but also avoids the problem of forward bias leakage current when the TFET is used as an SRAM access tube, reduces the static power consumption of the SRAM unit and improves the writing capability and writing speed of the unit.
As shown in fig. 2, it mainly includes: five NTFET transistors, three PTFET transistors, and two MOSFET transistors; five NTFET transistors are sequentially marked as N1-N5, three PTFET transistors are sequentially marked as P1-P3, and two MOSFET transistors are respectively marked as N6 and N7; the main results are as follows:
VDD and the sources of PTFET transistors P1 and P3 are electrically connected, and the source of PTFET transistor P1 is electrically connected to the source of PTFET transistor P3;
the drain of PTFET transistor P1 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P2 is electrically connected to the drain of NTFET transistor N2;
a drain of the PTFET transistor P3 is electrically connected to a drain of the NTFET transistor N3 and a gate of the NTFET transistor N4;
the drain of NTFET transistor N1 is electrically connected to the source of NTFET transistor N2;
the drain of NTFET transistor N4 is electrically connected to the source of NTFET transistor N5;
the drain electrode of the NMOSFET transistor N6 is electrically connected with the source electrode of the NMOSFET transistor N7;
the sources of the NTFET transistors N1, N3, and N4 are all electrically connected to GND.
Further, the write bit line WBL is electrically connected to the source of the NMOSFET transistor N6; the write bit line WBLB is connected with the gate of the NMOSFET transistor N6; the bit line PCL is connected with the grid electrode of the PTFET transistor P2; the bit line NCL is connected with the grid electrode of the NTFET transistor N2; the write word line WWL is connected to the gate of the NMOSFET transistor N7; the read word line RWL is connected to the gate of the NTFET transistor N5; the read bit line RBL is connected to the drain of NTFET transistor N5.
In the above-mentioned mixed 10T TFET SRAM cell circuit structure, PTFET transistors P1, P2 and NTFET transistors N1 and N2, and PTFET transistor P3 and NTFET transistor N3 constitute two inverters; the PTFET transistor P2 and the NTFET transistor N2 break the latch structure during writing operation, so that the purposes of improving the writing capability and the writing speed when the unit performs writing operation can be achieved; the NTFET transistors N4 and N5 form a read-write separation mode for read operation, and the read capacity and the read speed of the SRAM unit can be improved by adopting the structure; the NMOSFET transistors N6 and N7 are connected in series to eliminate the forward bias leakage current problem which is not controlled by the gate voltage when TFETs are used as SRAM access transistors.
The principle of the mixed 10T TFET SRAM unit circuit provided by the embodiment of the invention is as follows:
1. in the hold state, the write bit line WBLB, write word line WWL, and bit line PCL are low, while the NMOSFET transistors N6 and N7 are off, and the NTFET transistors N2 and PTFET transistor P2 are on;
based on the structure shown in fig. 2, the adopted access tube is an NMOSFET, so that the problem of forward bias leakage current caused by using a TFET as the access tube can be effectively avoided.
2. Write operation: 1) When the SRAM cell circuit performs a write 0 operation, it is assumed that a node Q in an inverter composed of PTFET transistor P2 and NTFET transistor N2 is stored 1, and a node QB in an inverter composed of PTFET transistor P3 and NTFET transistor N3 is stored 0; at this time, the write bit line WBLB and the write word line WWL are both set to high level, the bit line PCL is set to high level, and the write bit line WBL is set to low level; the NMOSFET transistors N6 and N7 are turned on, at this time the PTFET transistor P2 is turned off, the NTFET transistor N2 is turned on, the node Q discharges to the write bit line WBL through the NMOSFET transistors N6 and N7, the node Q voltage discharges to a low level, and the node QB voltage is turned to a high level accordingly. The write capability of the cell is improved by writing 0 in a manner of breaking latch. After the write 0 operation is completed, the write bit line WBLB and the write word line WWL are set to low. 2) When the SRAM unit circuit performs a write 1 operation, assuming that a node Q is stored 0, a node QB is stored 1, write bit lines WBL and WBLB and a write word line WWL are all set to be high, a bit line NCL is set to be low, NMOSFET transistors N6 and N7 are turned on, a PTFET transistor P2 is turned on, and at the moment, the NTFET transistor N2 is turned off; the write bit line WBL charges the node Q through the NMOSFET transistors N6 and N7 so that the node Q voltage rises to a high level while the node QB point is flipped to 0, thereby completing the write 1 operation.
3. Holding operation: hold refers to the data stored by storage nodes Q and QB remaining unchanged while the SRAM cell circuit is not being accessed by the outside world. Assuming that the data stored in the storage node Q is 1, in this mode, as shown in fig. 2, the write bit line WBL of the cell is set to high, the write bit line WBLB is set to low, and the write word line WWL and the read word line RWL are not turned on during this period, both are set to low. The bit line PCL is set low and the bit line NCL is set high. PTFET transistors P1 and P2 are on, PTFET transistor P3 is off, NTFET transistors N2 and N3 are on, NTFET transistors N1 and N5 are off, and two access NMOSFET transistors N6 and N7 are in an off state; thus, paths between the bit line WBL and the storage nodes Q and QB are cut off, and the paths are not mutually influenced under the ideal condition of the external environment; the data stored by Q and QB are latched by a latch formed by two cross-coupled inverters, so that the aim of unchanged stored information is fulfilled.
4. Read operation: assume that node Q stores data of 0; when the SRAM unit circuit performs a read operation, the read bit line RBL is precharged to a high level, the write bit line WBLB, the write word line WWL and the bit line PCL are set to a low level, and the write bit line WBL and the bit line NCL are set to a high level; node QB stores data 1, NTFET transistor N4 is turned on, read word line RWL is set to high level, NTFET transistor N5 is turned on, read bit line RBL is discharged to low level through NTFET transistors N4 and N5, and sense amplifier in the SRAM array detects a change in level on read bit line RBL to realize reading of the stored data of the SRAM cell circuit.
In order to clearly show the technical scheme and the technical effects provided by the invention, the performance of the unit circuit provided by the embodiment of the invention is compared with other TFET SRAM units; the concrete contents are as follows:
(1) As shown in fig. 3, a comparison of the write noise margin of two TFET SRAM cells is shown. The write noise margin (denoted as WSNM) is obtained by a bit line scan method. According to experimental simulation results, it can be seen from the graph that the mixed 10T TFET unit circuit provided by the invention has a larger write margin than that of a 6T TFET unit structure. At an operating voltage of 0.6V, the write margin of the proposed hybrid 10T TFET-MOSFET SRAM is twice that of the conventional 6T TFET SRAM; this is because the structure proposed by the present invention breaks the latch with the PTFET transistor P2 and the NTFET transistor N2 at the time of performing the write operation, improving the cell writing capability and writing speed.
(2) As shown in fig. 4, a comparison of the retained static noise margin of two TFET SRAM cells is shown. The hold static noise margin (denoted as HSNM) is obtained by the VTC curve. According to experimental simulation results, when the working voltage is 0.5V to 0.9V, the holding margin of the 6T TFET SRAM unit is continuously reduced after the working voltage is higher than 0.6V, and the holding margin is only 103.4mv under the working voltage of 0.9V, but the holding margin of the mixed 10T TFET-MOSFET SRAM unit circuit is continuously increased along with the increase of the working voltage. When the operating voltage was 0.9V, the holding margin was 245.2mv. The hybrid 10T TFET-MOSFET SRAM cell presented herein has a stronger retention stability compared to a 6T TFET SRAM cell.
(3) As shown in table 1, the write "1" speed of two TFET SRAM cells is demonstrated. According to experimental simulation results, the mixed 10T TFET unit circuit provided by the invention has a faster writing speed of 1. The proposed write "1" speed for a hybrid 10T TFET cell is 0.01ns and the write "1" speed for a 6T TFET cell is 1.6ns at an operating voltage of 0.3V, the two differing by at least 3 orders of magnitude. It can thus be seen that the structure presented herein has great advantages over 6T TFET cells in writing speed at low operating voltages.
Table 1 write 1 speed comparison results
(4) As shown in table 2, the write "0" speed of two TFET SRAM cells is demonstrated. According to experimental simulation results, the mixed 10T TFET unit circuit provided by the invention is compared with a 6T TFET unit, and the 10T TFET unit has a faster writing '0'. At the same time, comparing the data graphs of the write "1" speed and the write "0" speed, it can be seen that the cell structure proposed herein has at least a double increase in the write "0" speed over the write "1" speed.
Table 2 write 0 speed versus comparison results
(5) As shown in table 3, the read "0" speed of two TFET SRAM cells is demonstrated. According to experimental simulation results, the mixed 10T TFET unit circuit provided by the invention has a faster reading speed of 0. At 0.6V operating voltage, the read "0" speed of the 6T TFET SRAM cell is 51.8ns, while the read "0" speed of the hybrid 10T cell is 0.69ns, which is nearly 80 times higher than the former. The source of the access tube of the 6T TFET SRAM cell is externally connected to a bit line, assuming that the storage node Q stores a "1" and QB stores a "0", and when a read operation is performed, the bit line BLB is high, discharging radially through the NTFET transistors AR, NR paths. The level change of the bit line BLB may be detected by a sense amplifier in the SRAM array. Thereby completing the read operation. This read method operates with exactly the forward bias current of the TFET. As the operating voltage decreases, the forward bias current becomes smaller, which makes read operations difficult and may cause read errors. Therefore, the read-write separation structure is adopted by the unit provided by the invention, and the NTFET transistors N4 and N5 are used for reading, so that the reading capability of the unit is greatly improved. The problems of difficult cell reading and reading errors are solved.
Table 3 reads the 0 speed comparison results
(6) As shown in fig. 5, the static power consumption of both types of cells in the hold state is demonstrated. According to experimental simulation results, as the working voltage of the 6T TFET SRAM unit increases, the leakage current of the 6T TFET SRAM unit in a holding state increases. The static power consumption thereof increases by orders of magnitude without eliminating the forward bias. However, the mixed 10T TFET SRAM unit circuit provided by the invention adopts two NMOSFETs connected in series as the access tube, so that the forward bias problem of the TFET is effectively solved, the NMOSFETs are conducted in two directions and controllable, and the advantage exactly overcomes the defect that the forward bias leakage current is not controlled by the gate voltage due to the unidirectional conduction characteristic of the TFET. Therefore, as the cell operating voltage increases, the static power consumption of the memory cell does not increase much, and compared with a 6T TFET SRAM cell, the cell structure provided herein reduces the static power consumption by at least 2 orders of magnitude at 0.4V operating voltage and reduces the static power consumption by at least 5 orders of magnitude at 0.7V operating voltage.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (1)
1. A hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement, comprising: five NTFET transistors, three PTFET transistors, and two MOSFET transistors; five NTFET transistors are sequentially marked as N1-N5, three PTFET transistors are sequentially marked as P1-P3, and two MOSFET transistors are respectively marked as N6 and N7; wherein:
VDD and the sources of PTFET transistors P1 and P3 are electrically connected, and the source of PTFET transistor P1 is electrically connected to the source of PTFET transistor P3;
the drain of PTFET transistor P1 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P2 is electrically connected to the drain of NTFET transistor N2;
a drain of the PTFET transistor P3 is electrically connected to a drain of the NTFET transistor N3 and a gate of the NTFET transistor N4;
the drain of NTFET transistor N1 is electrically connected to the source of NTFET transistor N2;
the drain of NTFET transistor N4 is electrically connected to the source of NTFET transistor N5;
the drain electrode of the NMOSFET transistor N6 is electrically connected with the source electrode of the NMOSFET transistor N7;
the sources of the NTFET transistors N1, N3, and N4 are all electrically connected to GND;
the write bit line WBL is electrically connected to the source of the NMOSFET transistor N6; the write bit line WBLB is connected with the gate of the NMOSFET transistor N6; the bit line PCL is connected with the grid electrode of the PTFET transistor P2; the bit line NCL is connected with the grid electrode of the NTFET transistor N2; the write word line WWL is connected to the gate of the NMOSFET transistor N7; the read word line RWL is connected to the gate of the NTFET transistor N5; the read bit line RBL is connected with the drain electrode of the NTFET transistor N5;
in the hold state, the write bit line WBLB, write word line WWL, and bit line PCL are low, while the NMOSFET transistors N6 and N7 are off, and the NTFET transistors N2 and PTFET transistor P2 are on;
write operation: (1) When the SRAM cell circuit performs a write 0 operation, it is assumed that a node Q in an inverter composed of PTFET transistor P2 and NTFET transistor N2 is stored 1, and a node QB in an inverter composed of PTFET transistor P3 and NTFET transistor N3 is stored 0; at this time, the write bit line WBLB and the write word line WWL are both set to high level, the bit line PCL is set to high level, and the write bit line WBL is set to low level; NMOSFET transistors N6 and N7 are turned on, at this time PTFET transistor P2 is turned off, NTFET transistor N2 is turned on, node Q discharges to write bit line WBL through NMOSFET transistors N6 and N7, node Q voltage discharges to the low level, node QB voltage turns over to the high level accordingly, after write 0 operation is finished, write bit line WBLB and write word line WWL are set to the low level; (2) When the SRAM unit circuit performs a write 1 operation, assuming that a node Q is stored 0, a node QB is stored 1, write bit lines WBL and WBLB and a write word line WWL are all set to be high, a bit line NCL is set to be low, NMOSFET transistors N6 and N7 are turned on, a PTFET transistor P2 is turned on, and at the moment, the NTFET transistor N2 is turned off; the write bit line WBL charges the node Q through NMOSFET transistors N6 and N7, so that the voltage of the node Q rises to a high level, and meanwhile, the node QB is turned to a low level, thereby completing the write 1 operation;
holding operation: the holding means that the data stored by the nodes Q and QB are kept unchanged when the SRAM unit circuit is not accessed by the outside; assuming that the data stored in the storage node Q is 1, the write bit line WBL is set to a high level, the write bit line WBLB is set to a low level, the write word line WWL and the read word line RWL are not turned on during this period, both are set to a low level, the bit line PCL is set to a low level, and the bit line NCL is set to a high level; PTFET transistors P1 and P2 are on, PTFET transistor P3 is off, NTFET transistors N2 and N3 are on, NTFET transistors N1 and N5 are off, and two access NMOSFET transistors N6 and N7 are in an off state; thus, the paths between the bit line WBL and the nodes Q and QB are cut off, and the paths are not mutually influenced under the ideal condition of the external environment; the data stored by the nodes Q and QB are latched by a latch formed by two cross-coupled inverters, so that the stored information is kept unchanged;
read operation: assume that node Q stores data of 0; when the SRAM unit circuit performs a read operation, the read bit line RBL is precharged to a high level, the write bit line WBLB, the write word line WWL and the bit line PCL are set to a low level, and the write bit line WBL and the bit line NCL are set to a high level; node QB stores data 1, NTFET transistor N4 is turned on, read word line RWL is set to high level, NTFET transistor N5 is turned on, read bit line RBL is discharged to low level through NTFET transistors N4 and N5, and sense amplifier in the SRAM array detects a change in level on read bit line RBL to realize reading of the stored data of the SRAM cell circuit.
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| CN201910549755.XA CN110232941B (en) | 2019-06-24 | 2019-06-24 | Hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement |
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