CN113542649A - HDMI signal anti-shake circuit - Google Patents
HDMI signal anti-shake circuit Download PDFInfo
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- CN113542649A CN113542649A CN202010313722.8A CN202010313722A CN113542649A CN 113542649 A CN113542649 A CN 113542649A CN 202010313722 A CN202010313722 A CN 202010313722A CN 113542649 A CN113542649 A CN 113542649A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
- H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
- H04N21/43635—HDMI
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
Abstract
一种高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)信号防抖电路，用以消除HDMI信号抖动，所述HDMI信号防抖电路包括信号源、均衡模块及HDMI连接器，所述信号源、均衡模块及HDMI连接器依次电连接，所述信号源用以输出HDMI信号，所述均衡模块用以接收所述HDMI信号，并对所述HDMI信号进行时钟抖动及时钟偏斜校正，以将校正后的所述HDMI信号输出至所述HDMI连接器。本发明提供的HDMI信号防抖电路，有效避免HDMI信号的大幅度失真，提升了HDMI信号质量。
A high-definition multimedia interface (High Definition Multimedia Interface, HDMI) signal anti-shake circuit for eliminating HDMI signal jitter, the HDMI signal anti-shake circuit includes a signal source, an equalization module and an HDMI connector, the signal source, The equalization module and the HDMI connector are electrically connected in sequence, the signal source is used for outputting the HDMI signal, the equalization module is used for receiving the HDMI signal, and performs clock jitter and clock skew correction on the HDMI signal, so as to correct the HDMI signal. The latter HDMI signal is output to the HDMI connector. The HDMI signal anti-shake circuit provided by the invention can effectively avoid the large-scale distortion of the HDMI signal and improve the quality of the HDMI signal.
Description
Technical Field
The present invention relates to a High Definition Multimedia Interface (HDMI) signal anti-jitter circuit.
Background
In the circuit design of the display screen, an HDMI interface is often used to transmit signals. In the conventional HDMI circuit design, the HDMI signal is prone to large distortion due to large jitter, and integrity of signal transmission cannot be guaranteed, thereby reducing the sound quality and image quality of the video output device.
Disclosure of Invention
In view of the above, the present invention provides an HDMI signal anti-jitter circuit to solve the above problems.
The utility model provides a High Definition Multimedia Interface (HDMI) signal anti-shake circuit for eliminate HDMI signal shake, HDMI signal anti-shake circuit includes signal source, balanced module and HDMI connector, signal source, balanced module and HDMI connector electricity in proper order are connected, the signal source is used for exporting the HDMI signal, balanced module is used for receiving the HDMI signal, and right the HDMI signal carries out clock shake and clock skew correction, in order to be rectified the HDMI signal output extremely the HDMI connector.
Further, the HDMI signal includes first to sixth data signals, a first clock signal, and a second clock signal.
Further, the equalization module is a repeater.
Further, the signal source includes a first data signal pin to a sixth data signal pin, a first clock signal pin and a second clock signal pin, which are respectively used for outputting the first to sixth data signals, the first clock signal and the second clock signal, the repeater includes a first data signal input pin to a sixth data signal input pin, a first clock signal input pin and a second clock signal input pin, the first to sixth data signal input pins are respectively electrically connected to the first data signal to sixth data signal pin, and the first clock signal input pin and the second clock signal input pin are respectively electrically connected to the first clock signal pin and the second clock signal pin.
Further, the repeater further includes first to sixth data signal output pins, a first clock signal output pin, and a second clock signal output pin.
Further, the HDMI connector includes a first data signal receiving pin to a sixth data signal receiving pin, a first clock signal receiving pin and a second clock signal receiving pin, the first to sixth data signal receiving pins are electrically connected to the first to sixth data signal output pins, respectively, and the first clock signal receiving pin and the second clock signal receiving pin are electrically connected to the first clock signal output pin and the second clock signal output pin, respectively.
Furthermore, the HDMI signal anti-shake circuit includes a filter element, the HDMI connector includes a voltage input pin, one end of the filter element is electrically connected to the voltage input pin, and the other end of the filter element is grounded.
Further, the filter element is a capacitor with a capacitance value of 100 nanofarads.
Further, the repeater is a PS8409 chip.
Further, the signal source is a computer, a projector, a monitor, or a set-top box.
According to the HDMI signal anti-shake circuit provided by the invention, the balance module is connected between the signal source and the HDMI connector, so that the shake of the signal sent by the signal source is eliminated, the large-amplitude distortion of the HDMI signal is further avoided, and the quality of the HDMI signal is improved.
Drawings
Fig. 1 is a functional block diagram of an HDMI signal jitter prevention circuit according to a preferred embodiment of the present invention.
Fig. 2 is a circuit diagram of the HDMI signal anti-jitter circuit shown in fig. 1.
Description of the main elements
HDMI signal anti-shake circuit 100
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "electrically connected" to another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "electrically connected" to another element, it can be connected by contact, e.g., by wires, or by contactless connection, e.g., by contactless coupling.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Referring to fig. 1, a High Definition Multimedia Interface (HDMI) signal anti-jitter circuit 100 according to a preferred embodiment of the present invention includes a signal source 10, an equalizing module 20, and an HDMI connector 30. One end of the equalizing module 20 is electrically connected to the signal source 10, and the other end is electrically connected to the HDMI connector 30. In the present embodiment, the equalization module 20 has a function of correcting clock jitter and clock skew, thereby eliminating HDMI signal jitter.
Referring to fig. 2, the signal source 10 is configured to output an HDMI signal. The HDMI signals include first to sixth data signals, a first clock signal, and a second clock signal. In this embodiment, the signal source 10 may be, but is not limited to, a computer. The signal source 10 includes a first data signal pin DPD _ LANE _ DP2_ C, a second data signal pin DPD _ LANE _ DN2_ C, a third data signal pin DPD _ LANE _ DP1_ C, a fourth data signal pin DPD _ LANE _ DN1_ C, a fifth data signal pin DPD _ LANE _ DP0_ C, a sixth data signal pin DPD _ LANE _ DN0_ C, a first clock signal pin DPD _ LANE _ CKP _ C, and a second clock signal pin DPD _ LANE _ CKN _ C for outputting the first to sixth data signals, a first clock signal, and a second clock signal, respectively.
In one embodiment, the equalization module 20 is a repeater 21. One end of the repeater 21 is electrically connected to the signal source 10, and the other end of the repeater is electrically connected to the HDMI connector 30, and is configured to receive the first to sixth data signals, the first clock signal, and the second clock signal output by the signal source 10, perform clock jitter correction and clock skew correction on the first to sixth data signals, the first clock signal, and the second clock signal output by the signal source 10, and transmit the corrected first to sixth data signals, the first clock signal, and the second clock signal to the HDMI connector 30, so that the quality of the audio signal and the image signal output by the HDMI connector 30 is improved.
IN the present embodiment, the input terminals of the repeater 21 include a first data signal input pin IN _ D2P, a second data signal input pin IN _ D2N, a third data signal input pin IN _ D1P, a fourth data signal input pin IN _ D1N, a fifth data signal input pin IN _ D0P, a sixth data signal input pin IN _ D0N, a first clock signal input pin IN _ CKP, and a second clock signal input pin IN _ CKN.
The first data signal input pin IN _ D2P is electrically connected to the first data signal pin DPD _ LANE _ DP2_ C, the second data signal input pin IN _ D2N is electrically connected to the second data signal pin DPD _ LANE _ DN2_ C, the third data signal input pin IN _ D1P is electrically connected to the third data signal DPD _ LANE _ DP1_ C, the fourth data signal input pin IN _ D1N is electrically connected to the fourth data signal DPD _ LANE _ DN1_ C, the fifth data signal input pin IN _ D0P is electrically connected to the fifth data signal pin DPD _ LANE _ DP0_ C, the sixth data signal input pin IN _ D0N is electrically connected to the sixth data signal pin DPD _ LANE _ DN0_ C, the first clock signal input pin CKP is electrically connected to the first clock signal pin DPD _ LANE _ DP3_ DP 35C, and the second clock signal input pin IN _ CKN is electrically connected to the second clock signal DPD _ LANE _ DN3_ C.
The output terminal of the repeater 21 includes a first data signal output pin OUT _ D2P, a second data signal output pin OUT _ D2N, a third data signal output pin OUT _ D1P, a fourth data signal output pin OUT _ D1N, a fifth data signal output pin OUT _ D0P, a sixth data signal output pin OUT _ D0N, a first clock signal output pin OUT _ CKP, and a second clock signal output pin OUT _ CKN.
The HDMI connector 30 includes a first data signal receiving pin OUT _ D2P _ CON, a second data signal receiving pin OUT _ D2N _ CON, a third data signal receiving pin OUT _ D1P _ CON, a fourth data signal receiving pin OUT _ D1N _ CON, a fifth data signal receiving pin OUT _ D0P _ CON, a sixth data signal receiving pin OUT _ D0N _ CON, a first clock signal receiving pin OUT _ CKP _ CON, a second clock signal receiving pin OUT _ CKN _ CON, and a voltage input pin +5V _ HDMI.
The first data signal output pin OUT _ D2P is electrically connected to the first data signal receiving pin OUT _ D2P _ CON, the second data signal output pin OUT _ D2N is electrically connected to the second data signal receiving pin OUT _ D2N _ CON, the third data signal output pin OUT _ D1P is electrically connected to the third data signal receiving pin OUT _ D1P _ CON, the fourth data signal output pin OUT _ D1N is electrically connected to the fourth data signal receiving pin OUT _ D1N _ CON, the fifth data signal output pin OUT _ D0P is electrically connected to the fifth data signal receiving pin OUT _ D0P _ CON, the sixth data signal output pin OUT _ D0N is electrically connected to the sixth data signal receiving pin OUT _ D0N _ CON, the first clock signal output pin OUT _ CKP is electrically connected to the first clock signal receiving pin OUT _ CKP _ CON, the second clock signal output pin OUT _ CKN is electrically connected to the second clock signal receiving pin OUT _ CKN _ CON. The voltage input pin +5V _ HDMI is used to connect a +5V voltage to power the HDMI connector 30.
In operation, the repeater 21 receives the first to sixth data signals, the first clock signal and the second clock signal output by the signal source 10, and performs clock jitter and clock skew correction on the first to sixth data signals, the first clock signal and the second clock signal output by the signal source 10. Clock jitter refers to the error between two clock cycles generated inside a clock, and is usually related to the design of a crystal oscillator or a phase-locked loop inside a circuit. Clock skew refers to the difference in delay between multiple sub-clock signals generated by the same clock, typically associated with PCB traces.
It will be appreciated that the repeater 21 is internally provided with an equalisation circuit. Therefore, when the repeater 21 receives the first to sixth data signals, the first clock signal and the second clock signal output by the signal source 10, the equalization circuit therein corrects the phases and frequencies of the first to sixth data signals, the first clock signal and the second clock signal output by the signal source 10, so as to correct the clock jitter and clock skew of the first to sixth data signals, the first clock signal and the second clock signal, and transmits the corrected first to sixth data signals, the first clock signal and the second clock signal to the HDMI connector 30.
In one embodiment, the repeater 21 may be a chip with model number PS 8409. The PS8409 chip is a chip having a function of eliminating signal jitter. Of course, in other embodiments, the repeater 21 may be other chips, circuits or modules with the function of eliminating signal jitter.
In other embodiments, the HDMI signal anti-jitter circuit 100 further comprises a filter element. In one embodiment, the filtering element is a capacitor C1. One end of the capacitor C1 is electrically connected to the +5V _ HDMI input pin of the HDMI connector 30, and the other end is connected to the +5V voltage. The capacitor C1 is used for filtering the voltage input by the voltage input pin +5V _ HDMI, so that the voltage input into the HDMI signal anti-shake circuit 100 has a smaller change and a more stable voltage peak, and prevents the current from flowing backwards when the HDMI connector 30 is plugged and unplugged, thereby preventing the electronic equipment electrically connected with the HDMI signal anti-shake circuit 100 from being damaged. In one embodiment, the capacitance C1 has a capacitance value of 100nF (nanofarad).
It is understood that in other embodiments, the signal source 10 can also be any device that outputs an HDMI signal through the HDMI connector 30, such as a projector, a monitor, and a set-top box.
According to the invention, the signal output by the signal source 10 is subjected to clock jitter and clock skew correction through the equalization module 20, so that the jitter of the signal output by the signal source 10 is eliminated, the large-amplitude distortion of the signal is further avoided, and the signal quality is improved.
It should be noted that, the modules included in the foregoing device embodiments are merely divided according to functional logic, and are not limited to the above division, as long as the corresponding functions can be implemented. In addition, the specific names of the functional modules are only for convenience of distinguishing from each other and are not used for limiting the protection scope of the present invention.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention. Those skilled in the art can also make other changes and the like in the design of the present invention within the spirit of the present invention as long as they do not depart from the technical effects of the present invention. Such variations are intended to be included within the scope of the invention as claimed.
Claims (10)
1. An anti-jitter circuit for High Definition Multimedia Interface (HDMI) signals, for eliminating HDMI signal jitter, comprising: the HDMI signal anti-shake circuit comprises a signal source, an equalization module and an HDMI connector, wherein the signal source, the equalization module and the HDMI connector are electrically connected in sequence, the signal source is used for outputting an HDMI signal, the equalization module is used for receiving the HDMI signal and correcting the HDMI signal by clock jitter and clock skew so as to output the corrected HDMI signal to the HDMI connector.
2. The HDMI signal anti-jitter circuit of claim 1 wherein: the HDMI signals include first to sixth data signals, a first clock signal, and a second clock signal.
3. The HDMI signal anti-jitter circuit of claim 2 wherein: the equalization module is a repeater.
4. The HDMI signal anti-jitter circuit of claim 3 wherein: the signal source comprises a first data signal pin to a sixth data signal pin, a first clock signal pin and a second clock signal pin which are respectively used for outputting the first to sixth data signals, the first clock signal and the second clock signal, the repeater comprises a first data signal input pin to a sixth data signal input pin, a first clock signal input pin and a second clock signal input pin, and the first to sixth data signal input pins are respectively and electrically connected to the first data signal pin to the sixth data signal pin, the first clock signal input pin and the second clock signal input pin are respectively and electrically connected to the first clock signal pin and the second clock signal pin.
5. The HDMI signal anti-jitter circuit of claim 4 wherein: the repeater further includes first to sixth data signal output pins, a first clock signal output pin, and a second clock signal output pin.
6. The HDMI signal anti-jitter circuit of claim 5 wherein: the HDMI connector comprises a first data signal receiving pin, a second data signal receiving pin, a first clock signal receiving pin, a second clock signal receiving pin and a third clock signal receiving pin, wherein the first data signal receiving pin, the second data signal receiving pin, the third clock signal receiving pin and the fourth clock signal receiving pin are respectively and electrically connected to the first data signal output pin, the second data signal output pin and the third clock signal output pin, and the first clock signal receiving pin and the second clock signal receiving pin are respectively and electrically connected to the first clock signal output pin and the second clock signal output pin.
7. The HDMI signal anti-jitter circuit of claim 1 wherein: the HDMI signal anti-shake circuit comprises a filter element, the HDMI connector comprises a voltage input pin, one end of the filter element is electrically connected with the voltage input pin, and the other end of the filter element is grounded.
8. The HDMI signal anti-jitter circuit of claim 7 wherein: the filter element is a capacitor with a capacitance value of 100 nanofarads.
9. The HDMI signal anti-jitter circuit of claim 3 wherein: the repeater is a PS8409 chip.
10. The HDMI signal anti-jitter circuit of claim 1 wherein: the signal source is a computer, a projector, a monitor or a set-top box.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010313722.8A CN113542649A (en) | 2020-04-20 | 2020-04-20 | HDMI signal anti-shake circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010313722.8A CN113542649A (en) | 2020-04-20 | 2020-04-20 | HDMI signal anti-shake circuit |
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| CN113542649A true CN113542649A (en) | 2021-10-22 |
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| CN202010313722.8A Pending CN113542649A (en) | 2020-04-20 | 2020-04-20 | HDMI signal anti-shake circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115866169A (en) * | 2022-11-23 | 2023-03-28 | 深圳市玩视科技有限公司 | Device and method for eliminating I2S jitter through TMDS |
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2020
- 2020-04-20 CN CN202010313722.8A patent/CN113542649A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115866169A (en) * | 2022-11-23 | 2023-03-28 | 深圳市玩视科技有限公司 | Device and method for eliminating I2S jitter through TMDS |
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