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CN107241529A - A kind of TTL video output systems and its method - Google Patents

A kind of TTL video output systems and its method Download PDF

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Publication number
CN107241529A
CN107241529A CN201710569664.3A CN201710569664A CN107241529A CN 107241529 A CN107241529 A CN 107241529A CN 201710569664 A CN201710569664 A CN 201710569664A CN 107241529 A CN107241529 A CN 107241529A
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clock
image
output
control
signal
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CN107241529B (en
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王彬彬
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Shanghai Sail Acoustic Image Science And Technology Ltd
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Shanghai Sail Acoustic Image Science And Technology Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • H04N5/06Generation of synchronising signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明公开了一种TTL视频输出系统,所述第一时钟信号、所述第一时钟管理模块和所述图像输出控制模块依次连接,所述图像输出控制模块输出不包含时钟的图像信号,所述第二时钟信号连接所述第二时钟管理模块,所述第二时钟管理模块输出图像时钟。本发明的外部PLL芯片由FPGA控制系统进行控制,外部PLL芯片会输出两个时钟送往FPGA,这两个时钟是同频,但用途不同,其中一个通过PLL0进入FPGA控制系统内部连入时钟管理模块进行去偏斜以及增大扇出,以提高时钟质量,将改善的时钟送往图像控制;另一个时钟PLL1则送往时钟管理模块中,以提高信号质量,然后将该时钟送往外部,供点灯使用。

The invention discloses a TTL video output system, the first clock signal, the first clock management module and the image output control module are sequentially connected, and the image output control module outputs an image signal that does not contain a clock, so The second clock signal is connected to the second clock management module, and the second clock management module outputs an image clock. The external PLL chip of the present invention is controlled by the FPGA control system, and the external PLL chip can output two clocks and send them to the FPGA. These two clocks are of the same frequency, but have different purposes. One of them enters the FPGA control system through PLL0 and is connected to the internal clock management. The module de-skews and increases the fan-out to improve the clock quality, and sends the improved clock to the image control; another clock PLL1 is sent to the clock management module to improve the signal quality, and then sends the clock to the outside, It is for lighting.

Description

一种TTL视频输出系统及其方法A kind of TTL video output system and its method

技术领域technical field

本发明属于液晶技术领域,更具体地说,尤其涉及一种TTL视频输出系统。同时,本发明还涉及一种TTL视频输出方法。The invention belongs to the field of liquid crystal technology, and more specifically relates to a TTL video output system. At the same time, the invention also relates to a TTL video output method.

背景技术Background technique

液晶显示模组(Liquid Crystal Display Module,以下简称模组)及其相关的液晶显示设备(以下简称设备)的使用已十分普遍,同时也由于TTL(Transistor TransistorLogic,晶体管-晶体管逻辑电平)信号稳定可靠、传速率高、功耗较低,很多模组及设备都通过采用该信号作为接收视频图像的显示接口。The use of liquid crystal display modules (Liquid Crystal Display Module, hereinafter referred to as modules) and related liquid crystal display devices (hereinafter referred to as devices) has become very common, and because of TTL (Transistor TransistorLogic, transistor-transistor logic level) signal stability Reliable, high transmission rate, and low power consumption, many modules and devices use this signal as a display interface for receiving video images.

在模组及其设备进行生产、调试、显像过程时需要通过视频图像信号源或视频转接板(以下均简称视频源)产生TTL视频信号给其提供模组显示信号的来源,因此确保视频源产生的视频信号正确性和可靠性是保障模组显示的前提。During the production, debugging and display process of the module and its equipment, it is necessary to generate a TTL video signal through the video image signal source or video adapter board (hereinafter referred to as the video source) to provide the source of the module display signal, so ensure that the video The correctness and reliability of the video signal generated by the source are the prerequisites for ensuring the display of the module.

TTL视频传输方面,由于内部信号要经过封装键合线,PCB板上上的连线以及通孔,才能与其他芯片连接,如果采用TTL电平作为输出接口,则各种寄生参数会导致数据的上升/下降时间以及多路数据之间的同步匹配等严重恶化。因此,一般采用TTL电平作为视频传输,速度低,点出的图失真。In terms of TTL video transmission, since the internal signal needs to go through the package bonding wire, the connection wire on the PCB board and the through hole, it can be connected to other chips. If TTL level is used as the output interface, various parasitic parameters will lead to data loss. Rise/fall times and synchronous matching between multiplexed data are severely degraded. Therefore, TTL level is generally used as video transmission, the speed is low, and the picture displayed is distorted.

发明内容Contents of the invention

本发明的目的是为了解决现有技术中存在的缺点,而提出的一种TTL视频输出系统及其方法,在信号不失真的情况下,提升TTL视频传输效果。The purpose of the present invention is to solve the shortcomings in the prior art, and propose a TTL video output system and method thereof, which can improve the TTL video transmission effect without signal distortion.

为实现上述目的,本发明提供如下技术方案:To achieve the above object, the present invention provides the following technical solutions:

一种TTL视频输出系统,包括PLL芯片和FPGA控制系统,该PLL芯片包括同频的第一时钟信号和第二时钟信号,该FPGA控制系统包括第一时钟管理模块、第二时钟管理模块和图像输出控制模块,所述第一时钟信号、所述第一时钟管理模块和所述图像输出控制模块依次连接,所述图像输出控制模块输出不包含时钟的图像信号,所述第二时钟信号连接所述第二时钟管理模块,所述第二时钟管理模块输出图像时钟。A TTL video output system includes a PLL chip and an FPGA control system, the PLL chip includes a first clock signal and a second clock signal of the same frequency, and the FPGA control system includes a first clock management module, a second clock management module and an image Output control module, the first clock signal, the first clock management module and the image output control module are sequentially connected, the image output control module outputs an image signal that does not contain a clock, and the second clock signal is connected to the The second clock management module, the second clock management module outputs an image clock.

本发明还提供一种TTL视频输出方法,包括如下步骤:The present invention also provides a kind of TTL video output method, comprises the steps:

S1、上位机下发播放参数以及播放控制后,控制外部PLL芯片输出两路同频同相时钟中,其中PLL0用于控制图像的数据以及行场同步信号的输出;PLL1用于点灯的时钟控制;由于开始时PLL1以及PLL0为同频同相信号,因此输出的时序在源端是同步的信号;S1. After the upper computer sends the playback parameters and playback control, control the external PLL chip to output two clocks with the same frequency and phase, among which PLL0 is used to control the output of image data and line and field synchronization signals; PLL1 is used to control the clock of lighting; Since PLL1 and PLL0 are signals of the same frequency and phase at the beginning, the timing of the output is a synchronous signal at the source;

S2、如若点灯异常,上位机下发出相位控制参数,已调整输出图像的时钟相位,此时源端输出的时钟和数据并不同步,而由于信号通过系统时产生的相位偏移,输出到达终端会达到点灯效果。S2. If the lighting is abnormal, the host computer sends out phase control parameters, and the clock phase of the output image has been adjusted. At this time, the clock and data output by the source end are not synchronized, and due to the phase shift generated when the signal passes through the system, the output reaches the terminal. It will achieve lighting effect.

优选的,在S2中,通过观察图像状态进行调整。Preferably, in S2, the adjustment is made by observing the image state.

本发明的技术效果和优点:本发明提供的TTL视频输出系统及其方法,其外部PLL芯片由FPGA控制系统进行控制,外部PLL芯片会输出两个时钟送往FPGA,这两个时钟是同频,但用途不同,其中一个通过PLL0进入FPGA控制系统内部连入时钟管理模块进行去偏斜以及增大扇出,以提高时钟质量,将改善的时钟送往图像控制;另一个时钟PLL1则送往时钟管理模块中,以提高信号质量,然后将该时钟送往外部,供点灯使用;图像输出控制模块,这个部分图像输出的控制时序的时钟和点灯的时钟并不是同一个时钟,该模块在工作的时候仅仅输出图像的数据信号及一些行场同步信号,解决了在信号不失真的情况下,提升TTL视频传输效果。Technical effect and advantage of the present invention: TTL video output system and method thereof provided by the present invention, its external PLL chip is controlled by FPGA control system, and external PLL chip can output two clocks and send to FPGA, and these two clocks are the same frequency , but the purposes are different. One of them enters the FPGA control system through PLL0 and connects to the clock management module to de-skew and increase the fan-out to improve the clock quality and send the improved clock to image control; the other clock PLL1 is sent to In the clock management module, to improve the signal quality, and then send the clock to the outside for lighting; the image output control module, the clock for controlling the timing of this part of the image output and the clock for lighting are not the same clock, this module is working At the time, only the data signal of the image and some line and field synchronization signals are output, which solves the problem of improving the TTL video transmission effect without signal distortion.

附图说明Description of drawings

图1为本发明的模块原理框图;Fig. 1 is a block diagram of the module principle of the present invention;

图2为本发明的控制流程图。Fig. 2 is a control flow chart of the present invention.

图3为本发明的分析图。Fig. 3 is an analysis diagram of the present invention.

具体实施方式detailed description

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合具体实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

如图1所示,本发明提供一种TTL视频输出系统,包括PLL芯片和FPGA控制系统,该PLL芯片包括同频的第一时钟信号和第二时钟信号,该FPGA控制系统包括第一时钟管理模块、第二时钟管理模块和图像输出控制模块,所述第一时钟信号、所述第一时钟管理模块和所述图像输出控制模块依次连接,所述图像输出控制模块输出不包含时钟的图像信号,所述第二时钟信号连接所述第二时钟管理模块,所述第二时钟管理模块输出图像时钟。As shown in Figure 1, the present invention provides a kind of TTL video output system, comprises PLL chip and FPGA control system, and this PLL chip comprises the first clock signal of the same frequency and the second clock signal, and this FPGA control system comprises the first clock management system module, a second clock management module, and an image output control module, the first clock signal, the first clock management module, and the image output control module are sequentially connected, and the image output control module outputs an image signal that does not contain a clock , the second clock signal is connected to the second clock management module, and the second clock management module outputs an image clock.

如图2所示,本发明还提供一种TTL视频输出方法,包括如下步骤:As shown in Figure 2, the present invention also provides a kind of TTL video output method, comprises the steps:

S1、上位机下发播放参数以及播放控制后,控制PLL芯片输出两路同频时钟信号,其中一路时钟信号用于控制图像的数据以及行场同步信号的输出,另一路时钟信号用于点灯的时钟控制;S1. After the upper computer sends the playback parameters and playback control, control the PLL chip to output two clock signals with the same frequency, one of which is used to control the image data and the output of line and field synchronization signals, and the other clock signal is used for lighting. clock control;

S2、如若点灯异常,上位机下发出相位控制参数,以调整输出图像的时钟相位,输出到达终端会达到点灯效果。在S2中,通过观察图像状态,进行调整;因为同一套线缆以及治具,所能引起的相位变化是一定的,因此,只需要进行一次调整就可以。S2. If the lighting is abnormal, the upper computer sends out phase control parameters to adjust the clock phase of the output image, and the output reaches the terminal to achieve the lighting effect. In S2, adjust by observing the image state; because the same set of cables and fixtures can cause a certain phase change, therefore, only one adjustment is required.

在点灯过程中,我们会遇到源端输出波形同步,而到了终端不同步的情况。从而导致了点灯效果的异常。不难分析由傅里叶级数的定义可以知道,所有的周期性信号都可以用不同频率的正弦波(这里指正弦和余弦的总称)叠加而成。而一个固定频率的正弦波进入任何一个复杂系统,它的输出只会使输入的波形产生幅值与相位的变化,并不会改变波形的形状。因此,由于时钟与数据的频率的差异,导致时钟和信号在到达终端后产生了偏移。如图3所示。During the lighting process, we will encounter the situation that the output waveform of the source terminal is synchronous, but the terminal is not synchronous. As a result, the lighting effect is abnormal. It is not difficult to analyze. From the definition of Fourier series, it can be known that all periodic signals can be superimposed with sine waves of different frequencies (here refers to the general term of sine and cosine). When a sine wave with a fixed frequency enters any complex system, its output will only change the amplitude and phase of the input waveform, and will not change the shape of the waveform. Therefore, due to the frequency difference between the clock and the data, the clock and the signal are skewed after reaching the terminal. As shown in Figure 3.

最后应说明的是:以上所述仅为本发明的优选实施例而已,并不用于限制本发明,尽管参照前述实施例对本发明进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。Finally, it should be noted that: the above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, it still The technical solutions recorded in the foregoing embodiments may be modified, or some of the technical features may be replaced by equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims (3)

1.一种TTL视频输出系统,其特征在于,包括PLL芯片和FPGA控制系统,该PLL芯片包括同频的第一时钟信号和第二时钟信号,该FPGA控制系统包括第一时钟管理模块、第二时钟管理模块和图像输出控制模块,所述第一时钟信号、所述第一时钟管理模块和所述图像输出控制模块依次连接,所述图像输出控制模块输出不包含时钟的图像信号,所述第二时钟信号连接所述第二时钟管理模块,所述第二时钟管理模块输出图像时钟。1. a kind of TTL video output system is characterized in that, comprises PLL chip and FPGA control system, and this PLL chip comprises the first clock signal and the second clock signal of same frequency, and this FPGA control system comprises the first clock management module, the first clock signal Two clock management modules and an image output control module, the first clock signal, the first clock management module and the image output control module are connected in sequence, the image output control module outputs an image signal that does not contain a clock, the The second clock signal is connected to the second clock management module, and the second clock management module outputs an image clock. 2.一种权利要求1所述的TTL视频输出方法,其特征在于:包括如下步骤:2. a kind of TTL video output method according to claim 1, is characterized in that: comprise the steps: S1、上位机下发播放参数以及播放控制后,控制PLL芯片输出两路同频时钟信号,其中一路时钟信号用于控制图像的数据以及行场同步信号的输出,另一路时钟信号用于点灯的时钟控制;S1. After the upper computer sends the playback parameters and playback control, control the PLL chip to output two clock signals with the same frequency, one of which is used to control the image data and the output of line and field synchronization signals, and the other clock signal is used for lighting. clock control; S2、如若点灯异常,上位机下发出相位控制参数,以调整输出图像的时钟相位,输出到达终端会达到点灯效果。S2. If the lighting is abnormal, the upper computer sends out phase control parameters to adjust the clock phase of the output image, and the output reaches the terminal to achieve the lighting effect. 3.根据权利要求2所述的一种TTL视频输出方法,其特征在于:在S2中,通过观察图像状态进行调整。3. A TTL video output method according to claim 2, characterized in that: in S2, the adjustment is made by observing the image state.
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