CN221884301U - High-speed interface expansion board card and electronic equipment - Google Patents

Abstract

The utility model relates to a high-speed interface expansion board and an electronic device, wherein the board comprises: a main board and an expansion board; the main board comprises: a main control chip and a first high-speed serial interface connected to the main control chip; the expansion board comprises: a second high-speed serial interface, a first switch switching circuit, a second switch switching circuit and at least two different types of third high-speed serial interfaces; the second high-speed serial interface in the expansion board is used to connect the first high-speed serial interface on the main board, the sending channel of the second high-speed serial interface is connected to the signal input end of the first switch switching circuit, the signal output end of the first switch switching circuit is connected to the sending channels of each third high-speed serial interface, the receiving channel of the second high-speed serial interface is connected to the signal output end of the second switch switching circuit, and the signal input end of the second switch switching circuit is connected to the receiving channels of each third high-speed serial interface. Thus, the board manufacturing cost can be reduced while ensuring the transmission quality of high-speed signals.

Description

High-speed interface expansion board and electronic equipment

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a high-speed interface expansion board and electronic equipment.

Background Art

As the complexity of integrated circuit design increases, different high-speed serial interfaces (such as video communication interface, high-speed communication interface) need to be integrated into a chip. Since the number of ports or pins of the chip is limited, most ports have multiple functional options, and some ports are brought out through the general serializer serdes pins. In this way, during the verification or application stage of the chip, a port cannot be used for another function after being occupied by one function, which brings inconvenience to the functional verification or interface application of the full functional coverage of the chip.

Specifically, when verifying the function of a certain chip, the prior art either prepares multiple boards for different high-speed serial interfaces to achieve full-function verification. For example, for five high-speed serial interfaces (such as VBO interface, eDP interface, USB interface, DP interface and PCIe interface), it is necessary to prepare six boards shown in Figures 1a to 1f, that is, by preparing multiple boards and connecting the input and output ports of the chip to different high-speed serial interfaces, full-function verification of the chip can be achieved, which obviously increases the board manufacturing cost as well as the verification cost and verification cycle; or the prior art can also directly connect the input and output ports of the chip to different high-speed serial interfaces for multiplexing, such as a board shown in Figure 2, but this method will cause the routing (that is, signal transmission link) in the board (that is, PCB board) to form more forks (Stubs), which will have a negative impact on the signal quality and signal integrity of the high-speed signal (such as high-speed video signal, high-speed communication signal) transmitted through the forks, making the board unable to be used normally.

Utility Model Content

In view of this, the utility model proposes a high-speed interface expansion board and electronic equipment, which can reduce the board manufacturing cost, realize the multiplexing of the input and output ports of the main control chip, and ensure the transmission quality of high-speed signals, so as to facilitate the full-function verification of the main control chip.

According to a first aspect of the utility model, a high-speed interface expansion board is provided, comprising: a main board and an expansion board; the main board comprises: a main control chip and a first high-speed serial interface connected to the main control chip, the main control chip is a chip of a physical layer having integrated a high-speed serial interface; the expansion board comprises: a second high-speed serial interface, a first switch switching circuit, a second switch switching circuit and at least two different types of third high-speed serial interfaces; wherein the second high-speed serial interface in the expansion board is used to connect to the first high-speed serial interface on the main board, a sending channel of the second high-speed serial interface is connected to a signal input end of the first switch switching circuit, a signal output end of the first switch switching circuit is connected to a sending channel of each third high-speed serial interface, a receiving channel of the second high-speed serial interface is connected to a signal output end of the second switch switching circuit, and a signal input end of the second switch switching circuit is connected to a receiving channel of each third high-speed serial interface.

In a possible implementation of the first aspect, the signal output end of the high-speed signal multiplexing port of the main control chip is connected to the transmitting channel of the first high-speed serial interface, and the signal input end of the high-speed signal multiplexing port of the main control chip is connected to the receiving channel of the first high-speed serial interface.

In a possible implementation manner of the first aspect, when the first high-speed serial interface is connected to the second high-speed serial interface, a sending channel of the first high-speed serial interface is connected to a sending channel of the second high-speed serial interface, and a receiving channel of the first high-speed serial interface is connected to a receiving channel of the second high-speed serial interface.

In a possible implementation manner of the first aspect, the first high-speed serial interface and the second high-speed serial interface are VBO interfaces; the third high-speed serial interface includes at least two of the following: a DP interface, an eDP interface, a USB interface, and a PCIe interface; and the USB interface includes a Type C interface.

In a possible implementation of the first aspect, the first switch switching circuit includes two signal output ends, one signal output end of the first switch switching circuit is connected to the sending channel of the DP interface and the eDP interface, and the other signal output end of the first switch switching circuit is connected to the sending channel of the USB interface and the PCIe interface; the second switch switching circuit includes two signal input ends, one signal input end of the second switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input end of the second switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface.

According to a second aspect of the utility model, a high-speed interface expansion board is provided, comprising: a main control chip, a third switch switching circuit, a fourth switch switching circuit, a fifth switch switching circuit, a sixth switch switching circuit, a fourth high-speed serial interface, and at least two different types of fifth high-speed serial interfaces, wherein the main control chip is a chip of a physical layer of an integrated high-speed serial interface; wherein a signal output end of the main control chip is connected to a signal input end of the third switch switching circuit, a signal output end of the third switch switching circuit is connected to a sending channel of the fourth high-speed serial interface and a signal input end of the fourth switch switching circuit, and a signal output end of the fourth switch switching circuit is connected to sending channels of each fifth high-speed serial interface; a signal input end of the main control chip is connected to a signal output end of the fifth switch switching circuit, a signal input end of the fifth switch switching circuit is connected to a receiving channel of the fourth high-speed serial interface and a signal output end of the sixth switch switching circuit, and a signal input end of the sixth switch switching circuit is connected to receiving channels of each fifth high-speed serial interface.

In a possible implementation manner of the second aspect, the third switch switching circuit includes two signal output terminals, one signal output terminal of the third switch switching circuit is connected to a sending channel of the fourth high-speed serial interface, and the other signal output terminal of the third switch switching circuit is connected to a signal input terminal of the fourth switch switching circuit; the fifth switch switching circuit includes two signal input terminals, one signal input terminal of the fifth switch switching circuit is connected to a receiving channel of the fourth high-speed serial interface, and the other signal input terminal of the fifth switch switching circuit is connected to the signal output terminal of the sixth switch switching circuit.

In a possible implementation of the second aspect, the fourth high-speed serial interface is a VBO interface; the fifth high-speed serial interface includes at least two of the following: a DP interface, an eDP interface, a USB interface, and a PCIe interface; and the USB interface includes a Type C interface.

In a possible implementation of the second aspect, the fourth switch switching circuit has two signal output ends, one signal output end of the fourth switch switching circuit is connected to the sending channel of the DP interface and the eDP interface, and the other signal output end of the fourth switch switching circuit is connected to the sending channel of the USB interface and the PCIe interface; the sixth switch switching circuit has two signal input ends, one signal input end of the sixth switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input end of the sixth switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface.

According to another aspect of the utility model, an electronic device is provided, comprising: a board according to the first aspect or any possible implementation of the first aspect, or a board according to the second aspect or any possible implementation of the second aspect.

According to various aspects of the utility model, the switching function of two switching circuits or four switching circuits can be used to lead different high-speed signals to their corresponding interfaces, thereby realizing the multiplexing of high-speed signals. This not only reduces the number of boards and the cost of board manufacturing, but also does not produce many branches on the routing of the board, thereby ensuring the quality and integrity of high-speed signal transmission. At the same time, it can also meet the needs of full-function verification of the main control chip, saving chip development and verification costs.

Other features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the invention and, together with the description, serve to explain the principles of the invention.

1a to 1f are schematic diagrams showing six types of boards according to the prior art.

FIG. 2 shows a schematic diagram of a board according to the prior art.

FIG3 shows a schematic diagram of a high-speed interface expansion board according to an embodiment of the present invention.

FIG. 4 shows a schematic diagram of a high-speed interface expansion board according to an embodiment of the present invention.

FIG5 is a schematic diagram showing another high-speed interface expansion board according to an embodiment of the present invention.

FIG6 is a schematic diagram showing another high-speed interface expansion board according to an embodiment of the present invention.

DETAILED DESCRIPTION

Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

In addition, the prefixes of the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features, nor are they used to describe a specific order. Therefore, the features defined as "first", "second", "third", "fourth", "fifth", "sixth" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

The term "and/or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

In order to facilitate a better understanding of the solutions of the embodiments of the present utility model, the relevant terms and concepts that may be involved in the embodiments of the present utility model are first introduced below.

(1) PMA (Physical Media Attachment): The physical media attachment layer in the high-speed serial transceiver. The PMA port of the main control chip is also the high-speed signal multiplexing port of the main control chip.

(2) VBO interface, also known as V-by-One interface, is a high-speed serial interface for video signal transmission. The VBO interface can convert 40-bit/pixel image data into a pair of differential signals, greatly reducing the use of transmission lines and effectively saving the cost of wires and connectors. This VBO interface can be used in high-definition televisions, anti-theft surveillance cameras, computers and other equipment.

(3) DP interface, namely DisplayPort interface, is a digital video interface standardized by the Video Electronics Standards Association. It is mainly used to connect video sources to devices such as monitors, and supports carrying audio, USB and other forms of data. The DP interface protocol uses data packets instead of traditional timer signals, allowing it to use fewer pins and achieve higher resolution.

(4) eDP interface, namely Embedded DisplayPort interface, is an internal digital interface based on DisplayPort architecture and protocol, mainly used in various products with embedded display panels, such as all-in-one computers, notebook computers and tablet computers. eDP interface can provide higher transmission rate and better image quality, and gradually become the mainstream choice of internal digital interface.

(5) PCle interface, full name PCI-Express (Peripheral Component Interconnect Express), is a high-speed serial computer expansion bus interface used to connect various components inside the computer, such as graphics cards, solid-state drives (PCle interface form), wireless network cards, wired network cards, sound cards, video capture cards, etc.

(6) USB interface is a standard external bus interface used to regulate the connection and communication between computers and external devices. It is widely used in information communication products such as personal computers and mobile devices. Type-C is a new USB interface that integrates charging and data transmission functions.

(7) Lane, signal transmission link, can also be understood as the routing between different devices in the board. 8lane represents an eight-channel signal transmission link, 4lane represents a four-channel signal transmission link, and 2lane represents a two-channel signal transmission link.

(8) The main control chip is a chip that undertakes specific calculation and control tasks in the board. The main control chip may include but is not limited to: various processors (such as central processing unit CPU, image processing unit GPU, neural network processor NPU, digital signal processor DSP), micro control unit MCU, application-specific integrated circuit ASIC, field programmable gate array FPGA, etc. It should be noted that the main control chip involved in the embodiment of the utility model is a chip that has integrated the physical layer PHY (Physical, that is, physical interface transceiver) of various high-speed serial interfaces, that is, the main control chip directly supports the above-mentioned VBO, PCIe, USB, DP, eDP and other high-speed serial interfaces, and can directly process the high-speed signals transmitted by various high-speed serial interfaces and directly output the high-speed signals via the high-speed serial interface. Among them, PHY includes the above-mentioned PMA.

(9) Switching circuit (i.e., switch circuit), which realizes signal switching and transmission by controlling the on and off state of the switch element. In the switching circuit, commonly used switch elements include mechanical switches, semiconductor switches, and photoelectric switches. It should be noted that the switching circuit involved in the embodiment of the utility model is mainly used for the transmission and switching of high-speed signals, that is, it plays a physical switching role similar to a single-pole double-throw switch.

Fig. 3 shows a schematic diagram of a high-speed interface expansion board according to an embodiment of the present invention. As shown in Fig. 3, the board includes: a main board and an expansion board;

The mainboard includes: a main control chip and a first high-speed serial interface connected to the main control chip;

The expansion board includes: a second high-speed serial interface, a first switch switching circuit, a second switch switching circuit and at least two different types of third high-speed serial interfaces; wherein the second high-speed serial interface in the expansion board is used to connect to the first high-speed serial interface on the main board, a sending channel of the second high-speed serial interface is connected to a signal input end of the first switch switching circuit, a signal output end of the first switch switching circuit is connected to sending channels of each third high-speed serial interface, a receiving channel of the second high-speed serial interface is connected to a signal output end of the second switch switching circuit, and a signal input end of the second switch switching circuit is connected to a receiving channel of each third high-speed serial interface.

It can be known that any high-speed serial interface will include a signal sending channel TX and a receiving channel RX. Therefore, the signal output end in the high-speed signal multiplexing port (such as a PMA port) of the main control chip can be connected to the sending channel TX of the first high-speed serial interface, and the signal input end in the high-speed signal multiplexing port of the main control chip can be connected to the receiving channel RX of the first high-speed serial interface.

In actual applications, the main board and the expansion board can be connected through the first high-speed serial interface and the second high-speed serial interface. When the main board and the expansion board are not connected, the first high-speed serial interface of the main board can play the interface function of the interface itself, and then verify the function of the main board chip under the first high-speed serial interface.

When the first high-speed serial interface is connected to the second high-speed serial interface, the first high-speed serial interface on the main board and the second high-speed serial interface on the expansion board can be understood as two connectors, which mainly play the role of connecting the main board and the expansion board together. Therefore, when the first high-speed serial interface is connected to the second high-speed serial interface, the transmitting channel TX of the first high-speed serial interface is connected to the transmitting channel TX of the second high-speed serial interface, and the receiving channel TX of the first high-speed serial interface is connected to the receiving channel TX of the second high-speed serial interface.

In one possible implementation, the first high-speed serial interface and the second high-speed serial interface are VBO interfaces; the third high-speed serial interface may include at least two of the following: DP interface, eDP interface, USB interface, PCIe interface; the USB interface may include a Type C interface.

Based on the above-mentioned high-speed serial interfaces, the embodiment of the utility model further provides a high-speed interface expansion board as shown in FIG4 . As shown in FIG4 , the first switch switching circuit includes two signal output terminals, one signal output terminal of the first switch switching circuit is connected to the transmission channel of the DP interface and the eDP interface, and the other signal output terminal of the first switch switching circuit is connected to the transmission channel of the USB interface (such as the USB3.0 Type C interface) and the PCIe interface;

The second switch switching circuit includes two signal input terminals, one signal input terminal of the second switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input terminal of the second switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface.

As shown in Figure 4, the TX and RX of the VBO interface transmit 8-lane differential signals (that is, eight-channel differential signals) respectively. By using two switch circuits, these 16-channel differential signals can be multiplexed with the high-speed differential signals of the DP interface, eDP interface, USB interface, and PCIe interface, thereby reducing the number and cost of boards, while also meeting the functional verification of the main control chip under various high-speed serial interfaces.

It should be understood that the connection method between the two switch switching circuits and each third high-speed serial interface in the high-speed interface expansion board shown in Figure 4 is a possible implementation method provided by an embodiment of the utility model. In fact, technical personnel in this field can customize the number of third high-speed serial interfaces connected to the two switch switching circuits according to actual needs. For example, the first switch switching circuit can use two signal output ends to respectively connect the sending channels of the DP interface and the eDP interface, and the second switch switching circuit can use two signal input ends to respectively connect the receiving channels of the DP interface and the eDP interface; or, the first switch switching circuit can use two signal output ends to connect the sending channels of the USB interface and the PCIe interface, and the second switch switching circuit can use two signal input ends to respectively connect the receiving channels of the USB interface and the PCIe interface.

Exemplarily, when the high-speed interface expansion board shown in FIG. 4 is used to verify the video signal processing function of the main control chip, if the video signal is input through the receiving channel of the DP interface, the second switch switching circuit switches the switch to the signal transmission link corresponding to the receiving channel of the DP interface to connect the transmission link from the receiving channel of the DP interface to the main control chip, thereby transmitting the video signal to the main control chip. The signal processing result obtained after the main control chip processes the video signal is transmitted to the first switch switching circuit through the signal output end. At this time, the first switch switching circuit switches the switch to the signal transmission link corresponding to the sending channel of the DP interface to connect the transmission link from the main control chip to the sending channel of the DP interface, thereby transmitting the video signal to the main control chip through the DP interface. The sending channel of the port outputs the signal processing result of the main control chip. Based on the signal processing result and the expected signal processing, the video signal processing function of the main control chip can be verified, and whether the signal transmission link from the DP interface to the main control chip is normal can also be verified; similarly, if the video signal is input through the PCIe interface, the second switch switching circuit switches the switch to the signal transmission link corresponding to the receiving channel of the PCIe interface, and, when outputting the signal processing result, the first switch switching circuit switches the switch to the signal transmission link corresponding to the sending channel of the PCIe interface, which can not only verify the signal processing function of the main control chip, but also verify whether the signal transmission link from the PCIe interface to the main control chip is normal.

According to the high-speed interface expansion board of the embodiment of the utility model, the switching function of the two switching circuits can be used to transmit high-speed signals input from different interfaces to the main control chip and to guide different high-speed signals output from the main control chip to their respective corresponding interfaces, thereby realizing the multiplexing of the high-speed signal output and input ports of the main control chip, which not only reduces the number of boards and the cost of board manufacturing, but also does not produce many branches on the routing of the board, thereby ensuring the quality and integrity of high-speed signal transmission, and at the same time can meet the needs of full-function verification of the main control chip, saving chip development and verification costs.

Figure 5 shows a schematic diagram of another high-speed interface expansion board according to an embodiment of the utility model. As shown in Figure 5, the board includes: a main control chip, a third switch switching circuit, a fourth switch switching circuit, a fifth switch switching circuit, a sixth switch switching circuit, a fourth high-speed serial interface, and at least two different types of fifth high-speed serial interfaces;

The signal output end of the main control chip is connected to the signal input end of the third switch switching circuit, the signal output end of the third switch switching circuit is connected to the transmission channel TX of the fourth high-speed serial interface and the signal input end of the fourth switch switching circuit, and the signal output end of the fourth switch switching circuit is connected to the transmission channels of each fifth high-speed serial interface;

The signal input end of the main control chip is connected to the signal output end of the fifth switch switching circuit, the signal input end of the fifth switch switching circuit is connected to the receiving channel of the fourth high-speed serial interface and the signal output end of the sixth switch switching circuit, and the signal input end of the sixth switch switching circuit is connected to the receiving channels of each fifth high-speed serial interface.

In a possible implementation, as shown in FIG5 , the third switch switching circuit includes two signal output terminals, one signal output terminal of the third switch switching circuit is connected to the sending channel of the fourth high-speed serial interface, and the other signal output terminal of the third switch switching circuit is connected to the signal input terminal of the fourth switch switching circuit; the fifth switch switching circuit includes two signal input terminals, one signal input terminal of the fifth switch switching circuit is connected to the receiving channel of the fourth high-speed serial interface, and the other signal input terminal of the fifth switch switching circuit is connected to the signal output terminal of the sixth switch switching circuit.

In one possible implementation, the fourth high-speed serial interface is a VBO interface; the fifth high-speed serial interface includes at least two of the following: a DP interface, an eDP interface, a USB interface, and a PCIe interface; and the USB interface includes a Type C interface.

Based on the above-mentioned various high-speed serial interfaces, an embodiment of the utility model also provides a high-speed interface expansion board as shown in Figure 6. As shown in Figure 6, the fourth switch switching circuit has two signal output ends, one signal output end of the fourth switch switching circuit is connected to the sending channel of the DP interface and the eDP interface, and the other signal output end of the fourth switch switching circuit is connected to the sending channel of the USB interface (such as USB3.0 Type C) and the PCIe interface; the sixth switch switching circuit has two signal input ends, one signal input end of the sixth switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input end of the sixth switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface.

It should be understood that the connection method between the fourth switch switching circuit and the sixth switch switching circuit and each fifth high-speed serial interface in the high-speed interface expansion board shown in Figure 6 is a possible implementation method provided by an embodiment of the utility model. In fact, those skilled in the art can customize the number of fifth high-speed serial interfaces connected to the two switch switching circuits according to actual needs. For example, the fourth switch switching circuit can use two signal output ends to respectively connect the sending channels of the DP interface and the eDP interface, and the sixth switch switching circuit can use two signal input ends to respectively connect the receiving channels of the DP interface and the eDP interface; or, the fourth switch switching circuit can use two signal output ends to respectively connect the sending channels of the USB interface and the PCIe interface, and the sixth switch switching circuit can use two signal input ends to respectively connect the receiving channels of the USB interface and the PCIe interface.

It can be understood that, compared with the board shown in Figure 4, the board shown in Figure 6 can be understood as integrating all functions on a PCB board. In this case, there is no need to use two VBO interfaces as connectors. At the same time, in order to allow the VBO interface to play the functional role of its own interface, four switch switching circuits can be used to connect each high-speed serial interface.

Exemplarily, when the video signal processing function of the main control chip is verified by using the high-speed interface expansion board shown in Figure 6, if the video signal is input through the receiving channel of the VBO interface, the fifth switch switching circuit switches the switch to the signal transmission link corresponding to the receiving channel of the VBO interface to connect the transmission link from the receiving channel of the VBO interface to the main control chip, thereby transmitting the video signal to the main control chip. The signal processing result obtained after the main control chip processes the video signal is transmitted to the third switch switching circuit through the signal output end. At this time, the third switch switching circuit switches the switch to the signal transmission link corresponding to the sending channel of the VBO interface to connect the transmission link from the main control chip to the sending channel of the VBO interface, thereby outputting the signal processing result of the main control chip through the sending channel of the VBO interface. Based on the signal processing result and the expected signal processing, the main control chip can be processed. The video signal processing function can be verified, and whether the signal transmission link from the VBO interface to the main control chip is normal can be verified; if the video signal is input through the PCIe interface, the sixth switch switching circuit will switch the switch to the signal transmission link corresponding to the receiving channel of the PCIe interface, and the fifth switch switching circuit will switch the switch to the signal transmission link between the sixth switch switching circuit to connect the transmission link from the receiving channel of the PCIe interface to the main control chip, and, when outputting the signal processing result, the third switch switching circuit will switch the switch to the signal transmission link between the fourth switch switching circuit, and the fourth switch switching circuit will switch the switch to the signal transmission link corresponding to the sending channel of the PCIe interface, which can not only verify the signal processing function of the main control chip, but also verify whether the signal transmission link from the PCIe interface to the main control chip is normal.

According to the high-speed interface expansion board of the embodiment of the utility model, the switching function of the four switching circuits can be used to transmit high-speed signals input from different interfaces to the main control chip and to guide different high-speed signals output from the main control chip to their respective corresponding interfaces, thereby realizing the multiplexing of the high-speed signal output and input ports of the main control chip, which not only reduces the number of boards and the cost of board manufacturing, but also does not produce many branches on the routing of the board, thereby ensuring the quality and integrity of high-speed signal transmission, and at the same time can meet the needs of full-function verification of the main control chip, saving chip development and verification costs.

It should be noted that in the board shown in Figures 3 to 6 above, the main control chip is physically connected to each high-speed serial interface through a switch switching circuit, and there is no high-speed signal conversion process, so that the bandwidth of high-speed signal transmission is not damaged. After the high-speed signal is transferred to the corresponding high-speed serial interface through the switch switching circuit, it can be directly connected to the external device (such as a display) of the high-speed serial interface without the need to add other processing chips (such as a display processing chip).

Based on the board card provided by the above embodiment of the utility model, the embodiment of the utility model further provides an electronic device, which includes: any one of the board cards shown in the above FIG. 3 to FIG. 6 .

Exemplarily, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

Exemplarily, the electronic device may also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. The electronic device may also be a server, for example, the server may be a local server or a cloud server.

The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the utility model. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A high-speed interface expansion board, characterized in that it comprises: a main board and an expansion board; The mainboard comprises: a main control chip and a first high-speed serial interface connected to the main control chip, wherein the main control chip is a chip of a physical layer having integrated a high-speed serial interface; The expansion board includes: a second high-speed serial interface, a first switch switching circuit, a second switch switching circuit and at least two different types of third high-speed serial interfaces; wherein the second high-speed serial interface in the expansion board is used to connect to the first high-speed serial interface on the main board, a sending channel of the second high-speed serial interface is connected to a signal input end of the first switch switching circuit, a signal output end of the first switch switching circuit is connected to sending channels of each third high-speed serial interface, a receiving channel of the second high-speed serial interface is connected to a signal output end of the second switch switching circuit, and a signal input end of the second switch switching circuit is connected to a receiving channel of each third high-speed serial interface. 2. The board according to claim 1, characterized in that: The signal output end of the high-speed signal multiplexing port of the main control chip is connected to the sending channel of the first high-speed serial interface, and the signal input end of the high-speed signal multiplexing port of the main control chip is connected to the receiving channel of the first high-speed serial interface. 3. The board according to claim 1, characterized in that: When the first high-speed serial interface is connected to the second high-speed serial interface, the sending channel of the first high-speed serial interface is connected to the sending channel of the second high-speed serial interface, and the receiving channel of the first high-speed serial interface is connected to the receiving channel of the second high-speed serial interface. 4. The board according to any one of claims 1 to 3, characterized in that: The first high-speed serial interface and the second high-speed serial interface are VBO interfaces; The third high-speed serial interface includes at least two of the following: a DP interface, an eDP interface, a USB interface, and a PCIe interface; and the USB interface includes a Type C interface. 5. The board according to claim 4, characterized in that: The first switch switching circuit includes two signal output terminals, one signal output terminal of the first switch switching circuit is connected to the transmission channel of the DP interface and the eDP interface, and the other signal output terminal of the first switch switching circuit is connected to the transmission channel of the USB interface and the PCIe interface; The second switch switching circuit includes two signal input ends, one signal input end of the second switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input end of the second switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface. 6. A high-speed interface expansion board, characterized in that it comprises: A main control chip, a third switch switching circuit, a fourth switch switching circuit, a fifth switch switching circuit, a sixth switch switching circuit, a fourth high-speed serial interface, and at least two fifth high-speed serial interfaces of different types, wherein the main control chip is a chip having integrated a physical layer of a high-speed serial interface; The signal output end of the main control chip is connected to the signal input end of the third switch switching circuit, the signal output end of the third switch switching circuit is connected to the transmission channel of the fourth high-speed serial interface and the signal input end of the fourth switch switching circuit, and the signal output end of the fourth switch switching circuit is connected to the transmission channels of each fifth high-speed serial interface; The signal input end of the main control chip is connected to the signal output end of the fifth switch switching circuit, the signal input end of the fifth switch switching circuit is connected to the receiving channel of the fourth high-speed serial interface and the signal output end of the sixth switch switching circuit, and the signal input end of the sixth switch switching circuit is connected to the receiving channels of each fifth high-speed serial interface. 7. The board according to claim 6, characterized in that: The third switch switching circuit comprises two signal output terminals, one signal output terminal of the third switch switching circuit is connected to the transmission channel of the fourth high-speed serial interface, and the other signal output terminal of the third switch switching circuit is connected to the signal input terminal of the fourth switch switching circuit; The fifth switch switching circuit includes two signal input terminals, one signal input terminal of the fifth switch switching circuit is connected to the receiving channel of the fourth high-speed serial interface, and the other signal input terminal of the fifth switch switching circuit is connected to the signal output terminal of the sixth switch switching circuit. 8. The board according to claim 6 or 7, characterized in that: The fourth high-speed serial interface is a VBO interface; The fifth high-speed serial interface includes at least two of the following: a DP interface, an eDP interface, a USB interface, and a PCIe interface; and the USB interface includes a Type C interface. 9. The board according to claim 8, characterized in that: The fourth switch switching circuit has two signal output ends, one signal output end of the fourth switch switching circuit is connected to the transmission channel of the DP interface and the eDP interface, and the other signal output end of the fourth switch switching circuit is connected to the transmission channel of the USB interface and the PCIe interface; The sixth switch switching circuit has two signal input ends, one signal input end of the sixth switch switching circuit is connected to the receiving channel of the DP interface and the eDP interface, and the other signal input end of the sixth switch switching circuit is connected to the receiving channel of the USB interface and the PCIe interface. 10. An electronic device, comprising: the board card according to any one of claims 1 to 5, or the board card according to any one of claims 6 to 9.