CN113517361A

CN113517361A - Thermosensitive detector structure and integration method thereof

Info

Publication number: CN113517361A
Application number: CN202110262220.1A
Authority: CN
Inventors: 亨利·H·阿达姆松; 戚璇; 焦斌斌; 王桂磊
Original assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Current assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2021-10-19

Abstract

The invention relates to a heat-sensitive detector structure and an integration method thereof. A thermal detector structure comprises: a substrate with a readout circuit structure, on which a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are stacked in sequence; wherein , the dielectric layer has a cavity structure inside, and the intrinsic layer is an n-layer structure formed by alternately stacking Ge _1‑x Sn _x layers and Ge _1‑y Si _y layers, 0<x≤0.3, 0<y ≤0.3, n≥2. The present invention has a P-I-N suspended hollow structure, and after the light is absorbed, it can be reflected in the P-I-N structure in the hollow structure, and the absorption rate of light is significantly improved compared with the traditional detector.

Description

Thermosensitive detector structure and integration method thereof

Technical Field

The invention relates to the field of semiconductor devices, in particular to a thermosensitive detector structure and an integration method thereof.

Background

The heat-sensitive detector is a device for detecting by using the principle of thermal effect generated by irradiating an object with infrared radiation. This material, also known as a thermistor, has a conductivity that changes with the absorption of infrared photons. In the case of photons, when infrared photons emit light, electrons are obtained by the transition of the valence band to the conduction band. Due to the photon principle, imaging of such detectors provides high resolution in the short wavelength infrared band, but also absorbs longer infrared wavelengths. The influence on the absorption rate of infrared light directly influences the sensitivity, detection rate and other performances of the detector. The existing heat-sensitive detector is limited by low absorption rate of infrared light and has insufficient performance.

Disclosure of Invention

The invention mainly aims to provide a heat-sensitive detector structure, which is provided with a P-I-N suspension hollow structure, light can be reflected to the P-I-N structure in the hollow structure after being absorbed, and the light absorption rate is obviously improved compared with that of the traditional detector.

Another object of the present invention is to provide an integration method of the above-mentioned thermal detector structure, which uses amorphous silicon to form a cavity under the P-I-N stacked structure, and can improve the light absorption rate by utilizing the reflection of light in the cavity after light absorption, thereby improving the electrical performance of the thermal detector.

In order to achieve the above object, the present invention provides the following technical solutions.

A thermal detector structure comprising:

the substrate is provided with a reading circuit structure, and a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are sequentially stacked on the substrate;

wherein, the dielectric layer has a cavity structure therein, and the intrinsic layer is made of Ge_1-xSn_xLayer and Ge_1-ySi_yThe layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, y is more than 0 and less than or equal to 0.3, and n is more than or equal to 2.

A method of integrating a thermal-type detector structure, comprising:

providing a sacrificial substrate and a supporting substrate with a reading circuit structure, wherein the sacrificial substrate is formed by sequentially stacking a back substrate, an intrinsic layer and a P-type doped germanium layer; the intrinsic layer is made of Ge_1-xSn_xLayer and Ge_1-ySi_yThe layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, y is more than 0 and less than or equal to 0.3, and n is more than or equal to 2;

sequentially stacking a first dielectric layer and an amorphous silicon layer on the surface of the supporting substrate close to the reading circuit structure;

photoetching and etching the amorphous silicon layer to enable the amorphous silicon layer to only cover part of the surface of the first dielectric layer, then depositing a second dielectric layer, wherein the second dielectric layer is bordered by the first dielectric layer and wraps the amorphous silicon layer;

after the second dielectric layer is deposited, the read-out circuit structure and the P-type doped germanium layer in the supporting substrate are respectively used as bonding surfaces, and the supporting substrate and the sacrificial substrate are bonded;

removing the back substrate;

forming an N-type doped germanium layer on the surface of the intrinsic layer;

and etching to remove the amorphous silicon layer, so that a cavity structure is formed between the second dielectric layer and the first dielectric layer.

Compared with the prior art, the invention achieves the following technical effects.

(1) According to the invention, the amorphous silicon is used for forming the cavity below the P-I-N stacked structure, so that the light absorption rate can be improved by utilizing the reflection of the light absorbed in the cavity, and the electrical property of the thermosensitive detector is improved.

(2) The invention bonds the substrate which is also manufactured into a part of the detector structure in the substrate of the reading circuit structure, simplifies the integration flow, improves the integration level, is beneficial to reducing the system size, improving the system performance (reducing the length of the interconnection line) and the like.

(3) The intrinsic layer adopts Ge_1-xSn_xLayer and Ge_1-ySi_yThe layers are alternately stacked, so that the quantum effect is promoted, and the photoelectric conversion efficiency is enhanced.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.

FIG. 1 is a schematic diagram of an integrated structure of a detector provided by the present invention;

fig. 2 to 9 are schematic structural diagrams obtained in steps of the detector integration method provided in embodiment 1.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The thermal-type detector shown in fig. 1 includes a substrate 101 having a read-out circuit structure (ROIC) on which a dielectric layer, a P-type doped germanium layer 203, an intrinsic layer 202, and an N-type doped germanium layer 204 are sequentially stacked.

The dielectric layer has a cavity 105 therein, and may be formed by compounding multiple layers of the same or different materials, and usually employs silicon oxide.

The intrinsic layer 202 is made of Ge_1-xSn_xLayer and Ge_1-ySi_yThe layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, y is more than 0 and less than or equal to 0.3, and n is more than or equal to 2. In the intrinsic layer, Ge_1-xSn_xFor the compressive stress layer, Ge_1-ySi_yThe tensile stress layer is favorable for improving the quantum effect and enhancing the photoelectric conversion efficiency. Meanwhile, the material contacting the P-type doped germanium layer or the N-type doped germanium layer may be Ge_1- _xSn_xLayer or Ge_1-ySi_yAnd (3) a layer.

In addition, the number of alternation can be arbitrarily adjusted according to the device requirements, and the intrinsic layer may have a multilayer structure of 2 layers, 3 layers, 4 layers, etc., including but not limited to the intrinsic layer structure listed in table 1 below.

TABLE 1

The thermal detector shown in fig. 1 has various integration methods, such as preparing discrete devices first and then integrating, but because of the problems of inaccurate alignment, the present invention provides a method for manufacturing a photonic device after integrating, and the basic flow is as follows.

Preparing a substrate:

and providing a sacrificial substrate and a supporting substrate with a readout circuit structure, wherein the sacrificial substrate is formed by sequentially stacking a back substrate, an intrinsic layer and a P-type doped germanium layer.

Reforming a support substrate:

and photoetching and etching the amorphous silicon layer to enable the amorphous silicon layer to only cover part of the surface of the first dielectric layer, and then depositing a second dielectric layer, wherein the second dielectric layer is adjacent to the first dielectric layer and wraps the amorphous silicon layer.

Bonding:

and (3) bonding process:

removing the back substrate;

forming an N-type doped germanium layer on the surface of the intrinsic layer;

After the above procedure is completed, a specific detector structure may be fabricated in a P-I-N stack structure, and then the readout circuitry structure and the detector structure are interconnected.

According to the method provided by the invention, firstly, the amorphous silicon is used for forming the cavity below the P-I-N stacked structure, and the light absorption rate can be improved by utilizing the reflection in the cavity after light absorption, so that the electrical property of the thermosensitive detector is improved.

In addition, the invention simplifies the integration flow and improves the integration level, for example, the integration discrete devices have the problems of complexity, low integration level and the like in interconnection; another aspect is to fabricate the probe structure after integration, bypassing the problem of precise alignment (mainly referring to alignment of the electronic structure and the probe structure).

The method is suitable for any vertical type (indicating the arrangement direction of a PN structure) photoelectric device which needs to be integrated on a single silicon-based chip, so that no specific requirements are made on a reading circuit structure and a detector structure.

The supporting substrate and the sacrificial substrate targeted by the above method are mainly silicon-based substrates (but the invention is not limited thereto, and is also applicable to substrates of other semiconductor materials), but there is no specific requirement on the crystal orientation, the presence or absence of a buried oxide layer, and the like, and the supporting substrate and the sacrificial substrate may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), silicon germanium, and the like.

The method has no specific requirements on the first dielectric layer and the second dielectric layer. The dielectric layers mainly play a role in isolation, and the first dielectric layer and the second dielectric layer can be made of common silicon oxide. The first dielectric layer and the second dielectric layer can be respectively and independently selected from materials. The deposition method of the first dielectric layer and the second dielectric layer is also arbitrary, and includes but not limited to LPCVD, RTCVD, PECVD, thermal oxidation method, or plasma chemical vapor deposition method.

The method of forming the stacked intrinsic layers is also arbitrary and includes, but is not limited to, LPCVD, RTCVD, PECVD or evaporation, epitaxial growth, and the like.

The method of forming the N-type doped germanium layer is arbitrary and the N-doped germanium may be formed epitaxially or by implantation.

The above method has no particular requirement on the shape of the cavity, but is generally determined by the shape of the etched amorphous silicon. Therefore, it is necessary to define a good shape when lithographically etching amorphous silicon according to product requirements.

In addition, before bonding, the second dielectric layer can be subjected to planarization treatment such as chemical mechanical polishing.

The means for removing the back substrate after bonding is not limited, and one or more of grinding and polishing, wet etching, dry etching and CMP can be used for removing.

A preferred embodiment of the present invention is as follows.

Embodiment 1 a structure of a heat sensitive detector

Manufacturing a support substrate:

a substrate 101 having a readout circuitry structure is provided and then a first silicon oxide layer 102 is deposited on the surface of the readout circuitry structure resulting in the structure shown in fig. 2.

An amorphous silicon layer 103 is deposited on the surface of the first silicon oxide layer 102 resulting in the structure shown in fig. 3.

The amorphous silicon layer 103 is subjected to photolithography and etching, and a portion of amorphous silicon is removed to cover only a portion of the surface of the first silicon oxide layer 103, so as to obtain the structure shown in fig. 4.

A second silicon oxide layer 104 is deposited, the second silicon oxide layer 104 borders the first silicon oxide layer 102 and wraps the amorphous silicon layer to obtain the structure shown in fig. 5, and a planarization process (e.g., CMP) is performed.

Manufacturing a sacrificial substrate:

sequential deposition of Ge on a silicon substrate 201_1-xSn_xlayer/Ge_1-ySi_yThe layers (0 < x ≦ 0.3, 0 < y ≦ 0.3) of the intrinsic layer 202 and the P-type doped germanium layer 203 are alternately stacked to obtain the structure shown in fig. 6, followed by the surface smoothing treatment. Wherein Ge is in the intrinsic layer_1-xSn_xlayer/Ge_1-ySi_yThe number of times the layers are alternately repeated is arbitrary.

Bonding:

and bonding the support substrate and the sacrificial substrate by using the second silicon dioxide layer 104 and the P-type doped germanium layer 203 as bonding surfaces to form the structure shown in fig. 7.

The silicon substrate 201 is removed to form the structure shown in fig. 8.

An N-type doped germanium layer 204 is formed on the surface of the intrinsic layer to form the structure shown in fig. 9.

And etching to remove the amorphous silicon layer 103, so that a cavity 105 is formed between the second silicon oxide layer 104 and the first silicon oxide layer 102, and the structure shown in fig. 1 is formed.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. a heat-sensitive detector structure, is characterized in that, comprises:

a substrate with a readout circuit structure, on which a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are stacked in sequence;

Wherein, the dielectric layer has a cavity structure inside, and the intrinsic layer is an n-layer structure formed by alternately stacking Ge _1-x Sn _x layers and Ge _1-y Si _y layers, 0<x≤0.3, 0< y≤0.3, n≥2.

2 . The thermal detector structure according to claim 1 , wherein the dielectric layer is a silicon oxide layer. 3 .

3. An integrated method of a thermal detector structure, characterized in that, comprising:

Provide a sacrificial substrate and a supporting substrate with a readout circuit structure, the sacrificial substrate is formed by stacking a back substrate, an intrinsic layer and a P-type doped germanium layer in sequence; the intrinsic layer is composed of Ge _1- The n-layer structure formed by alternately stacking _x Sn _x layers and Ge _1-y Si _y layers, 0<x≤0.3, 0<y≤0.3, n≥2;

A first dielectric layer and an amorphous silicon layer are sequentially stacked on the surface of the support substrate close to the readout circuit structure;

Photolithography and etching are performed on the amorphous silicon layer to cover only part of the surface of the first dielectric layer, and then a second dielectric layer is deposited, the second dielectric layer bordering the first dielectric layer and wrapping the amorphous silicon layer;

After depositing the second dielectric layer, the readout circuit structure and the P-type doped germanium layer in the supporting substrate are used as bonding surfaces, respectively, and the supporting substrate and the sacrificial substrate are bonded together. Bond;

removing the backing substrate;

forming an N-type doped germanium layer on the surface of the intrinsic layer;

The amorphous silicon layer is removed by etching, so that a cavity structure is formed between the second dielectric layer and the first dielectric layer.

4. The integration method according to claim 3, wherein the second dielectric layer and the first dielectric layer are both silicon oxide layers.

5. The integration method according to claim 3, wherein the back substrate is silicon.

6 . The integration method according to claim 3 , wherein the first dielectric layer and the second dielectric layer are formed by a plasma chemical vapor deposition method. 7 .

7 . The integration method according to claim 3 , wherein chemical mechanical polishing is further performed on the second dielectric layer before the bonding. 8 .

8 . The integration method according to claim 3 , wherein the N-type doped germanium layer is formed by an epitaxy method. 9 .

9 . The integration method according to claim 3 , wherein the back substrate is removed by at least one of grinding and polishing, wet etching, dry etching and chemical mechanical polishing. 10 .