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CN113451313B - Method and device for designing semiconductor memory device, storage medium and preparation method - Google Patents

Method and device for designing semiconductor memory device, storage medium and preparation method Download PDF

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CN113451313B
CN113451313B CN202110721672.1A CN202110721672A CN113451313B CN 113451313 B CN113451313 B CN 113451313B CN 202110721672 A CN202110721672 A CN 202110721672A CN 113451313 B CN113451313 B CN 113451313B
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capacitors
capacitance value
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memory device
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CN113451313A (en
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永井享浩
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Fujian Jinhua Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The present application provides a design method, apparatus, storage medium and manufacturing method of a semiconductor memory device, the method includes dividing at least a first group of capacitors and a second group of capacitors from among the plurality of unit capacitors such that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the upper electrodes of the plurality of cell capacitors are each connected to a first interconnect metal layer, the lower electrodes of each cell capacitor in the first group of capacitors are each connected to a second interconnect metal layer, and the lower electrodes of each cell capacitor in the second group of capacitors are each connected to a third interconnect metal layer. Under the condition that the size of the whole semiconductor memory device is not changed (namely, the size of the upper electrode interconnection metal layer is not changed), the capacitance value of the whole semiconductor memory device is much smaller than the parallel capacitance value of all unit capacitors, and the process difficulty and the process cost are greatly reduced.

Description

Method and device for designing semiconductor memory device, storage medium and preparation method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and apparatus for designing a semiconductor memory device, a storage medium, and a method for manufacturing the same.
Background
In recent years, electronic products are designed with multiple functions and fast processing capability. In order to increase the processing power, such as a computer system or a multi-function electronic product, a large capacity of dynamic random access memory (Dynamic Random Access Memory, DRAM) is required.
There are two ways to store the capacitance of a DRAM, including a storage node and a plate capacitance. The capacitance value of the storage node is far greater than that of the plate capacitor under the same area, so that the SN capacitor area is far smaller than the grid capacitor area under the same capacitor target. Therefore, the storage node is widely used not only in the active area of the DRAM as a storage unit of the DRAM, but also in the Capacitor of the peripheral circuit of the DRAM, such as Metal-insulator-Metal Capacitor (MIMCAP).
However, in the DRAM of the storage node type, due to the lower electrode structure with a large aspect ratio and the manufacturing process of each film layer, if the size of the DRAM is too small, the film layer (mainly the upper electrode interconnection metal layer) is dropped, so that the DRAM has a minimum size limitation (the size of the upper electrode interconnection metal layer cannot be too small), which makes it difficult to achieve a smaller range of the capacitance value of the DRAM if the conventional connection method is adopted.
In this case, in the prior art, a capacitor series connection is often adopted, and two DRAMs are connected in series, so as to form a memory device with a lower capacitance value. However, in this case, the overall size of the memory device is increased, and other components are also changed to match the memory device during packaging, which results in a great increase in process difficulty and process cost.
Disclosure of Invention
In view of the above problems, the present application provides a method, an apparatus, a storage medium, and a method for manufacturing a semiconductor memory device, which solve the technical problems of process difficulty and cost increase caused by the existing memory device connected in series.
In a first aspect, the present application provides a method of designing a semiconductor memory device including a plurality of cell capacitors arranged in an array, the method comprising:
acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
dividing at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value such that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
connecting the upper electrodes of the plurality of unit capacitors to a first interconnection metal layer, connecting the lower electrodes of the unit capacitors of the first group of capacitors to a second interconnection metal layer, and connecting the lower electrodes of the unit capacitors of the second group of capacitors to a third interconnection metal layer;
and connecting the second interconnection metal layer with a first power supply voltage, and connecting the third interconnection metal layer with a second power supply voltage.
According to an embodiment of the present application, optionally, in the method for designing a semiconductor memory device described above, each of the unit capacitors in the first group of capacitors is connected in parallel to each other through the first interconnect metal layer and the second interconnect metal layer;
each cell capacitor in the second group of capacitors is connected in parallel with each other through the first interconnect metal layer and the third interconnect metal layer.
According to an embodiment of the present application, optionally, in the method for designing a semiconductor memory device described above, the first group of capacitors includes a first number of cell capacitors, and the second group of capacitors includes a second number of cell capacitors; the target capacitance value, the capacitance value of the single cell capacitor, the first number, and the second number satisfy the following relation:
Figure BDA0003137040630000021
wherein C is T For the target capacitance value, a is the first quantity, b is the second quantity, C 0 Is the capacitance value of a single cell capacitor.
According to an embodiment of the present application, optionally, the method for designing a semiconductor memory device further includes:
the lower electrodes of all the unit capacitors except the first group of capacitors and the second group of capacitors are connected to a fourth interconnection metal layer.
According to an embodiment of the present application, optionally, the method for designing a semiconductor memory device further includes:
interconnecting the fourth interconnect metal layer with the first interconnect metal layer.
According to an embodiment of the present application, optionally, the method for designing a semiconductor memory device further includes:
the lower electrodes of all the unit capacitors except the first and second groups of capacitors are connected to fourth and fifth interconnection metal layers, respectively.
According to an embodiment of the present application, optionally, the method for designing a semiconductor memory device further includes:
interconnecting the fourth interconnect metal layer with the first interconnect metal layer.
According to an embodiment of the present application, optionally, the method for designing a semiconductor memory device further includes:
interconnecting the fifth interconnect metal layer with the first interconnect metal layer.
In a second aspect, the present application provides a design apparatus of a semiconductor memory device including a plurality of cell capacitors arranged in an array, comprising:
a capacitance value acquisition module for acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
a capacitance dividing module for dividing at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value, so that the series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
an electrode connection module for connecting upper electrodes of the plurality of unit capacitors to the first interconnection metal layer, connecting lower electrodes of the respective unit capacitors of the first group of capacitors to the second interconnection metal layer, and connecting lower electrodes of the respective unit capacitors of the second group of capacitors to the third interconnection metal layer;
and the voltage connection module is used for connecting the second interconnection metal layer with the first power supply voltage and connecting the third interconnection metal layer with the second power supply voltage.
In a third aspect, the present application provides an electronic device including a memory and a processor, the memory having stored thereon a computer program which, when executed by the processor, performs the method of designing a semiconductor memory device according to any one of the first aspects.
In a fourth aspect, the present application provides a storage medium storing a computer program which, when executed by one or more processors, implements the method of designing a semiconductor memory device according to any one of the first aspects.
In a fifth aspect, the present application provides a method for manufacturing a semiconductor memory device, including:
a corresponding semiconductor memory device is prepared according to the design drawing designed by the method according to any one of the first aspects.
In a sixth aspect, the present application provides a semiconductor memory device comprising: prepared by the method according to the fifth aspect.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
the present application provides a design method, apparatus, storage medium and manufacturing method of a semiconductor memory device, the method including dividing at least a first group of capacitors and a second group of capacitors from among the plurality of unit capacitors according to the target capacitance value such that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the upper electrodes of the plurality of cell capacitors are each connected to a first interconnect metal layer, the lower electrodes of each cell capacitor in the first group of capacitors are each connected to a second interconnect metal layer, and the lower electrodes of each cell capacitor in the second group of capacitors are each connected to a third interconnect metal layer. Under the condition that the size of the whole semiconductor memory device is not changed (namely, the size of the upper electrode interconnection metal layer is not changed), the capacitance value of the whole semiconductor memory device can be changed, so that the capacitance value of the whole semiconductor memory device is much smaller than the parallel capacitance value of all the unit capacitors, the connection mode of each unit capacitor can be changed according to the target capacitance value, and the process difficulty and the process cost are greatly reduced.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and, together with the description, do not limit the application. In the drawings:
fig. 1 is a flow chart illustrating a method of designing a semiconductor memory device according to an exemplary embodiment of the present application;
fig. 2 is a schematic top view of a semiconductor memory device designed according to the method shown in fig. 1;
FIG. 3 is a schematic cross-sectional view of FIG. 2 along line A-A';
FIG. 4 is a schematic diagram of an equivalent circuit of FIG. 2;
fig. 5 is a schematic top view of another semiconductor memory device designed in accordance with the method shown in fig. 1;
FIG. 6 is a schematic diagram of an equivalent circuit of FIG. 5;
fig. 7 is a schematic top view of another semiconductor memory device designed in accordance with the method shown in fig. 1;
FIG. 8 is a schematic diagram of an equivalent circuit of FIG. 7;
fig. 9 is a schematic top view of another semiconductor memory device designed in accordance with the method shown in fig. 1;
FIG. 10 is a schematic diagram of an equivalent circuit of FIG. 9;
fig. 11 is a connection block diagram of a design apparatus of a semiconductor memory device shown in an exemplary embodiment of the present application;
in the drawings, wherein like parts are designated by like reference numerals throughout, the drawings are not to scale;
the reference numerals are:
11-cell capacitors; 111-a lower electrode; 112-an insulating layer; 113-an upper electrode; 12-a first interconnect metal layer; 13-a second interconnect metal layer; 14-a third interconnect metal layer; 15-a fourth interconnect metal layer; 16-a first connector; 17-a second connector; 18-a third connector; c1-a first set of capacitors; c2-a second set of capacitors; c3_third set of capacitors; c4-fourth set of capacitors; v1-a first supply voltage; v2-a second supply voltage; 21-cell capacitors; 22-a first interconnect metal layer; 23-a second interconnect metal layer; 24-a third interconnect metal layer; 25-fourth interconnect metal layers; 26-a fifth interconnect metal layer; 27-a first connector; 28-a second connector; 29-a third connector; 30-fourth connection.
Detailed Description
The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby how to apply technical means to the present application to solve technical problems, and realizing processes achieving corresponding technical effects can be fully understood and implemented accordingly. The embodiments and the features in the embodiments can be combined with each other under the condition of no conflict, and the formed technical schemes are all within the protection scope of the application. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present application, detailed structures and steps are set forth in the following description in order to illustrate the technical solutions set forth herein. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.
Example 1
As shown in fig. 1, an embodiment of the present application provides a method for designing a semiconductor memory device including a plurality of cell capacitors 11 (i.e., storage node capacitors SN) arranged in an array, the method including:
step S110: acquiring a target capacitance value of the semiconductor memory device and a capacitance value of the single cell capacitor 11; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors 11.
The semiconductor memory device in this embodiment may be a DRAM, and the upper electrodes of the respective unit capacitors of the conventional DRAM are connected to the upper electrode interconnection metal layer, and the lower electrodes are connected to the lower electrode interconnection metal layer, so that the total capacitance value of the DRAM is the parallel capacitance value of all the unit capacitors, that is, the sum of the capacitance values of the respective unit capacitors.
The present embodiment is aimed at reducing the total capacitance value of the DRAM without changing the size of the DRAM (the number of cell capacitors is unchanged, and the size of the upper electrode interconnect metal layer is unchanged), that is, the target capacitance value finally obtained by the semiconductor memory device is smaller than the parallel capacitance value (sum of the capacitance values of the respective cell capacitors 11) of the plurality of cell capacitors 11.
Each of the cell capacitors 11 includes a lower electrode 111, an insulating layer 112, and an upper electrode 113, wherein the lower electrode 111 may have a long cylindrical shape having a certain aspect ratio.
Step S120: dividing at least a first group capacitor C1 and a second group capacitor C2 from among the plurality of unit capacitors 11 in accordance with the target capacitance value such that a series capacitance value of the first group capacitor C1 and the second group capacitor C2 is equal to the target capacitance value; the capacitance value of the first group of capacitors C1 is the parallel capacitance value of all the unit capacitors 11 in the first group of capacitors C1, and the capacitance value of the second group of capacitors C2 is the parallel capacitance value of all the unit capacitors 11 in the second group of capacitors C2.
That is, the first group of capacitors C1 includes a first number of cell capacitors 11, and the second group of capacitors C2 includes a second number of cell capacitors 11; the target capacitance value, the capacitance value of the single cell capacitor 11, the first number, and the second number satisfy the following relation:
Figure BDA0003137040630000071
wherein C is T For the target capacitance value, a is the first quantity, b is the second quantity, C 0 Is the capacitance value of the single cell capacitor 11.
That is, the present embodiment is more suitable for the case where the target capacitance value is 0.5 times or less the parallel capacitance value of the plurality of unit capacitors 1111.
Step S130: as shown in fig. 2 and 3, the upper electrodes 113 of the plurality of cell capacitors 11 are each connected to the first interconnect metal layer 12, the lower electrodes 111 of the respective cell capacitors 11 in the first group of capacitors C1 are each connected to the second interconnect metal layer 13, and the lower electrodes 111 of the respective cell capacitors 11 in the second group of capacitors C2 are each connected to the third interconnect metal layer 14.
The respective unit capacitors 11 in the first group of capacitors C1 are connected in parallel to each other through the first interconnect metal layer 12 and the second interconnect metal layer 13.
The respective unit capacitors 11 in the second group of capacitors C2 are connected in parallel to each other through the first interconnect metal layer 12 and the third interconnect metal layer 14.
The second interconnect metal layer 13 is spaced apart from the third interconnect metal layer 14 without a connection therebetween.
Thus, the respective unit capacitors 11 in the first group capacitor C1 are obtained in parallel, the respective unit capacitors 11 in the second group capacitor C2 are connected in parallel, and then the first group capacitor C1 and the second group capacitor C2 are connected in series since the upper electrodes 113 of the respective unit capacitors 11 in the first group capacitor C1 and the respective unit capacitors 11 in the second group capacitor C2 are connected to the first interconnect metal layer 12.
Step S140: the second interconnect metal layer 13 is connected to a first supply voltage V1 and the third interconnect metal layer 14 is connected to a second supply voltage V2.
The first power voltage V1 may be a power anode voltage Vdd, and the second power voltage V2 may be a power cathode voltage Vss.
Specifically, the second interconnection metal layer 13 may be connected to the first power voltage V1 through the first connection 16, and the third interconnection metal layer 14 may be connected to the second power voltage V2 through the second connection 17.
In the present embodiment, the lower electrodes 111 of all the unit capacitors 11 except the first group capacitor C1 and the second group capacitor C2 among the plurality of unit capacitors 11 are connected to the fourth interconnection metal layer 15, and since the upper electrodes 113 of the portion of the unit capacitors 11 (the C3 portion and the C4 portion) are connected to the first interconnection metal layer 12 and the lower electrodes 111 are connected to the fourth interconnection metal layer 15, the portion of the unit capacitors 11 (the C3 portion and the C4 portion) are connected in parallel. The fourth interconnect metal layer 15 is spaced apart from the second interconnect metal layer 13 and the third interconnect metal layer 14, and there is no connection between any two.
Subsequently, the fourth interconnect metal layer 15 may optionally be disconnected from the voltage signal, as shown in fig. 2 and 4; the fourth interconnect metal layer 15 and the first interconnect metal layer 12 may also be interconnected as shown in fig. 5 and 6.
That is, the lower electrodes 111 of all the unit capacitors 11 except the first and second groups of capacitors C1 and C2 may be selectively not connected to the voltage signal, or may be interconnected with the upper electrodes 112 through the third connection member 18, in both of which the unit capacitors 11 except the first and second groups of capacitors C1 and C2 do not contribute to the capacitance value of the entire semiconductor memory device, which is only related to the first and second groups of capacitors C1 and C2.
In this way, without changing the size of the entire semiconductor memory device (i.e., without changing the size of the upper electrode interconnection metal layer), the capacitance of the entire semiconductor memory device can be changed so that the capacitance of the entire semiconductor memory device is much smaller than the parallel capacitance of all the cell capacitors 11, and the connection manner of each cell capacitor 11 can be changed according to the target capacitance, so that the applicability is strong, and the process difficulty and the process cost are greatly reduced.
The embodiment of the application provides a design method of a semiconductor memory device, according to the target capacitance value, at least a first group of capacitors C1 and a second group of capacitors C2 are divided from the plurality of unit capacitors 11, so that the series capacitance value of the first group of capacitors C1 and the second group of capacitors C2 is equal to the target capacitance value; the upper electrodes 113 of the plurality of cell capacitors 11 are each connected to the first interconnect metal layer 12, the lower electrodes 111 of the respective cell capacitors 11 in the first group of capacitors C1 are each connected to the second interconnect metal layer 13, and the lower electrodes 111 of the respective cell capacitors 11 in the second group of capacitors C2 are each connected to the third interconnect metal layer 14. Under the condition that the size of the whole semiconductor memory device (namely, the size of the upper electrode interconnection metal layer) is not changed, the capacitance value of the whole semiconductor memory device can be changed, so that the capacitance value of the whole semiconductor memory device is much smaller than the parallel capacitance value of all the unit capacitors 11, the connection mode of each unit capacitor 11 can be changed according to the target capacitance value, and the process difficulty and the process cost are greatly reduced.
Example two
Another embodiment of the present application provides a method for designing a semiconductor memory device including a plurality of cell capacitors 21 (i.e., storage node capacitors SN) arranged in an array, the method including:
step S210: acquiring a target capacitance value of the semiconductor memory device and a capacitance value of the single cell capacitor 21; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors 21.
The semiconductor memory device in this embodiment may be a DRAM, and the upper electrodes of the respective unit capacitors of the conventional DRAM are connected to the upper electrode interconnection metal layer, and the lower electrodes are connected to the lower electrode interconnection metal layer, so that the total capacitance value of the DRAM is the parallel capacitance value of all the unit capacitors, that is, the sum of the capacitance values of the respective unit capacitors.
The present embodiment is aimed at reducing the total capacitance value of the DRAM without changing the size of the DRAM (the number of cell capacitors is unchanged, and the size of the upper electrode interconnect metal layer is unchanged), that is, the target capacitance value finally obtained by the semiconductor memory device is smaller than the parallel capacitance value (sum of the capacitance values of the respective cell capacitors 21) of the plurality of cell capacitors 21.
Each of the cell capacitors 21 includes a lower electrode (not shown in the drawing), an insulating layer (not shown in the drawing), and an upper electrode (not shown in the drawing), wherein the lower electrode may have a long cylindrical shape with a certain aspect ratio.
Step S220: dividing at least a first group capacitor C1 and a second group capacitor C2 from the plurality of unit capacitors 21 in accordance with the target capacitance value such that a series capacitance value of the first group capacitor C1 and the second group capacitor C2 is equal to the target capacitance value; the capacitance value of the first group of capacitors C1 is the parallel capacitance value of all the unit capacitors 21 in the first group of capacitors C1, and the capacitance value of the second group of capacitors C2 is the parallel capacitance value of all the unit capacitors 21 in the second group of capacitors C2.
That is, the first group of capacitors C1 includes a first number of unit capacitors 21, and the second group of capacitors C2 includes a second number of unit capacitors 21; the target capacitance value, the capacitance value of the single cell capacitor 21, the first number, and the second number satisfy the following relation:
Figure BDA0003137040630000091
wherein C is T For the target capacitance value, a is the first quantity, b is the second quantity, C 0 Is the capacitance value of the single cell capacitor 21.
That is, the present embodiment is more suitable for the case where the target capacitance value is 0.5 times or less the parallel capacitance value of the plurality of unit capacitors 21.
Step S230: as shown in fig. 7, the upper electrodes 223 of the plurality of cell capacitors 21 are each connected to the first interconnect metal layer 22, the lower electrodes 211 of the respective cell capacitors 21 in the first group of capacitors C1 are each connected to the second interconnect metal layer 23, and the lower electrodes 211 of the respective cell capacitors 21 in the second group of capacitors C2 are each connected to the third interconnect metal layer 24.
The respective unit capacitors 21 in the first group of capacitors C1 are connected in parallel to each other through the first interconnect metal layer 22 and the second interconnect metal layer 23.
The respective unit capacitors 21 in the second group of capacitors C2 are connected in parallel to each other through the first interconnect metal layer 22 and the third interconnect metal layer 24.
The second interconnect metal layer 23 is spaced apart from the third interconnect metal layer 24 without a connection therebetween.
Thus, the respective unit capacitors 21 in the first group capacitor C1 are obtained in parallel, the respective unit capacitors 21 in the second group capacitor C2 are connected in parallel, and then the first group capacitor C1 and the second group capacitor C2 are connected in series since the upper electrodes 223 of the respective unit capacitors 21 in the first group capacitor C1 and the respective unit capacitors 21 in the second group capacitor C2 are connected to the first interconnect metal layer 22.
Step S240: the second interconnect metal layer 23 is connected to a first supply voltage V1 and the third interconnect metal layer 24 is connected to a second supply voltage V2.
The first power voltage V1 may be a power anode voltage Vdd, and the second power voltage V2 may be a power cathode voltage Vss.
Specifically, the second interconnection metal layer 23 may be connected to the first power voltage V1 through the first connection 27, and the third interconnection metal layer 24 may be connected to the second power voltage V2 through the second connection 28
In the present embodiment, the lower electrodes 211 of all the unit capacitors 21 except the first group capacitor C1 and the second group capacitor C2 among the plurality of unit capacitors 21 are connected to the fourth interconnection metal layer 25 and the fifth interconnection metal layer 26, respectively, since the upper electrodes 223 of the portion of the unit capacitors 21 (C3 portion and C4 portion) are both connected to the first interconnection metal layer 22, the lower electrodes 211 are connected to the fourth interconnection metal layer 25 and the fifth interconnection metal layer 26, respectively, the unit capacitors 21 connected to the fourth interconnection metal layer 25 constitute the third group capacitor C3, and the unit capacitors 21 connected to the fifth interconnection metal layer 26 constitute the fourth group capacitor C4. The cell capacitors 21 in the third group of capacitors C3 are connected in parallel, the cell capacitors 21 in the fourth group of capacitors C4 are connected in parallel, and then the third group of capacitors C3 is connected in series with the fourth group of capacitors C4. The fourth interconnect metal layer 25, the fifth interconnect metal layer 26, the second interconnect metal layer 23, and the third interconnect metal layer 24 are disposed at intervals from each other, and there is no connection between any two.
Subsequently, the fourth interconnect metal layer 25 may optionally not be connected to a voltage signal, but may also be interconnected to the first interconnect metal layer 22 by a third connection 29; likewise, the fifth interconnect metal layer 26 may alternatively not be connected to a voltage signal, but may also be interconnected to the first interconnect metal layer 22 by a fourth connection 30.
When the fourth interconnect metal layer 25 and the fifth interconnect metal layer 26 are simultaneously selected to be disconnected from the voltage signal, the resulting schematic top view structure is shown in fig. 7, and the corresponding equivalent circuit diagram is shown in fig. 8.
When the fourth interconnect metal layer 25 and the fifth interconnect metal layer 26 are simultaneously selected to be connected to each other with the first interconnect metal layer 22, the resulting schematic top view structure is shown in fig. 9, and the corresponding equivalent circuit diagram is shown in fig. 10.
In both of the above-described modes, all the cell capacitors 21 except the first group capacitor C1 and the second group capacitor C2 do not contribute to the capacitance value of the entire semiconductor memory device, which is related only to the first group capacitor C1 and the second group capacitor C2.
In this way, without changing the size of the entire semiconductor memory device (i.e., without changing the size of the upper electrode interconnection metal layer), the capacitance value of the entire semiconductor memory device can be changed so that the capacitance value of the entire semiconductor memory device is much smaller than the parallel capacitance value of all the cell capacitors 21, and the connection manner of each cell capacitor 21 can be changed according to the target capacitance value, so that the applicability is strong, and the process difficulty and the process cost are greatly reduced.
The embodiment of the application provides a design method of a semiconductor memory device, according to the target capacitance value, at least a first group of capacitors C1 and a second group of capacitors C2 are divided from the plurality of unit capacitors 21, so that the series capacitance value of the first group of capacitors C1 and the second group of capacitors C2 is equal to the target capacitance value; the upper electrodes 223 of the plurality of cell capacitors 21 are each connected to the first interconnect metal layer 22, the lower electrodes 211 of each cell capacitor 21 in the first group of capacitors are each connected to the second interconnect metal layer 23, and the lower electrodes 211 of each cell capacitor 21 in the second group of capacitors C2 are each connected to the third interconnect metal layer 24. Under the condition that the size of the whole semiconductor memory device (namely, the size of the upper electrode interconnection metal layer) is not changed, the capacitance value of the whole semiconductor memory device can be changed, so that the capacitance value of the whole semiconductor memory device is much smaller than the parallel capacitance value of all the unit capacitors 21, the connection mode of each unit capacitor 21 can be changed according to the target capacitance value, and the process difficulty and the process cost are greatly reduced.
Example III
Referring to fig. 11, the present embodiment provides a semiconductor memory device design apparatus 100, including: the device comprises a capacitance value acquisition module 110, a capacitance dividing module 120, an electrode connection module 130 and a voltage connection module 140.
A capacitance value acquisition module 110 for acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
a capacitance dividing module 120, configured to divide at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value, so that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
an electrode connection module 130 for connecting upper electrodes of the plurality of unit capacitors to the first interconnection metal layer, connecting lower electrodes of the respective unit capacitors of the first group of capacitors to the second interconnection metal layer, and connecting lower electrodes of the respective unit capacitors of the second group of capacitors to the third interconnection metal layer;
and the voltage connection module 140 is used for connecting the second interconnection metal layer with a first power supply voltage and connecting the third interconnection metal layer with a second power supply voltage.
The specific embodiment process of the above method steps can be referred to as embodiment one or two, and this embodiment is not repeated here.
Example IV
The present embodiment provides an electronic device, which may be a mobile phone, a computer, or a tablet computer, and includes a memory and a processor, where the memory stores a computer program, and the computer program when executed by the processor implements the method for designing a semiconductor memory device as described in the second embodiment. It is to be appreciated that the electronic device can also include an input/output (I/O) interface, as well as a communication component.
Wherein the processor is configured to execute all or part of the steps in the method of designing a semiconductor memory device as in the second embodiment. The memory is used to store various types of data, which may include, for example, instructions for any application or method in the electronic device, as well as application-related data.
The processor may be an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), a digital signal processor (Digital Signal Processor, abbreviated as DSP), a digital signal processing device (Digital Signal Processing Device, abbreviated as DSPD), a programmable logic device (Programmable Logic Device, abbreviated as PLD), a field programmable gate array (Field Programmable Gate Array, abbreviated as FPGA), a controller, a microcontroller, a microprocessor, or other electronic component implementation for executing the method for designing a semiconductor memory device in the above embodiment.
The Memory may be implemented by any type of volatile or non-volatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read-Only Memory, PROM for short), read-Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk or optical disk.
Example five
The present embodiment provides a computer readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, a server, an App application store, etc., on which a computer program is stored, which when executed by a processor, can implement the following method steps:
step S110: acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
step S120: dividing at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value such that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
step S130: connecting the upper electrodes of the plurality of unit capacitors to a first interconnection metal layer, connecting the lower electrodes of the unit capacitors of the first group of capacitors to a second interconnection metal layer, and connecting the lower electrodes of the unit capacitors of the second group of capacitors to a third interconnection metal layer;
step S140: and connecting the second interconnection metal layer with a first power supply voltage, and connecting the third interconnection metal layer with a second power supply voltage.
The specific embodiment process of the above method steps can be referred to as embodiment one or two, and this embodiment is not repeated here.
Example six
The embodiment of the application provides a preparation method of a semiconductor memory device, which comprises the following steps: the corresponding semiconductor memory device is prepared according to the design drawing designed by the method as described in the first embodiment or the second embodiment.
The semiconductor memory device manufactured according to the design drawing designed by the method described in the first embodiment or the second embodiment has a capacitance value much smaller than that of the conventional semiconductor memory device without a change in size, and thus the process difficulty and the process cost are greatly reduced.
While the embodiments disclosed herein are described above, the descriptions are presented only to facilitate an understanding of the present application and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of protection of this application shall be subject to the scope of the claims that follow.

Claims (13)

1. A method of designing a semiconductor memory device including a plurality of cell capacitors arranged in an array, the method comprising:
acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
dividing at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value such that a series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
connecting the upper electrodes of the plurality of unit capacitors to a first interconnection metal layer, connecting the lower electrodes of the unit capacitors of the first group of capacitors to a second interconnection metal layer, and connecting the lower electrodes of the unit capacitors of the second group of capacitors to a third interconnection metal layer;
and connecting the second interconnection metal layer with a first power supply voltage, and connecting the third interconnection metal layer with a second power supply voltage.
2. The method of claim 1, wherein individual cell capacitors of the first set of capacitors are connected in parallel with each other through the first interconnect metal layer and the second interconnect metal layer;
each cell capacitor in the second group of capacitors is connected in parallel with each other through the first interconnect metal layer and the third interconnect metal layer.
3. The method of claim 2, wherein the first set of capacitors comprises a first number of cell capacitors and the second set of capacitors comprises a second number of cell capacitors; the target capacitance value, the capacitance value of the single cell capacitor, the first number, and the second number satisfy the following relation:
Figure FDA0003137040620000011
wherein C is T For the target capacitance value, a is the first quantity, b is the second quantity, C 0 Is the capacitance value of a single cell capacitor.
4. The method as recited in claim 1, further comprising:
the lower electrodes of all the unit capacitors except the first group of capacitors and the second group of capacitors are connected to a fourth interconnection metal layer.
5. The method as recited in claim 4, further comprising:
interconnecting the fourth interconnect metal layer with the first interconnect metal layer.
6. The method as recited in claim 1, further comprising:
the lower electrodes of all the unit capacitors except the first and second groups of capacitors are connected to fourth and fifth interconnection metal layers, respectively.
7. The method as recited in claim 6, further comprising:
interconnecting the fourth interconnect metal layer with the first interconnect metal layer.
8. The method as recited in claim 7, further comprising:
interconnecting the fifth interconnect metal layer with the first interconnect metal layer.
9. A capacitance designing apparatus of a semiconductor memory device including a plurality of cell capacitors arranged in an array, comprising:
a capacitance value acquisition module for acquiring a target capacitance value of the semiconductor memory device and a capacitance value of a single cell capacitor; wherein the target capacitance value is smaller than the parallel capacitance value of the plurality of unit capacitors;
a capacitance dividing module for dividing at least a first group of capacitors and a second group of capacitors from the plurality of unit capacitors according to the target capacitance value, so that the series capacitance value of the first group of capacitors and the second group of capacitors is equal to the target capacitance value; the capacitance value of the first group of capacitors is the parallel capacitance value of all the unit capacitors in the first group of capacitors, and the capacitance value of the second group of capacitors is the parallel capacitance value of all the unit capacitors in the second group of capacitors;
an electrode connection module for connecting upper electrodes of the plurality of unit capacitors to the first interconnection metal layer, connecting lower electrodes of the respective unit capacitors of the first group of capacitors to the second interconnection metal layer, and connecting lower electrodes of the respective unit capacitors of the second group of capacitors to the third interconnection metal layer;
and the voltage connection module is used for connecting the second interconnection metal layer with the first power supply voltage and connecting the third interconnection metal layer with the second power supply voltage.
10. An electronic device comprising a memory and a processor, wherein the memory has stored thereon a computer program which, when executed by the processor, performs the method of designing a semiconductor memory device according to any one of claims 1 to 8.
11. A storage medium storing a computer program which, when executed by one or more processors, implements the method of designing a semiconductor memory device according to any one of claims 1 to 8.
12. A method of manufacturing a semiconductor memory device, comprising:
a corresponding semiconductor memory device is prepared according to a design drawing designed by the method as claimed in any one of claims 1 to 8.
13. A semiconductor memory device manufactured by the method of claim 12.
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