CN110544682A - Method for forming parallel capacitor and parallel capacitor - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000002955 isolation Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000000126 substance Substances 0.000 claims description 9
- 238000007517 polishing process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 abstract description 9
- 239000000463 material Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- 150000001869 cobalt compounds Chemical class 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- -1 silicon gallium compound Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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Abstract
本发明提供了一种形成并联电容器的方法及并联电容器，形成并联电容器的方法包括：提供一衬底，所述衬底上形成有第一导电层、第一介质层及第二导电层，所述第一导电层、第一介质层及第二导电层构成第一电容器；在所述第二导电层上形成第二介质层及隔离层，并研磨去除所述第二介质层上的隔离层；在所述第二介质层上形成互连层，所述互连层、所述第二介质层及所述第二导电层构成第二电容器，所述第一电容器和所述电容器构成并联电容器。在无需增加新的光罩的情况下形成与所述第一电容器并联的第二电容器，提高了器件的总电容值。
The present invention provides a method for forming a parallel capacitor and the parallel capacitor. The method for forming the parallel capacitor includes: providing a substrate on which a first conductive layer, a first dielectric layer, and a second conductive layer are formed. The first conductive layer, the first dielectric layer and the second conductive layer constitute a first capacitor; a second dielectric layer and an isolation layer are formed on the second conductive layer, and the isolation layer on the second dielectric layer is removed by grinding ; forming an interconnection layer on the second dielectric layer, the interconnection layer, the second dielectric layer and the second conductive layer constitute a second capacitor, and the first capacitor and the capacitor constitute a parallel capacitor . Forming a second capacitor in parallel with the first capacitor without adding a new photomask increases the overall capacitance of the device.
Description
技术领域technical field
本发明涉及半导体制造技术领域，特别涉及一种形成并联电容器的方法及并联电容器。The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a parallel capacitor and the parallel capacitor.
背景技术Background technique
PIP(多晶硅-绝缘层-多晶硅)电容器是一种广泛应用于频率调制和防止模拟电路发射噪声的器件。A PIP (Poly-Insulator-Poly) capacitor is a device widely used in frequency modulation and to prevent noise emission from analog circuits.
但是目前的PIP结构的电容器通常存在电容值较小的问题，从而导致集成电路的滤波效果差的缺陷。目前为了提高PIP结构的电容器的电容值，通常的做法是使用新的光罩，在一PIP结构的电容器上再形成与其并联的另一PIP结构的电容器，但是这样会额外增加光刻、刻蚀等多道工艺步骤，这势必增加了工艺时长，降低了工作效率，同时也不符合尺寸较小的半导体器件的要求，所以急需一种新的形成并联电容器的方法，以在尽量不增加额外的工艺步骤的情况下来解决PIP结构的电容器的电容值较小的问题。However, the capacitors of the current PIP structure usually have the problem of small capacitance value, which leads to the defect that the filtering effect of the integrated circuit is poor. At present, in order to increase the capacitance value of the capacitor of the PIP structure, the common practice is to use a new photomask to form a capacitor of another PIP structure in parallel with it on the capacitor of the PIP structure, but this will increase the cost of photolithography and etching. Wait for multiple process steps, which will inevitably increase the process time, reduce the work efficiency, and also do not meet the requirements of smaller semiconductor devices, so there is an urgent need for a new method of forming parallel capacitors, so as not to increase additional In the case of the process steps, the problem of the small capacitance value of the capacitor with the PIP structure is solved.
发明内容Contents of the invention
本发明的目的在于提供一种形成并联电容器的方法及并联电容器，以解决在不增加额外的工艺步骤的情况下增大PIP结构的电容器的电容值的问题。The object of the present invention is to provide a method for forming a parallel capacitor and the parallel capacitor, so as to solve the problem of increasing the capacitance value of a capacitor with a PIP structure without adding additional process steps.
为解决上述技术问题，本发明提供一种形成并联电容器的方法，包括：In order to solve the above technical problems, the present invention provides a method for forming parallel capacitors, including:
提供一衬底；providing a substrate;
依次形成第一导电层、第一介质层以及第二导电层，所述第一导电层覆盖所述衬底的部分表面，所述第一介质层覆盖所述第一导电层，所述第二导电层覆盖所述第一介质层的部分表面及所述衬底，其中，相互堆叠的所述第一导电层、第一介质层及第二导电层构成第一电容器；sequentially forming a first conductive layer, a first dielectric layer and a second conductive layer, the first conductive layer covers part of the surface of the substrate, the first dielectric layer covers the first conductive layer, and the second A conductive layer covers part of the surface of the first dielectric layer and the substrate, wherein the first conductive layer, the first dielectric layer and the second conductive layer stacked on each other form a first capacitor;
形成第二介质层，所述第二介质层覆盖所述第二导电层；forming a second dielectric layer, the second dielectric layer covering the second conductive layer;
形成隔离层，所述隔离层覆盖所述第二介质层及所述第一介质层；forming an isolation layer, the isolation layer covering the second dielectric layer and the first dielectric layer;
执行化学机械研磨工艺，以去除位于所述第二介质层上的所述隔离层；performing a chemical mechanical polishing process to remove the isolation layer on the second dielectric layer;
形成第一插塞、第二插塞和互连层，所述第一插塞贯穿所述隔离层以及第一介质层并与所述第一导电层电连接，所述第二插塞贯穿所述隔离层以及第二介质层并与所述第二导电层电连接，所述互连层形成于所述隔离层以及第二介质层上，所述第一插塞和第二插塞分别与所述互连层电连接，且所述第一插塞和第二插塞相互绝缘。forming a first plug, a second plug and an interconnection layer, the first plug penetrates the isolation layer and the first dielectric layer and is electrically connected to the first conductive layer, the second plug penetrates the The isolation layer and the second dielectric layer are electrically connected to the second conductive layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, and the first plug and the second plug are respectively connected to the The interconnection layers are electrically connected, and the first plug and the second plug are insulated from each other.
可选的，在所述形成并联电容器的方法中，所述第二导电层、所述第二介质层及所述互联层构成第二电容器，所述第一电容器和所述第二电容器构成并联电容器，所述并联电容器的电容值大于或者等于3.3fF/μm2。Optionally, in the method for forming a parallel capacitor, the second conductive layer, the second dielectric layer, and the interconnection layer form a second capacitor, and the first capacitor and the second capacitor form a parallel capacitor. A capacitor, the capacitance of the parallel capacitor is greater than or equal to 3.3 fF/μm 2 .
可选的，在所述形成并联电容器的方法中，所述第一介质层的材质为氧化硅。Optionally, in the method for forming a parallel capacitor, the material of the first dielectric layer is silicon oxide.
可选的，在所述形成并联电容器的方法中，通过高温氧化工艺形成所述第一介质层。Optionally, in the method for forming a parallel capacitor, the first dielectric layer is formed through a high temperature oxidation process.
可选的，在所述形成并联电容器的方法中，所述第二介质层的材质为氮化硅或者氮氧化硅。Optionally, in the method for forming a parallel capacitor, the material of the second dielectric layer is silicon nitride or silicon oxynitride.
可选的，在所述形成并联电容器的方法中，所述第一导电层、第二导电层的材质均为多晶硅。Optionally, in the method for forming a parallel capacitor, the first conductive layer and the second conductive layer are made of polysilicon.
可选的，在所述形成并联电容器的方法中，所述第一介质层的厚度介于之间。Optionally, in the method for forming a parallel capacitor, the thickness of the first dielectric layer is between between.
可选的，在所述形成并联电容器的方法中，所述第二介质层的厚度介于 之间。Optionally, in the method for forming a parallel capacitor, the thickness of the second dielectric layer is between between.
可选的，在所述形成并联电容器的方法中，所述第一导电层的厚度介于之间。Optionally, in the method for forming a parallel capacitor, the thickness of the first conductive layer is between between.
可选的，在所述形成并联电容器的方法中，所述第二导电层的厚度介于之间。Optionally, in the method for forming a parallel capacitor, the thickness of the second conductive layer is between between.
基于同一发明构思，本发明还提供一种并联电容器，包括：Based on the same inventive concept, the present invention also provides a parallel capacitor, including:
衬底，所述衬底上形成有第一导电层、第一介质层以及第二导电层，所述第一导电层覆盖所述衬底的部分表面，所述第一介质层覆盖所述第一导电层，所述第二导电层覆盖所述第一介质层的部分表面及所述衬底，其中，相互堆叠的所述第一导电层、第一介质层及第二导电层构成第一电容器；A substrate, on which a first conductive layer, a first dielectric layer and a second conductive layer are formed, the first conductive layer covers part of the surface of the substrate, the first dielectric layer covers the first A conductive layer, the second conductive layer covers part of the surface of the first dielectric layer and the substrate, wherein the first conductive layer, the first dielectric layer and the second conductive layer stacked on each other form a first capacitor;
第二介质层，所述第二介质层覆盖所述第二导电层；a second dielectric layer, the second dielectric layer covering the second conductive layer;
隔离层，所述隔离层覆盖所述第一介质层及所述第二介质层的部分表面；an isolation layer, the isolation layer covers part of the surface of the first dielectric layer and the second dielectric layer;
第一插塞，所述第一插塞贯穿所述隔离层以及第一介质层并与所述第一导电层电连接；a first plug, the first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected to the first conductive layer;
第二插塞，所述第二插塞贯穿所述隔离层以及第二介质层并与所述第二导电层电连接；以及，a second plug, the second plug penetrates the isolation layer and the second dielectric layer and is electrically connected to the second conductive layer; and,
互连层，所述互连层形成于所述隔离层以及第二介质层上，所述第一插塞和第二插塞分别与所述互连层电连接，且所述第一插塞和第二插塞相互绝缘，其中，相互堆叠的所述互连层、所述第二介质层及所述第二导电层构成第二电容器，所述第一电容器和所述第二电容器构成并联电容器。An interconnection layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected to the interconnection layer, and the first plug and the second plug are insulated from each other, wherein the interconnection layer, the second dielectric layer and the second conductive layer stacked on each other form a second capacitor, and the first capacitor and the second capacitor form a parallel connection capacitor.
综上，本发明提供一种形成并联电容器的方法及并联电容器，形成并联电容器的方法包括：提供一衬底，所述衬底上依次形成有第一导电层、第一介质层及第二导电层，其中，所述第一导电层、第一介质层及第二导电层构成第一电容器；在所述第二导电层上形成第二介质层；在所述第二介质层及所述第一介质层上形成隔离层，并研磨去除所述第二介质层表面的隔离层；在所述第二介质层上形成互连层，其中，所述互连层、所述第二介质层及所述第二导电层构成第二电容器，所述第一电容器和所述第二电容器构成并联电容器。在不需要增加新光罩以及新的工艺步骤的情况下，通过研磨去除所述第二介质层表面的隔离层并利用所述第二介质层作为所述第二导电层和所述互连层的中间绝缘介质以得到与所述第一电容器并联的第二电容器，所述第一电容器与第二电容器构成的并联电容器使得器件的总电容值有了显著的提高。In summary, the present invention provides a method for forming a parallel capacitor and a parallel capacitor. The method for forming a parallel capacitor includes: providing a substrate on which a first conductive layer, a first dielectric layer, and a second conductive layer are sequentially formed. layer, wherein the first conductive layer, the first dielectric layer and the second conductive layer constitute a first capacitor; a second dielectric layer is formed on the second conductive layer; a second dielectric layer is formed on the second dielectric layer and the first forming an isolation layer on a dielectric layer, and grinding and removing the isolation layer on the surface of the second dielectric layer; forming an interconnection layer on the second dielectric layer, wherein the interconnection layer, the second dielectric layer and The second conductive layer forms a second capacitor, and the first capacitor and the second capacitor form a parallel capacitor. Without adding new photomasks and new process steps, the isolation layer on the surface of the second dielectric layer is removed by grinding and the second dielectric layer is used as the connection between the second conductive layer and the interconnection layer The intermediate insulating medium is used to obtain a second capacitor connected in parallel with the first capacitor, and the parallel capacitor formed by the first capacitor and the second capacitor makes the total capacitance of the device significantly increased.
附图说明Description of drawings
图1是本发明实施例的形成并联电容器的方法流程图；1 is a flowchart of a method for forming a parallel capacitor according to an embodiment of the present invention;
图2-图6是本发明实施例形成并联电容器的各工艺步骤中的半导体结构图；2-6 are semiconductor structure diagrams in various process steps of forming a parallel capacitor according to an embodiment of the present invention;
其中，附图标记说明：Wherein, the reference numerals explain:
100-衬底，110-第一导电层，120-第一介质层，130-第二导电层，140-第二介质层，150-隔离层，160-互连层，200-第一电容器，210-第一插塞，220-第二插塞，300-第二电容器，310-沟槽。100-substrate, 110-first conductive layer, 120-first dielectric layer, 130-second conductive layer, 140-second dielectric layer, 150-isolation layer, 160-interconnection layer, 200-first capacitor, 210-first plug, 220-second plug, 300-second capacitor, 310-trench.
具体实施方式Detailed ways
以下结合附图和具体实施例对本发明提出的形成并联电容器的方法及并联电容器作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。此外，附图所展示的结构往往是实际结构的一部分。特别的，各附图需要展示的侧重点不同，有时会采用不同的比例。The method for forming a parallel capacitor and the parallel capacitor proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, each drawing needs to display different emphases, and sometimes uses different scales.
本发明提供一种形成并联电容器的方法，参考图1，图1是本发明实施例的形成并联电容器的方法流程图，所述形成并联电容器的方法包括：The present invention provides a method for forming a parallel capacitor. Referring to FIG. 1, FIG. 1 is a flowchart of a method for forming a parallel capacitor according to an embodiment of the present invention. The method for forming a parallel capacitor includes:
S10：提供一衬底；S10: providing a substrate;
S20：依次形成第一导电层、第一介质层以及第二导电层，所述第一导电层覆盖所述衬底的部分表面，所述第一介质层覆盖所述第一导电层，所述第二导电层覆盖所述第一介质层的部分表面及所述衬底，其中，相互堆叠的所述第一导电层、第一介质层及第二导电层构成第一电容器；S20: sequentially forming a first conductive layer, a first dielectric layer, and a second conductive layer, the first conductive layer covers part of the surface of the substrate, the first dielectric layer covers the first conductive layer, the The second conductive layer covers part of the surface of the first dielectric layer and the substrate, wherein the first conductive layer, the first dielectric layer and the second conductive layer stacked on each other form a first capacitor;
S30：形成第二介质层，所述第二介质层覆盖所述第二导电层；S30: forming a second dielectric layer, the second dielectric layer covering the second conductive layer;
S40：形成隔离层，所述隔离层覆盖所述第二介质层及所述第一介质层；S40: forming an isolation layer, the isolation layer covering the second dielectric layer and the first dielectric layer;
S50：执行化学机械研磨工艺，以去除位于所述第二介质层上的所述隔离层；S50: Perform a chemical mechanical polishing process to remove the isolation layer on the second dielectric layer;
S60：形成第一插塞、第二插塞和互连层，所述第一插塞贯穿所述隔离层以及第一介质层并与所述第一导电层电连接，所述第二插塞贯穿所述隔离层以及第二介质层并与所述第二导电层电连接，所述互连层形成于所述隔离层以及第二介质层上，所述第一插塞和第二插塞分别与所述互连层电连接，且所述第一插塞和第二插塞相互绝缘。S60: forming a first plug, a second plug and an interconnection layer, the first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected to the first conductive layer, the second plug penetrating through the isolation layer and the second dielectric layer and electrically connected to the second conductive layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected to the interconnection layer, and the first plug and the second plug are insulated from each other.
具体的，参考图2-图6，图2-图6是本发明实施例形成并联电容器的各工艺步骤中的半导体结构图。Specifically, refer to FIG. 2-FIG. 6, which are semiconductor structure diagrams in each process step of forming a parallel capacitor according to an embodiment of the present invention.
首先，如图2所示，提供一衬底100；依次形成第一导电层110、第一介质层120以及第二导电层130，所述第一导电层110覆盖所述衬底100的部分表面，所述第一介质层120覆盖所述第一导电层110，在靠近未被所述第一导电层110覆盖的所述衬底100侧的所述第一导电层110完全被所述第一介质层120覆盖，这样使得所述第一导电层110可以和后续形成在所述第一介质层120以及未被所述第一导电层110覆盖的所述衬底100的所述第二导电层130完全隔绝开来，所述第二导电层130覆盖所述第一介质层120的部分表面及所述衬底100(未被所述第一导电层110覆盖的所述衬底100)，其中，相互堆叠的所述第一导电层110、第一介质层120及第二导电层130构成第一电容器200。具体的，所述衬底100可以是单晶硅、多晶硅、非晶硅中的一种，所述衬底100的材料也可以是砷化镓、硅稼化合物等，所述衬底100还可以具有绝缘层上硅或硅上外延层结构，当然，所述衬底100还可以是由其它半导体材质制成，这里不再一一列举。此外，在所述衬底100中可以具有N阱或P阱等公知的结构。进一步的，所述第一导电层110、第二导电层130的材质均为多晶硅，在形成第二导电层130之后，需要通过光刻、刻蚀、原子层沉积(ALD)等工艺在所述第一导电层110表面后续需要与第一插塞的位置以及在所述第二导电层130表面后续需要与第二插塞接触的位置均形成钴化合物薄膜，从而使得材质为多晶硅的所述第一导电层110、第二导电层130在特定的位置具备导电功能，从而实现后续所述第一导电层110与第一插塞210的电连接以及所述第二导电层130与第二插塞220的电连接，部分表面覆盖有钴化合物薄膜的所述第一导电层110作为后续形成的所述第一电容器200的上极板，部分表面覆盖有钴化合物薄膜的所述第二导电层130作为后续形成的所述第一电容器200的下极板，所述第一介质层120作为所述第一电容器200的中间绝缘介质，从而构成PIP(多晶硅-绝缘层-多晶硅)结构的第一电容器200。First, as shown in FIG. 2 , a substrate 100 is provided; a first conductive layer 110 , a first dielectric layer 120 and a second conductive layer 130 are sequentially formed, and the first conductive layer 110 covers part of the surface of the substrate 100 , the first dielectric layer 120 covers the first conductive layer 110, and the first conductive layer 110 on the side of the substrate 100 that is not covered by the first conductive layer 110 is completely covered by the first The dielectric layer 120 covers, so that the first conductive layer 110 can be subsequently formed on the first dielectric layer 120 and the second conductive layer of the substrate 100 not covered by the first conductive layer 110 130 completely isolated, the second conductive layer 130 covers part of the surface of the first dielectric layer 120 and the substrate 100 (the substrate 100 not covered by the first conductive layer 110), wherein , the first conductive layer 110 , the first dielectric layer 120 and the second conductive layer 130 stacked on each other form a first capacitor 200 . Specifically, the substrate 100 can be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the material of the substrate 100 can also be gallium arsenide, silicon gallium compound, etc., and the substrate 100 can also be It has a silicon-on-insulator or epitaxial layer structure on silicon. Of course, the substrate 100 can also be made of other semiconductor materials, which will not be listed here. In addition, the substrate 100 may have a well-known structure such as an N-well or a P-well. Further, the materials of the first conductive layer 110 and the second conductive layer 130 are both polysilicon. After the second conductive layer 130 is formed, photolithography, etching, atomic layer deposition (ALD), etc. A cobalt compound film is formed on the surface of the first conductive layer 110 where it needs to be in contact with the first plug and at the position where the surface of the second conductive layer 130 needs to be in contact with the second plug, so that the material of the first plug is made of polysilicon. A conductive layer 110 and a second conductive layer 130 have a conductive function at a specific position, thereby realizing the subsequent electrical connection between the first conductive layer 110 and the first plug 210 and the connection between the second conductive layer 130 and the second plug. 220 electrical connection, part of the surface is covered with the first conductive layer 110 of the cobalt compound film as the upper plate of the first capacitor 200 formed subsequently, and part of the surface is covered with the second conductive layer 130 of the cobalt compound film As the lower plate of the first capacitor 200 formed subsequently, the first dielectric layer 120 is used as the intermediate insulating medium of the first capacitor 200, thereby forming a first capacitor with a PIP (polysilicon-insulating layer-polysilicon) structure 200.
优选的，所述第一介质层120的厚度介于之间，所述第一介质层120的材质为氧化硅，在本实施例中，通过高温氧化工艺形成所述第一介质层120；所述第一导电层110的厚度介于之间；所述第二导电层130的厚度介于之间，所述第一导电层110、所述第一介质层120及所述第二导电层130的厚度可以是本领域对应层的常用的厚度。Preferably, the thickness of the first dielectric layer 120 is between Between, the material of the first dielectric layer 120 is silicon oxide, in this embodiment, the first dielectric layer 120 is formed through a high temperature oxidation process; the thickness of the first conductive layer 110 is between between; the thickness of the second conductive layer 130 is between Between, the thicknesses of the first conductive layer 110 , the first dielectric layer 120 and the second conductive layer 130 may be common thicknesses of corresponding layers in the field.
进一步的，如图3所示，形成第二介质层140，所述第二介质层140覆盖所述第二导电层130。具体的，所述第二介质层140的厚度介于之间，所述第二介质层140的材质为氮化硅或者氮氧化硅，选材为氮化硅或者氮氧化硅使得所述第二介质层140适合作为后续形成的第二电容器300的中间绝缘介质。Further, as shown in FIG. 3 , a second dielectric layer 140 is formed, and the second dielectric layer 140 covers the second conductive layer 130 . Specifically, the thickness of the second dielectric layer 140 is between Between, the material of the second dielectric layer 140 is silicon nitride or silicon oxynitride, and the material is silicon nitride or silicon oxynitride so that the second dielectric layer 140 is suitable as the intermediate insulation of the second capacitor 300 formed subsequently. medium.
接着，如图4所示，形成隔离层150，所述隔离层150覆盖所述第二介质层140及未被第二导电层130覆盖的所述第一介质层120。所述隔离层150的材质可以是常见的硅氧化物，在本实施例中，所述隔离层150可以采用化学气相沉积工艺形成。所述隔离层150可以覆盖所述第二介质层140以及填充所述第一介质层120上的因形成所述第二导电层130及第二介质层140产生的沟槽，使得后续贯穿所述隔离层150的第一插塞及第二插塞能够与所述第二导电层130相互绝缘，从而提高了器件的良率。此外，在所述第二介质层140上形成所述隔离层150，使得后续执行化学机械研磨工艺提供了有利的条件，研磨所述隔离层150的平整的表面可以减小所述隔离层150下面的各层之间研磨产生的应力，避免各层的形貌被损坏的情况。Next, as shown in FIG. 4 , an isolation layer 150 is formed, and the isolation layer 150 covers the second dielectric layer 140 and the first dielectric layer 120 not covered by the second conductive layer 130 . The material of the isolation layer 150 can be common silicon oxide, and in this embodiment, the isolation layer 150 can be formed by chemical vapor deposition process. The isolation layer 150 can cover the second dielectric layer 140 and fill the grooves on the first dielectric layer 120 due to the formation of the second conductive layer 130 and the second dielectric layer 140, so that the subsequent penetration through the The first plug and the second plug of the isolation layer 150 can be insulated from the second conductive layer 130, thereby improving the yield of the device. In addition, the isolation layer 150 is formed on the second dielectric layer 140, so that the subsequent chemical mechanical polishing process provides favorable conditions. Grinding the flat surface of the isolation layer 150 can reduce the thickness of the isolation layer 150. The stress generated by the grinding between the layers can avoid the damage of the morphology of each layer.
然后，如图5所示，执行化学机械研磨工艺，以去除位于所述第二介质层140上的所述隔离层150。具体的，通过化学机械研磨工艺去除位于所述第二介质层140上的所述隔离层150，保留所述第一介质层120上的因形成所述第二导电层130及第二介质层140而产生的沟槽中的所述隔离层150。优选的，执行化学机械研磨工艺时，也可以去除位于所述第二介质层140上的所述隔离层150及部分厚度的所述第二介质层，化学机械研磨去除部分厚度的所述第二介质层的厚度可以为研磨去除所述隔离层150时也相应地去除部分厚度的所述第二介质层，可以使得研磨后剩余厚度的所述第二介质层上的所述隔离层150被清除干净，避免了所述第二介质层140表面仍有所述隔离层150的残留的情况。Then, as shown in FIG. 5 , a chemical mechanical polishing process is performed to remove the isolation layer 150 on the second dielectric layer 140 . Specifically, the isolation layer 150 located on the second dielectric layer 140 is removed by a chemical mechanical polishing process, and the second conductive layer 130 and the second dielectric layer 140 formed on the first dielectric layer 120 are retained. The isolation layer 150 in the trench is generated. Preferably, when the chemical mechanical polishing process is performed, the isolation layer 150 and a partial thickness of the second dielectric layer located on the second dielectric layer 140 can also be removed, and the chemical mechanical polishing removes a partial thickness of the second dielectric layer. The thickness of the dielectric layer can be When grinding and removing the isolation layer 150, the second dielectric layer with a partial thickness is correspondingly removed, so that the isolation layer 150 on the remaining thickness of the second dielectric layer after grinding can be cleaned up, avoiding the The isolation layer 150 still remains on the surface of the second dielectric layer 140 .
进一步的，如图6所示，形成第一插塞210、第二插塞220和互连层160，所述第一插塞210贯穿所述隔离层150以及第一介质层120并与所述第一导电层110电连接，所述第二插塞220贯穿所述隔离层150以及第二介质层140并与所述第二导电层130电连接，所述互连层160形成于所述隔离层150以及第二介质层140上，所述第一插塞210和第二插塞220分别与所述互连层160电连接，且所述第一插塞210和第二插塞220相互绝缘，从图6中可以看出，所述互连层160中形成有沟槽310，所述沟槽310可以使得所述第一插塞210与所述第二插塞220之间断开电性连接。其中，堆叠的所述互连层160、所述第二介质层140及所述第二导电层130构成第二电容器300，所述第一电容器200和所述第二电容器300构成并联电容器，部分表面覆盖有钴化合物薄膜的所述第二导电层130作为所述第二电容器300的上极板，所述第二介质层140作为所述第二电容器300的中间绝缘介质，所述互连层160作为所述第二电容器300的下极板，从而构成PIM(多晶硅-绝缘层-金属)结构的第二电容器，从而构成PPM(多晶硅-多晶硅-金属)结构的并联电容器，所述并联电容器的电容值大于或者等于3.3fF/μm2，目前的PIP结构的电容器的电容值最大只能做到1.3fF/μm2左右，所以本发明形成的并联电容器使得器件的总电容值有了显著的提高。Further, as shown in FIG. 6 , a first plug 210, a second plug 220 and an interconnection layer 160 are formed, the first plug 210 penetrates through the isolation layer 150 and the first dielectric layer 120 and is connected to the The first conductive layer 110 is electrically connected, the second plug 220 penetrates the isolation layer 150 and the second dielectric layer 140 and is electrically connected to the second conductive layer 130, and the interconnection layer 160 is formed on the isolation layer 150. layer 150 and the second dielectric layer 140, the first plug 210 and the second plug 220 are electrically connected to the interconnection layer 160 respectively, and the first plug 210 and the second plug 220 are insulated from each other , it can be seen from FIG. 6 that a groove 310 is formed in the interconnection layer 160, and the groove 310 can disconnect the electrical connection between the first plug 210 and the second plug 220. . Wherein, the stacked interconnection layer 160, the second dielectric layer 140 and the second conductive layer 130 form a second capacitor 300, and the first capacitor 200 and the second capacitor 300 form a parallel capacitor, partly The second conductive layer 130 whose surface is covered with a cobalt compound thin film is used as the upper plate of the second capacitor 300, the second dielectric layer 140 is used as an intermediate insulating medium of the second capacitor 300, and the interconnection layer 160 is used as the lower plate of the second capacitor 300 to form a second capacitor with a PIM (polysilicon-insulator-metal) structure, thereby forming a parallel capacitor with a PPM (polysilicon-polysilicon-metal) structure. The capacitance value is greater than or equal to 3.3fF/μm 2 , and the maximum capacitance value of the current PIP structure capacitor can only reach about 1.3fF/μm 2 , so the parallel capacitor formed by the present invention has significantly improved the total capacitance value of the device .
在形成所述互连层160之前，在不用新增加光罩的情况下，通过化学机械研磨工艺去除所述第二介质层140上的隔离层150并利用所述第二介质层140作为所述第二导电层130和所述互连层160的中间绝缘介质以得到与所述第一电容器200并联的第二电容器300，形成的并联电容器使得器件的总电容值有了显著的提高，同时也减小了所述互连层160与所述第一导电层110及所述第二导电层130的垂直距离，从而减小了电路的体积，符合尺寸较小的半导体器件的要求。Before forming the interconnection layer 160, the isolation layer 150 on the second dielectric layer 140 is removed by a chemical mechanical polishing process and the second dielectric layer 140 is used as the The second conductive layer 130 and the intermediate insulating medium of the interconnection layer 160 are used to obtain the second capacitor 300 connected in parallel with the first capacitor 200. The parallel capacitor formed makes the total capacitance value of the device significantly improved, and at the same time The vertical distance between the interconnection layer 160 and the first conductive layer 110 and the second conductive layer 130 is reduced, thereby reducing the volume of the circuit and meeting the requirements of smaller semiconductor devices.
基于同一发明构思，本发明还提供一种并联电容器，如图6所示，包括：Based on the same inventive concept, the present invention also provides a parallel capacitor, as shown in Figure 6, including:
衬底100，所述衬底100上形成有第一导电层110、第一介质层120以及第二导电层130，所述第一导电层110覆盖所述衬底100的部分表面，所述第一介质层120覆盖所述第一导电层110，所述第二导电层130覆盖所述第一介质层120的部分表面及所述衬底100，其中，相互堆叠的所述第一导电层110、第一介质层120及第二导电层130构成第一电容器200；A substrate 100, on which a first conductive layer 110, a first dielectric layer 120, and a second conductive layer 130 are formed, the first conductive layer 110 covers part of the surface of the substrate 100, and the first A dielectric layer 120 covers the first conductive layer 110, and the second conductive layer 130 covers part of the surface of the first dielectric layer 120 and the substrate 100, wherein the first conductive layers 110 stacked on each other 1. The first dielectric layer 120 and the second conductive layer 130 constitute the first capacitor 200;
第二介质层140，所述第二介质层140覆盖所述第二导电层130；A second dielectric layer 140, the second dielectric layer 140 covering the second conductive layer 130;
隔离层150，所述隔离层150覆盖所述第一介质层120及所述第二介质层140的部分表面；an isolation layer 150, the isolation layer 150 covers part of the surface of the first dielectric layer 120 and the second dielectric layer 140;
第一插塞210，所述第一插塞210贯穿所述隔离层150以及第一介质层120并与所述第一导电层110电连接；A first plug 210, the first plug 210 penetrates through the isolation layer 150 and the first dielectric layer 120 and is electrically connected to the first conductive layer 110;
第二插塞220，所述第二插塞220贯穿所述隔离层150以及第二介质层140并与所述第二导电层130电连接；以及，A second plug 220 , the second plug 220 penetrates through the isolation layer 150 and the second dielectric layer 140 and is electrically connected to the second conductive layer 130 ; and,
互连层160，所述互连层160形成于所述隔离层150以及第二介质层140上，所述第一插塞210和第二插塞220分别与所述互连层160电连接，且所述第一插塞210和第二插塞220相互绝缘，其中，相互堆叠的所述互连层160、所述第二介质层140及所述第二导电层130构成第二电容器300，所述第一电容器200和所述第二电容器300构成并联电容器，利用常规工艺中的所述第一导电层110、第一介质层120及第二导电层130构成第一电容器200，以及利用常规工艺中的所述第二介质层140作为所述互连层160及所述第二导电层130的中间绝缘介质以得到与所述第一电容器200并联的第二电容器300，减小了所述互连层160与所述第一导电层110及所述第二导电层130的垂直距离，从而减小了电路的体积，符合尺寸较小的半导体器件的要求，同时也提高了器件的总电容值。An interconnection layer 160, the interconnection layer 160 is formed on the isolation layer 150 and the second dielectric layer 140, the first plug 210 and the second plug 220 are respectively electrically connected to the interconnection layer 160, And the first plug 210 and the second plug 220 are insulated from each other, wherein the interconnection layer 160, the second dielectric layer 140 and the second conductive layer 130 stacked on each other form a second capacitor 300, The first capacitor 200 and the second capacitor 300 form a parallel capacitor, and the first capacitor 200 is formed by using the first conductive layer 110, the first dielectric layer 120 and the second conductive layer 130 in a conventional process, and using a conventional The second dielectric layer 140 in the process is used as the intermediate insulating medium of the interconnection layer 160 and the second conductive layer 130 to obtain the second capacitor 300 connected in parallel with the first capacitor 200, which reduces the The vertical distance between the interconnection layer 160 and the first conductive layer 110 and the second conductive layer 130, thereby reducing the volume of the circuit, meeting the requirements of smaller semiconductor devices, and also improving the total capacitance of the device value.
综上，本发明提供一种形成并联电容器的方法及并联电容器，形成并联电容器的方法包括：提供一衬底，所述衬底上依次形成有第一导电层、第一介质层及第二导电层，其中，所述第一导电层、第一介质层及第二导电层构成第一电容器(PIP结构)；在所述第二导电层上形成第二介质层及隔离层，并研磨去除所述第二介质层表面的隔离层；在所述第二介质层上形成互连层，其中，所述互连层、所述第二介质层及所述第二导电层构成第二电容器(PIM结构)，所述第一电容器和所述电容器构成并联电容器(PPM结构)。在不用额外再进行光刻等其他工艺步骤的情况下，通过研磨去除所述第二介质层表面的隔离层并利用所述第二介质层作为所述第二导电层和所述互连层的中间绝缘介质以得到与所述第一电容器并联的第二电容器，形成的并联电容器使得器件的总电容值有了显著的提高；同时也减小了并联电容器的在高度上的尺寸，从而减小了电路的体积，符合尺寸较小的半导体器件的要求。In summary, the present invention provides a method for forming a parallel capacitor and a parallel capacitor. The method for forming a parallel capacitor includes: providing a substrate on which a first conductive layer, a first dielectric layer, and a second conductive layer are sequentially formed. layer, wherein, the first conductive layer, the first dielectric layer and the second conductive layer constitute a first capacitor (PIP structure); a second dielectric layer and an isolation layer are formed on the second conductive layer, and all of them are removed by grinding An isolation layer on the surface of the second dielectric layer; an interconnection layer is formed on the second dielectric layer, wherein the interconnection layer, the second dielectric layer and the second conductive layer constitute a second capacitor (PIM structure), the first capacitor and the capacitor form a parallel capacitor (PPM structure). In the absence of additional process steps such as photolithography, the isolation layer on the surface of the second dielectric layer is removed by grinding and the second dielectric layer is used as the second conductive layer and the interconnection layer. An intermediate insulating medium is used to obtain a second capacitor connected in parallel with the first capacitor, and the formed parallel capacitor makes the total capacitance value of the device significantly improved; meanwhile, the size in height of the parallel capacitor is also reduced, thereby reducing The size of the circuit is reduced, which meets the requirements of smaller semiconductor devices.
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.
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Cited By (3)
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| CN111048662A (en) * | 2019-12-26 | 2020-04-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of parallel PPS capacitor and parallel PPS capacitor |
| CN113451313A (en) * | 2021-06-28 | 2021-09-28 | 福建省晋华集成电路有限公司 | Design method and device of semiconductor memory device, storage medium and preparation method |
| CN114335342A (en) * | 2021-12-16 | 2022-04-12 | 上海华虹宏力半导体制造有限公司 | A kind of PPM capacitor and preparation method thereof |
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Application publication date: 20191206 |