CN111048662A - Manufacturing method of parallel PPS capacitor and parallel PPS capacitor - Google Patents
Manufacturing method of parallel PPS capacitor and parallel PPS capacitor Download PDFInfo
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Abstract
本发明提供了一种并联PPS电容器的制作方法及并联PPS电容器，所述并联PPS电容器的制作方法包括：提供一衬底，所述衬底上形成有第一多晶硅层、第一介质层、第二多晶硅层、第二介质层及第三多晶硅层；利用第一光罩形成第一沟槽和第二沟槽；形成隔离层；利用第二光罩形成第一插塞、第二插塞及第三插塞，本发明在不额外增加光刻、刻蚀等多道工艺步骤的情况下，新增加一由所述第一多晶硅层、第一介质层及第二多晶硅层构成的第一PPS电容器，极大效率地利用了已有的所述第一多晶硅层、第一介质层，使得器件的总电容值有了显著的提高。
The invention provides a manufacturing method of a parallel PPS capacitor and a parallel PPS capacitor. The manufacturing method of the parallel PPS capacitor includes: providing a substrate on which a first polysilicon layer and a first dielectric layer are formed , the second polysilicon layer, the second dielectric layer and the third polysilicon layer; use the first mask to form the first trench and the second trench; form the isolation layer; use the second mask to form the first plug , the second plug and the third plug, the present invention adds a new layer consisting of the first polysilicon layer, the first dielectric layer and the third The first PPS capacitor composed of two polysilicon layers utilizes the existing first polysilicon layer and the first dielectric layer with great efficiency, so that the total capacitance value of the device is significantly improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a parallel PPS capacitor and the parallel PPS capacitor.
Background
A PPS (polypropylene film) capacitor, which is a device widely used for frequency modulation and preventing emission of noise from analog circuits, has a lower electrode and an upper electrode formed of polysilicon (generally, a material for making a gate electrode of a logic circuit in a semiconductor device).
However, in the semiconductor device at present, the PPS capacitor generally has a problem of small capacitance value, thereby causing a defect of poor filtering effect of the integrated circuit. At present, in order to improve the capacitance value of the PPS capacitor, a common method is to use a new photomask to form a new plug on a PPS capacitor in a logic region, so as to form another PPS capacitor connected in parallel with the PPS capacitor, but multiple process steps such as photolithography and etching are additionally added, which inevitably increases the process time and reduces the working efficiency, and simultaneously does not meet the requirement of a semiconductor device with a smaller size, so that a new manufacturing method of the PPS capacitor is urgently needed to solve the problem of a smaller capacitance value of the PPS capacitor without adding additional process steps as much as possible.
Disclosure of Invention
The invention aims to provide a method for manufacturing a parallel PPS capacitor and the parallel PPS capacitor, so as to solve the problem of increasing the capacitance value of the PPS capacitor under the condition of not increasing additional process steps.
In order to solve the technical problem, the invention provides a method for manufacturing a parallel PPS capacitor, which comprises the following steps:
providing a substrate, wherein a first polycrystalline silicon layer, a first dielectric layer, a second polycrystalline silicon layer, a second dielectric layer and a third polycrystalline silicon layer are sequentially formed on the substrate;
performing an etching process on the third polysilicon layer and the second dielectric layer by using a first photomask to form a first trench, and performing an etching process on the third polysilicon layer, the second dielectric layer, the second polysilicon layer and the first dielectric layer to form a second trench;
forming an isolation layer filling the first trench and the second trench and covering the third polysilicon layer;
performing an etching process on the isolation layer by using a second photomask to form a first plug, a second plug and a third plug, wherein the first plug penetrates through the isolation layer and is electrically connected with the first polysilicon layer; the second plug penetrates through the isolation layer and is electrically connected with the second polycrystalline silicon layer; the third plug penetrates through the isolation layer and is electrically connected with the third polysilicon layer;
under the condition of not adding an additional photomask, the first polycrystalline silicon layer, the first dielectric layer and the second polycrystalline silicon layer which are sequentially stacked form a first PPS capacitor; the second polycrystalline silicon layer, the second dielectric layer and the third polycrystalline silicon layer which are stacked in sequence form a second PPS capacitor, and the first PPS capacitor and the second PPS capacitor form a parallel PPS capacitor.
Optionally, in the method for manufacturing the parallel PPS capacitor, after forming the first plug, the second plug, and the third plug, the method for manufacturing the parallel PPS capacitor further includes:
and forming an interconnection layer, wherein the interconnection layer is formed on the isolation layer, the first plug, the second plug and the third plug are respectively electrically connected with the interconnection layer, and the first plug, the second plug and the third plug are mutually insulated.
Optionally, in the method for manufacturing the parallel PPS capacitor, the first dielectric layer is made of silicon oxide.
Optionally, in the method for manufacturing the parallel PPS capacitor, the first dielectric layer is formed by a chemical vapor deposition process.
Optionally, in the method for manufacturing the parallel PPS capacitor, the second dielectric layer is made of silicon oxide.
Optionally, in the method for manufacturing the parallel PPS capacitor, the second dielectric layer is formed by a high-temperature oxidation process.
Optionally, in the method for manufacturing the parallel PPS capacitor, a silicon nitride layer is further formed between the isolation layer and the third polysilicon layer, the silicon nitride layer covers the third polysilicon layer, and the third plug penetrates through the isolation layer and the silicon nitride layer and is electrically connected to the third polysilicon layer.
Optionally, in the method for manufacturing the parallel PPS capacitor, the thickness of the silicon nitride layer is
Optionally, in the method for manufacturing the parallel PPS capacitor, the thickness of the first polysilicon layer is
The thickness of the first dielectric layer is
The second polysilicon layer has a thickness of
The thickness of the second dielectric layer is
The third polysilicon layer has a thickness of
Based on the same inventive concept, the invention also provides a parallel PPS capacitor, comprising:
the polysilicon gate structure comprises a substrate, wherein a first polysilicon layer, a first dielectric layer, a second polysilicon layer, a second dielectric layer and a third polysilicon layer which are stacked are formed on the substrate, and a first groove is formed in the third polysilicon layer and the second dielectric layer; a second groove is formed in the third polycrystalline silicon layer, the second dielectric layer, the second polycrystalline silicon layer and the first dielectric layer;
an isolation layer filling the first and second trenches and covering the third polysilicon layer;
the first plug penetrates through the isolation layer and is electrically connected with the first polysilicon layer; the second plug penetrates through the isolation layer and is electrically connected with the second polycrystalline silicon layer; the third plug penetrates through the isolation layer and is electrically connected with the third polysilicon layer;
the first PPS capacitor is formed by the first polysilicon layer, the first dielectric layer and the second polysilicon layer which are sequentially stacked; the second polycrystalline silicon layer, the second dielectric layer and the third polycrystalline silicon layer which are stacked in sequence form a second PPS capacitor, and the first PPS capacitor and the second PPS capacitor form a parallel PPS capacitor.
In the method for manufacturing the parallel PPS capacitor and the parallel PPS capacitor provided by the invention, the method for manufacturing the parallel PPS capacitor comprises the following steps: providing a substrate, wherein a first polycrystalline silicon layer, a first dielectric layer, a second polycrystalline silicon layer, a second dielectric layer and a third polycrystalline silicon layer are formed on the substrate; forming a first groove and a second groove by using a first photomask; forming an isolation layer; the method comprises the steps of forming a first plug, a second plug and a third plug by using a second photomask, wherein under the condition that no additional photomask is added, only two photomasks are used, so that a first PPS capacitor is formed by the first polycrystalline silicon layer, the first dielectric layer and the second polycrystalline silicon layer which are sequentially stacked, a second PPS capacitor is formed by the second polycrystalline silicon layer, the second dielectric layer and the third polycrystalline silicon layer which are sequentially stacked, and the first PPS capacitor and the second PPS capacitor form a parallel PPS capacitor.
Drawings
FIG. 1 is a flow chart of a method for fabricating a parallel PPS capacitor according to an embodiment of the invention;
FIGS. 2-6 are schematic views of semiconductor structures at various processing steps for fabricating a parallel PPS capacitor according to embodiments of the invention;
wherein the reference numbers indicate:
10-a first trench, 20-a second trench, 100-a substrate, 110-a first polysilicon layer, 120-a first dielectric layer, 130-a second polysilicon layer, 140-a second dielectric layer, 150-a third polysilicon layer, 160-an isolation layer, 161-a silicon nitride layer, 171-a first plug, 172-a second plug, 173-a third plug, 180-an interconnect layer, 190-a third trench, 200-a first PPS capacitor, 300-a second PPS capacitor.
Detailed Description
The method for manufacturing the parallel PPS capacitor and the parallel PPS capacitor according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
The invention provides a method for manufacturing a parallel PPS capacitor, which refers to FIG. 1, wherein FIG. 1 is a flow chart of a method for manufacturing the parallel PPS capacitor according to an embodiment of the invention, and the method for manufacturing the parallel PPS capacitor comprises the following steps:
s10: providing a substrate, wherein a first polycrystalline silicon layer, a first dielectric layer, a second polycrystalline silicon layer, a second dielectric layer and a third polycrystalline silicon layer which are stacked in sequence are formed on the substrate;
s20: performing an etching process on the third polysilicon layer and the second dielectric layer by using a first photomask to form a first trench, and performing an etching process on the third polysilicon layer, the second dielectric layer, the second polysilicon layer and the first dielectric layer to form a second trench;
s30: forming an isolation layer filling the first trench and the second trench and covering the third polysilicon layer;
s40: performing an etching process on the isolation layer by using a second photomask to form a first plug, a second plug and a third plug, wherein the first plug penetrates through the isolation layer and is electrically connected with the first polysilicon layer; the second plug penetrates through the isolation layer and is electrically connected with the second polycrystalline silicon layer; the third plug penetrates through the isolation layer and is electrically connected with the third polysilicon layer.
The first PPS capacitor is formed by the first polysilicon layer, the first dielectric layer and the second polysilicon layer which are sequentially stacked under the condition that only the first photomask and the second photomask are used and no additional photomask is added; the second polysilicon layer, the second dielectric layer and the third polysilicon layer which are sequentially stacked form a second PPS capacitor, the first PPS capacitor and the second PPS capacitor form a parallel PPS capacitor, and the structure of the parallel PPS capacitor is provided based on a special product of 0.12um flash of HHG.
Specifically, referring to fig. 2-6, fig. 2-6 are schematic views of semiconductor structures in the steps of fabricating the parallel PPS capacitor according to the embodiment of the invention.
First, as shown in fig. 2, a substrate 100 is provided, on which a first polysilicon layer 110, a first dielectric layer 120, a second polysilicon layer 130, a second dielectric layer 140 and a third polysilicon layer 150 are formed in sequence. Specifically, the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, the material of the substrate 100 may also be gallium arsenide, silicon gallium arsenide compound, and the like, the substrate 100 may also have a silicon-on-insulator or silicon-on-silicon epitaxial layer structure, and of course, the substrate 100 may also be made of other semiconductor materials, which are not listed here; the substrate 100 may have a known structure such as an N-well or a P-well. Further, the thickness of the first polysilicon layer 110 is
The thickness of the first dielectric layer 120 is
The first dielectric layer 120 is made of silicon oxide and is formed by chemical vapor depositionForming the first dielectric layer 120; the second polysilicon layer 130 has a thickness of
The thickness of the second dielectric layer 140 is
The second dielectric layer 140 is made of silicon oxide, and the second dielectric layer 140 is formed through a high-temperature oxidation process; the third polysilicon layer 150 has a thickness of
In this embodiment, taking a semiconductor flash memory device as an example, the first polysilicon layer 110 may be regarded as source line polysilicon (SPL) in the flash memory device, the first dielectric layer 120 may be regarded as a tunnel oxide layer in the flash memory device, the second polysilicon layer 130 may be regarded as Memory Polysilicon (MPL) in the flash memory device, the second dielectric layer 140 may be regarded as a high temperature oxide layer in the flash memory device, the third polysilicon layer 150 may be regarded as Gate Polysilicon (GPL) in the flash memory device, floating gate polysilicon and control gate polysilicon that are sequentially stacked are usually formed between the first polysilicon layer 110 and the substrate, and an ONO dielectric layer is usually formed between the floating gate polysilicon and the control gate polysilicon.
Then, as shown in fig. 3, an etching process is performed on the third polysilicon layer 150 and the second dielectric layer 140 by using a first mask to form a first trench 10, and an etching process is performed on the third polysilicon layer 150, the second dielectric layer 140, the second polysilicon layer 130 and the first dielectric layer 120 to form a second trench 20. Specifically, the step of forming the first trench 10 and the second trench 20 includes: forming a first mask layer, and performing a photoetching process on the first mask layer by using a first photomask to obtain a patterned first mask layer; performing an etching process on the second polysilicon layer and the first dielectric layer using the patterned first mask layer to form a first trench 10 and performing an etching process on the third polysilicon layer 150, the second dielectric layer 140, the second polysilicon layer 130, and the first dielectric layer 120 using the patterned first mask layer to form a second trench 20.
Next, as shown in fig. 4, an isolation layer 160 is formed, wherein the isolation layer 160 fills the first trench 10 and the second trench 20 and covers the third polysilicon layer 150. Specifically, the material of the isolation layer 160 includes but is not limited to silicon oxide, a silicon nitride layer 161 may be further formed between the isolation layer 160 and the third polysilicon layer 150, the silicon nitride layer 161 covers the third polysilicon layer 150, and the thickness of the silicon nitride layer 161 is
Further, after the isolation layer 160 is formed, a cobalt compound thin film is formed on the surface of the first polysilicon layer 110 at a position where the first plug 171 needs to be subsequently contacted with the surface of the second polysilicon layer 130, at a position where the second plug 172 needs to be subsequently contacted with the surface of the third polysilicon layer 150, and at a position where the third plug 173 needs to be subsequently contacted with the surface of the third polysilicon layer 150, so that the first polysilicon layer 110, the second polysilicon layer 130, and the third polysilicon layer 150 have a conductive function at specific positions, and thus, the first polysilicon layer 110 and the first plug 171, the second polysilicon layer 130 and the second plug 172, and the third polysilicon layer 150 and the third plug 173 are electrically connected.
Finally, as shown in fig. 5, an etching process is performed on the isolation layer 160 by using a second mask to form a first plug 171, a second plug 172 and a third plug 173, wherein the first plug 171 penetrates through the isolation layer 160 and is electrically connected to the first polysilicon layer 110; the second plug 172 penetrates the isolation layer 160 and is electrically connected to the second polysilicon layer 130; the third plug 173 penetrates the isolation layer 160 and the silicon nitride layer 161 and is electrically connected to the third polysilicon layer 150. Specifically, the steps of forming the first plug 171, the second plug 172, and the third plug 173 include: forming a second mask layer on the isolation layer 160, and performing a photolithography process on the second mask layer by using a second photomask to obtain a patterned second mask layer; an etching process is performed on the isolation layer 160 using the patterned second mask layer to form the first plug 171, the second plug 172, and the third plug 173. In the present embodiment, the material of the first plug 171, the second plug 172 and the third plug 173 includes, but is not limited to, tungsten, copper and other metals.
Further, as shown in fig. 6, after the first plug 171, the second plug 172, and the third plug 173 are formed, the method for manufacturing the parallel PPS capacitor further includes: an interconnection layer 180 is formed, the interconnection layer 180 is formed on the isolation layer 160, the first plug 171, the second plug 172 and the third plug 173 are electrically connected to the interconnection layer 160, respectively, as can be seen from fig. 6, a third trench 190 is formed in the interconnection layer 180, and the third trench 190 can disconnect the electrical connection among the first plug 171, the second plug 172 and the third plug 173, so that the first plug 171, the second plug 172 and the third plug 173 are insulated from each other.
In the invention, only the first photomask and the second photomask are used, and the first polysilicon layer 110, the first dielectric layer 120 and the second polysilicon layer 130 which are sequentially stacked form the first PPS capacitor 200 without adding additional photomasks; the second polysilicon layer 130, the second dielectric layer 140 and the third polysilicon layer 150 stacked in sequence form a second PPS capacitor 300, and the first PPS capacitor 200 and the second PPS capacitor 300 form a parallel PPS capacitor. On one hand, the first polysilicon layer 110 with a part of the surface covered with the cobalt compound film is used as an upper plate of the first PPS capacitor 200 formed later, the second polysilicon layer 130 with a part of the surface covered with the cobalt compound film is used as a lower plate of the first PPS capacitor 200 formed later, and the first dielectric layer 120 is used as a middle insulating medium of the first PPS capacitor 200; on the other hand, the second polysilicon layer 130 with a part of the surface covered with the cobalt compound film also serves as an upper plate of the second PPS capacitor 300 to be formed subsequently, the third polysilicon layer 150 with a part of the surface covered with the cobalt compound film serves as a lower plate of the second PPS capacitor 300 to be formed subsequently, and the second dielectric layer 140 serves as a middle insulating medium of the second PPS capacitor 300. Under the condition of not additionally adding a plurality of process steps such as photoetching, etching and the like, the first PPS capacitor 200 formed by the first polysilicon layer 110, the first dielectric layer 120 and the second polysilicon layer 130 is added by utilizing the existing first polysilicon layer 110 and the first dielectric layer 120 in the flash memory device, so that the total capacitance value of the device is obviously improved, the volume of a circuit in the device is reduced in a phase-changing manner, and the requirements of a semiconductor device with a smaller size are met; meanwhile, raw materials for manufacturing the capacitor are saved, and the manufacturing efficiency of the parallel PPS capacitor is improved.
Based on the same inventive concept, the present invention further provides a parallel PPS capacitor, referring to fig. 6, the parallel PPS capacitor comprising:
a substrate 100, wherein a first polysilicon layer 110, a first dielectric layer 120, a second polysilicon layer 130, a second dielectric layer 140 and a third polysilicon layer 150 are stacked on the substrate 100, and a first trench 10 is formed in the third polysilicon layer 150 and the second dielectric layer 140; a second trench 20 is formed in the third polysilicon layer 150, the second dielectric layer 140, the second polysilicon layer 130 and the first dielectric layer 120;
an isolation layer 160 filling the first and second trenches 10 and 20 and covering the third polysilicon layer 150; and the number of the first and second groups,
a first plug 171, a second plug 172 and a third plug 173, wherein the first plug 171 penetrates the isolation layer 160 and is electrically connected to the first polysilicon layer 110; the second plug 172 penetrates through the isolation layer 160 and is electrically connected to the second polysilicon layer 140; the third plug 173 penetrates the isolation layer 160 and is electrically connected to the third polysilicon layer 150;
the first PPS capacitor 200 is formed by the first polysilicon layer 110, the first dielectric layer 120 and the second polysilicon layer 130 which are stacked in sequence; the second polysilicon layer 130, the second dielectric layer 140 and the third polysilicon layer 150 stacked in sequence form a second PPS capacitor 300, and the first PPS capacitor 200 and the second PPS capacitor 300 form a parallel PPS capacitor. The first polysilicon layer 110, the first dielectric layer 120 and the second polysilicon layer 130 in the conventional process are used for forming the first PPS capacitor 200, and are connected in parallel with the second PPS capacitor 300 in the conventional process to obtain the parallel PPS capacitor, so that the situation that the PPS capacitor is added by adding multiple process steps such as photoetching and etching is avoided, the improvement of the total capacitance value of a device is realized by reasonably using the existing first polysilicon layer 110 and the existing first dielectric layer 120, the manufacturing efficiency of the parallel PPS capacitor is improved, and meanwhile, the finally obtained semiconductor device meets the requirement of the semiconductor device with smaller size.
In summary, in the method for manufacturing the parallel PPS capacitor and the parallel PPS capacitor provided by the invention, the method for manufacturing the parallel PPS capacitor includes: providing a substrate, wherein a first polycrystalline silicon layer, a first dielectric layer, a second polycrystalline silicon layer, a second dielectric layer and a third polycrystalline silicon layer are formed on the substrate; forming a first groove and a second groove by using a first photomask; forming an isolation layer; the method comprises the steps of forming a first plug, a second plug and a third plug by using a second photomask, wherein under the condition that no additional photomask is added, only two photomasks are used, so that a first PPS capacitor is formed by the first polycrystalline silicon layer, the first dielectric layer and the second polycrystalline silicon layer which are sequentially stacked, a second PPS capacitor is formed by the second polycrystalline silicon layer, the second dielectric layer and the third polycrystalline silicon layer which are sequentially stacked, and the first PPS capacitor and the second PPS capacitor form a parallel PPS capacitor.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
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| CN114335342A (en) * | 2021-12-16 | 2022-04-12 | 上海华虹宏力半导体制造有限公司 | A kind of PPM capacitor and preparation method thereof |
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