CN113157079B - Method and device for controlling processor and processor thereof - Google Patents

Abstract

The present disclosure discloses a method for controlling a processor, an integrated circuit device and a corresponding processor. Wherein the processor may be included in a processing device of a combined processing device, which may also include a universal interconnect interface and other processing devices. The processing device interacts with other processing devices to jointly complete the calculation operation designated by the user. The combined processing means may further comprise storage means connected to the processing means and the other processing means, respectively, for storing data of the processing means and the other processing means. The scheme of the disclosure can evaluate the power consumption of the processing device and adjust the processing circuit with high power consumption expenditure, thereby improving the performance of the whole system.

Description

Method and device for controlling a processor and processor thereof

Technical Field

The present disclosure generally relates to the field of processors. More specifically, the present disclosure relates to a method for controlling a processor, an integrated circuit device and a corresponding processor thereof.

Background technique

Currently, a board containing a computing device may have multiple chips, and each chip may contain several computing core clusters. When controlling the power consumption of the board, the actual power consumption value of the board is usually collected and observed, and the clock frequency of the board is not reduced until the power consumption value exceeds the set threshold. This passive frequency modulation method will cause the system to respond too slowly to the requirement to reduce the power consumption of the entire board. In addition, although the power consumption of the entire board can be reduced by reducing the clock frequency of the board, this will also reduce the frequency of each computing core cluster in the board, especially the computing core cluster with low power consumption overhead. Furthermore, such a unified way of reducing power consumption of the entire board will also cause the performance of the corresponding scalar computing circuits, vector computing circuits, and input-output circuits in the same computing core cluster to decrease, which is not conducive to the virtualization of system equipment.

Summary of the invention

In order to at least solve the problems described in the above background technology section, the present disclosure provides the following technical solutions in one or more aspects.

In one aspect, the present disclosure proposes a processor comprising: a plurality of processing circuits, wherein each processing circuit is configured to perform computing operations; a plurality of timing control circuits, wherein each timing control circuit is connected to a corresponding one or more of the plurality of processing circuits and is configured to adjust the clock signal of the connected processing circuit; and a control circuit, which is configured to manipulate part or all of the plurality of timing control circuits according to instructions so as to instruct the manipulated timing control circuit to make the adjustment to the clock signal of the processing circuit connected thereto.

In another aspect, the present disclosure also discloses an integrated circuit device, comprising the aforementioned processor.

In yet another aspect, the present disclosure further discloses a method for controlling a processor, wherein the processor comprises a plurality of processing circuits, a plurality of timing control circuits and a control circuit, wherein the processing circuit is configured to perform computing operations, and each timing control circuit is connected to one or more corresponding processing circuits, the method comprising: instructing the control circuit to manipulate some or all of the plurality of timing control circuits according to instructions; and in response to the manipulation of the control circuit, instructing the manipulated timing control circuit to adjust the clock signal of the processing circuit connected thereto.

By utilizing the method for controlling the processor, the integrated circuit device, and the processor thereof proposed in the present disclosure, the power consumption of the entire board can be optimized and adjusted through active frequency modulation, which can not only avoid excessive power consumption of the entire board, but also will not affect the performance of other computing core clusters with low power consumption overhead, as well as the scalar and vector computing circuits and input and output circuits within the same computing core cluster.

BRIEF DESCRIPTION OF THE DRAWINGS

By combining the accompanying drawings, the above features of the present invention can be better understood, and its many purposes, features and advantages are obvious to those skilled in the art. The drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

FIG1 is a schematic diagram showing the structure of a processor according to an embodiment of the present disclosure;

FIG2 is a flow chart showing a method for controlling a processor according to an embodiment of the present disclosure;

FIG3 is a detailed flow chart showing a method for controlling a processor according to an embodiment of the present disclosure;

FIG4 is a timing diagram illustrating manipulation of a clock signal according to an embodiment of the present disclosure;

FIG5 is a simplified flow chart illustrating a method of controlling a processor according to an embodiment of the present disclosure;

FIG6 is a detailed flow chart showing a method for controlling a processor according to an embodiment of the present disclosure;

FIG7 is a schematic diagram showing the structure of a processor according to an embodiment of the present disclosure;

FIG8 is a structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

FIG. 9 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure.

Detailed ways

The technical solution disclosed in the present invention provides a method for controlling a processor, an integrated circuit device and a corresponding processor thereof. Specifically, the processor includes a plurality of processing circuits, a timing control circuit and a control circuit, wherein each processing circuit is used to perform arithmetic operations. Different from the solution of reducing the power consumption of the processor by passive frequency modulation in the prior art. The present invention adopts an active frequency reduction method, and only performs frequency reduction on the processing circuit with high power consumption, thereby shortening the system response time, and at the same time does not affect the performance of other processors, or the scalar calculation circuit, vector calculation circuit, and input-output circuit in the same processor.

The technical solution of the present disclosure and its multiple embodiments will be clearly and completely described below in conjunction with the accompanying drawings. It should be understood that the present disclosure sets forth many specific details in order to provide a thorough understanding of the embodiments described in the present disclosure. However, those of ordinary skill in the art can implement the multiple embodiments described in the present disclosure without these specific details under the guidance of the present disclosure. In other cases, the present disclosure does not describe in detail the well-known methods, processes and components, so as not to unnecessarily obscure the embodiments described in the present disclosure. Moreover, the description should not be regarded as limiting the scope of the embodiments described in the present disclosure.

FIG. 1 is a schematic diagram showing the structure of a processor 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , the processor may include, among other things, a plurality of processing circuits 101, each of which is used to perform computing operations, such as operations involving the field of artificial intelligence. The processor also includes a plurality of timing circuits 102, each of which is connected to a corresponding one or more of the plurality of processing circuits, and is configured to adjust the clock signal of the connected processing circuit so as to adjust the power consumption of the processor accordingly. According to the scheme of the present disclosure, the processing circuit here may be a computing core, including circuits such as a scalar computing circuit, a vector computing circuit, and the like, and a plurality of processing circuits may form a computing core cluster.

Further, the processor also includes a control circuit 103, which is configured to manipulate some or all of the multiple timing control circuits according to the instruction, so as to instruct the manipulated timing control circuit to adjust the clock signal of the processing circuit connected thereto. According to different implementation scenarios, the instructions here can be obtained in a variety of ways. For example, the instruction can be an instruction received from an external input of the processor. For another example, the instruction can be an instruction generated by the processor according to one or more of the operation mode to be executed, the data type, and the working mode. In addition, the instruction can also be an instruction generated based on the current workload of the processor.

In one embodiment, in adjusting the clock signal of the connected processing circuit, the timing control circuit is configured to reduce or increase the frequency of the clock signal of the processing circuit according to the control of the control circuit. For example, the control circuit can control the timing control circuit to eliminate at least one clock edge signal in the clock signal of one or more processing circuits connected thereto to reduce the frequency of the clock signal. Conversely, the control circuit can also control the timing control circuit to restore the eliminated clock edge signal of one or more processing circuits connected thereto to increase the frequency of the clock signal. Examples of clock edge signals and their details will be described later in conjunction with FIG. 4.

In the above-mentioned operation of eliminating at least one clock edge signal in the clock signal to reduce the frequency of the clock signal, in order to avoid the situation where multiple processing circuits may switch from full load to no load or from high load to low load, resulting in excessive noise. Here, the range of high load and low load can be determined, for example, according to the specific application scenario, combined with actual measurement results and empirical values. In one embodiment, each of the timing control circuits is configured under the control of the control circuit to make the clock edge signal eliminated by it not overlap or overlap less with the clock edge signal eliminated by other timing control circuits. Further, the situation of no overlap or little overlap can include the eliminated clock edge signal and the clock edge signal eliminated by other timing control circuits being staggered at predetermined intervals.

In one or more embodiments, the processor of the present disclosure may further include a mode circuit 104, which is configured to associate each of a plurality of predetermined clock edge intervals with an elimination mode for eliminating a clock edge signal. Thus, the mode circuit may include multiple elimination modes. In some application scenarios, these elimination modes may be determined based on empirical values and pre-configured in the mode circuit. As an example of implementation, it is assumed that the mode circuit may be configured with five elimination modes, namely "1", "7/8", "3/4", "1/2" and "1/4", wherein each elimination mode represents a mode in which a timing control circuit performs clock signal adjustment. Specifically, the first elimination mode "1" indicates that the clock edge signal does not need to be eliminated; the second elimination mode "7/8" indicates that one clock edge signal is eliminated in eight consecutive clock edge signals; the third elimination mode "3/4" indicates that one clock edge signal is eliminated in four consecutive clock edge signals; the fourth elimination mode "1/2" indicates that one clock edge signal is eliminated in two consecutive clock edge signals; and the fifth elimination mode "1/4" indicates that three clock edge signals are eliminated in four consecutive clock edge signals.

In some application scenarios, the control circuit may query the mode circuit according to the instruction to obtain the corresponding elimination mode, so as to determine whether to instruct the timing circuit to operate in the elimination mode. Further, the control circuit may also compare the obtained elimination mode with the current elimination mode of the timing circuit to determine whether the two are the same. When it is determined that the two are different, the control circuit may instruct the timing circuit to change the current elimination mode to the obtained elimination mode, so as to make corresponding adjustments to the clock signal of the processing circuit connected to the timing circuit; conversely, when the two are the same, the control circuit may instruct the timing circuit to remain in the current elimination mode. In some embodiments, before making corresponding adjustments to the clock signals of the multiple processing circuits, the control circuit may also be configured to perform synchronization operations on the multiple processing circuits being manipulated. Further, in the synchronization operation, the control circuit may also determine whether the multiple processing circuits are in an idle state. In response to determining that the multiple processing circuits are in the idle state, the control circuit may instruct the corresponding multiple timing circuits to make corresponding adjustments to the clock signals of the multiple processing circuits, such as eliminating or restoring certain clock edge signals, so as to make corresponding adjustments to the power consumption of the processor.

The above describes a schematic diagram of the structure of a processor that can implement the technical solution of the present disclosure in conjunction with FIG1. Based on the above description, those skilled in the art can understand that the processor shown in FIG1 can also be implemented in an integrated circuit device or a board. Therefore, the present disclosure actually also discloses an integrated circuit device or a board, which includes one or more of the aforementioned processors. In addition, it should be noted that the above description of the processor structure and arrangement is exemplary and not restrictive, and those skilled in the art can make appropriate modifications to the structure and arrangement shown as needed without departing from the spirit and scope of the present disclosure.

FIG2 is a flow chart showing a method 200 for controlling a processor according to an embodiment of the present disclosure. Here, the processor controlled by the method 200 may be the processor described in conjunction with FIG1 , which also includes a plurality of processing circuits, a plurality of timing circuits and a control circuit, and optionally also includes a mode circuit. In view of this, the above description of the processor in FIG1 is also applicable to the processor controlled by the method 200, and thus will not be repeated.

As shown in FIG. 2 , at step 201 , method 200 instructs the control circuit to manipulate some or all of the multiple timing control circuits according to the instruction. The instructions described here are of the same nature as the instructions described in conjunction with FIG. 1 and may have different sources. For example, the received instruction may be an input instruction from outside the processor. For another example, the received instruction may also be an instruction generated based on the current workload of the processor. In one embodiment, the received instruction may be generated by the processor according to one or more of the operation mode to be executed, the data type (e.g., an integer, a fixed-point number, or a floating-point number), and the working mode (e.g., a single-core mode, a dual-core mode, or a quad-core mode). For example, the aforementioned operation mode may be an operation mode composed of at least one or more of one or more multipliers, one or more adders, an addition tree composed of adders, a scalar processing circuit, a vector processing circuit, an input-output circuit, and the like.

Next, at step 202 , the method 200 instructs the controlled timing control circuit to adjust the clock signal of the processing circuit connected thereto in response to the control of the control circuit, thereby achieving power consumption control.

Although not shown in FIG. 2 , as described above, adjusting the clock signal includes reducing or increasing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit. Specifically, the frequency of the clock signal can be reduced by eliminating at least one clock edge signal in the clock signal; or, the eliminated clock edge signal can be restored to increase the frequency of the clock signal. In addition, in the process of eliminating the clock edge, the clock edge signal eliminated by the manipulated timing control circuit can be instructed not to overlap or overlap less with the clock edge signals eliminated by other timing control circuits, for example, these eliminated clock edge signals can be staggered at predetermined intervals in time.

The method for controlling the processor is briefly described above in conjunction with FIG. 2 , and will be further described in detail below in conjunction with FIG. 3 .

FIG3 is a detailed flow chart showing a method 300 for controlling a processor according to an embodiment of the present disclosure. Through the following description, those skilled in the art can understand that FIG3 is a further refinement of the method for controlling a processor shown in FIG2, and the description of FIG2 is also applicable to the content shown in FIG3.

As shown in Figure 3, at step 301, method 300 obtains instructions. The same or similar to the contents described in conjunction with Figures 1-2, the instructions can be received from instructions input from outside the processor. For example, the externally input instructions can be software outputs from different levels. In addition, the instructions can also be instructions generated based on the current workload or operating mode of the processor. When the above instructions are generated according to the operating mode of the processor, different processor operating modes can correspond to different numbers of processor cores (such as the dual-core or quad-core mentioned above). Based on these operating modes, the processor can generate associated instructions, thereby adjusting its clock signal accordingly.

Next, the method 300 proceeds to steps 302 and 303, respectively. Specifically, at step 302, the method 300 causes the control circuit to query the mode circuit according to the input instruction to obtain the corresponding elimination mode, so as to determine whether to instruct the timing control circuit to operate in the elimination mode. Here, the mode circuit is the same as the mode circuit shown in FIG. 1, which can be configured to associate each of a plurality of predetermined intervals with a corresponding one of a plurality of elimination modes of an elimination clock edge signal.

At step 303, the method 300 instructs the control circuit to query the current existing elimination mode of part or multiple timing circuits connected to one or more processing circuits. Next, at step 304, the method 300 instructs the control circuit to compare the elimination mode obtained from the mode circuit with the current elimination mode of the timing circuit to determine whether the two are the same. When the two are the same, the control circuit instructs the timing circuit to remain in the current elimination mode, and the process can return to step 301 to start the operation of re-acquiring instructions. However, when it is determined at step 304 that the two are different, the process proceeds to step 305. Here, the method 300 instructs the control circuit to perform a pre-operation before adjusting the clock signal of the processing circuit according to the obtained elimination mode. For example, before adjusting the clock signals of multiple processing circuits accordingly, the control circuit can perform a synchronization operation on multiple controlled processing circuits that need to be adjusted. Additionally or optionally, in the synchronization operation, the control circuit can determine whether the multiple processing circuits are in an idle state. For ease of understanding, assuming that there are four timing control circuits that need to adjust the clock signals of the processing circuits connected thereto, at the first clock edge signal, the control circuit can synchronize the four clock signals of the processing circuits, that is, after determining that the processing circuit is in an idle state, the adjustment of the four clock signals is started. The advantage of introducing idle detection here is that the processing circuit has no computational work at this time, so the power consumption is low. Furthermore, the noise introduced by the timing control circuit when performing clock signal adjustment is relatively small.

After completing the above-mentioned exemplary pre-operation, the process proceeds to step 306, where method 300 instructs the control circuit to instruct the timing circuit to make corresponding adjustments to the clock signal of the processing circuit connected thereto. Specifically, according to the elimination mode obtained in the mode circuit, the control circuit instructs the timing circuit to reduce or increase the frequency of the clock signal of the processing circuit connected thereto. For example, the control circuit may instruct the timing circuit to eliminate at least one clock edge signal in the clock signal to reduce the frequency of the clock signal. For example, when the elimination mode obtained is the "3/4" described above, it indicates that the timing circuit will reduce the frequency of the clock signal of the processing circuit connected thereto. To this end, the control circuit may instruct the timing circuit to eliminate one clock edge signal among four consecutive clock edge signals of the processing circuit. Different from the aforementioned frequency reduction, the control circuit may also instruct the timing circuit to restore the eliminated clock edge signal to increase the frequency of the clock signal.

In one implementation scenario, assuming that the elimination pattern obtained by the control circuit from the mode circuit is "7/8" and the elimination pattern in the current timing circuit is "1", by comparing the elimination patterns obtained by the control circuit from the mode circuit and the timing circuit respectively, it can be determined that the two results are different. The control circuit can now instruct the timing circuit to change the current elimination pattern "1" to the obtained elimination pattern "7/8". Based on the obtained elimination pattern, the timing circuit will reduce the clock signal frequency of the processing circuit. Specifically, the timing circuit can perform elimination of one clock edge signal in eight consecutive clock edge signals to reduce the clock signal frequency of the processing circuit.

In another implementation scenario, assuming that the elimination mode in the acquired mode circuit is "1" and the elimination mode in the current timing circuit is "7/8", by comparing the elimination modes obtained by the control circuit from the mode circuit and the timing circuit respectively, it can be determined that the two results are different. The control circuit can then instruct the timing circuit to change the current elimination mode "7/8" to the obtained elimination mode "1". Based on the obtained elimination mode, the timing circuit can increase the clock signal frequency of the processing circuit. Specifically, the timing circuit can perform a clock edge signal of the recovery elimination to increase the clock signal frequency of the processing circuit.

As mentioned above, in the case where the timing control circuit executes to eliminate at least one clock edge signal in the clock signal, the control circuit instructs the timing control circuit to eliminate the clock edge signal and the clock edge signal eliminated by other timing control circuits to not overlap or overlap less, for example, they are arranged in a staggered manner at a predetermined interval. Thus, by crossing in time, it is possible to avoid the problem of introducing large noise when all processing circuits that need to adjust the clock signal frequency are switched from full load to no load or from high load to low load at the same time.

Optionally, when the input instruction is an instruction input from outside the processor, at step 302, the control circuit may query the mode circuit to obtain a corresponding elimination mode, and thereafter the process may directly proceed to step 305, that is, the control circuit performs preprocessing before adjusting the clock signal of the processing circuit according to the obtained elimination mode. Then, at step 306, the control circuit will instruct the timing circuit to adjust the clock signal of the processing circuit connected thereto accordingly according to the elimination mode obtained at step 302. Alternatively, after executing step 302, step 306 may also be directly executed.

FIG4 is a timing diagram showing the manipulation of clock signals according to an embodiment of the present disclosure. The four clock signals 0, 1, 2 and 3 shown (each clock signal includes respective exemplary clock edge signals 1-6) can be the clock signals of the processing circuits described in conjunction with FIGS. 1-3 , and thus can correspond to timing circuits 0, 1, 2 and 3, respectively. As can be seen from FIG4 , the current elimination mode is the aforementioned "3/4", i.e., one clock edge signal is eliminated in four consecutive clock edge signals. The operation of the present disclosure will be described below based on the elimination mode.

First, the control circuit instructs the timing circuit to perform the clock signal adjustment according to the obtained elimination mode "3/4". Before performing the adjustment operation, preprocessing of idle detection of multiple processing circuits can be performed as needed. After performing the preprocessing, the timing circuit performs the clock edge signal elimination operation under the elimination mode "3/4" on the clock signal of the processing circuit connected to it (the eliminated clock edge signal is shown in the figure with a dotted line).

Specifically, according to the above elimination mode "3/4", the control circuit instructs the timing control circuit 0 to eliminate a clock edge signal after every three consecutive clock signals starting from the second clock edge signal 401 (i.e., clock edge signal 2) for clock signal 0. Next, the timing control circuit 1 performs an operation of eliminating a clock edge signal starting from the third clock edge signal 403 (i.e., clock edge signal 3) for clock signal 1. Similarly, the timing control circuit 2 performs an operation of eliminating a clock edge signal starting from the fourth clock edge signal 404 (i.e., clock edge signal 4) for clock signal 2, and the timing control circuit 3 performs an operation of eliminating a clock edge signal starting from the fifth clock edge signal 405 (i.e., clock edge signal 5) for clock signal 3. When each of the four clock signals completes the elimination of a clock edge signal, it is said to complete an elimination cycle.

After the execution of the first elimination cycle above, the next elimination cycle can be executed. To this end, the control circuit instructs the timing circuit 0 to continue to perform the operation of eliminating the next clock edge signal from the sixth clock edge signal 402 (i.e., clock edge signal 6) on the clock signal 0. By analogy, the subsequent elimination operation will continue to be performed in sequence according to the sequence number of the clock signal. The elimination operation will continue until the control circuit receives a new instruction, and the elimination mode obtained from the mode circuit is different from the current elimination mode of the timing circuit, and the elimination operation in the current elimination mode will stop. Then, the control circuit continues to perform the elimination operation in the new elimination mode according to the newly obtained elimination mode.

It should be understood that the description of the clock signal adjustment mode in FIG4 above is merely illustrative and not restrictive, and those skilled in the art, under the guidance of the present disclosure, can change the number of clock signals and their elimination modes in FIG4 according to the number of processing circuits.

FIG5 is a simplified flow chart showing a method 500 for controlling a processor according to an embodiment of the present disclosure. As will be appreciated by those skilled in the art, the processor involved in FIG5 may be the processor described in conjunction with FIG1 and includes a plurality of timing control circuits and one or more processing circuits connected thereto. Therefore, the description of the processor in FIG1 is also applicable to the processor involved in the method 500.

As shown in Figure 5, at step 501, method 500 obtains instructions for adjusting the power of the processor on the processor. In one embodiment, the processor may include one or more processing circuits, so that obtaining the instructions includes obtaining instructions for adjusting the power of one or more processing circuits on the processor. According to the scheme disclosed herein, the instructions obtained can be generated in a variety of ways. For example, instructions are generated based on one or more of the operation mode, data type, and working mode to be executed by the processor. For another example, instructions can be generated based on the current workload of the processor. In some embodiments, the instructions can also be microinstructions or microoperations, which can be control signals or finer-grained instructions or operations obtained by parsing the instructions. In some other embodiments, the instructions obtained can be program instructions received from inside or outside the processor, or machine instructions formed after the program instructions are compiled.

After receiving the above-mentioned instruction, at step 502, method 500 adjusts the power of the processor based on the instruction.

In some embodiments, when the processor includes multiple timing control circuits, each of which is connected to one or more of the multiple processing circuits, some or all of the multiple timing control circuits can be manipulated according to instructions to instruct the timing control circuits to adjust the power of one or more processing circuits connected thereto. In an application scenario, adjusting the power of one or more processing circuits may include adjusting the clock signal of the connected processing circuit. In one embodiment, the aforementioned adjustment may include eliminating at least one clock edge signal of the processing circuit to reduce the power of the processing circuit; or restoring the eliminated at least one clock edge signal to increase the power of the processing circuit.

Based on the above description, those skilled in the art can understand that the adjustment of the power of the processing circuit in method 500 can adopt the same method as described above in combination with Figures 1-4, so the aforementioned various operations on clock edge adjustment are also applicable to the operations here, and therefore will not be repeated.

FIG6 is a detailed flow chart showing a method 600 for controlling a processor according to an embodiment of the present disclosure. Through the following description, those skilled in the art can understand that the method flow of FIG6 is a further refinement of the content shown in FIG5. Therefore, the technical description of FIG5 is also applicable to the content shown in FIG6.

As shown in Figure 6, method 600 executes one or more of steps 601-604 respectively to obtain instructions for adjusting processor power. Those skilled in the art will appreciate that the steps herein are not limited to the described step number sequence, but may adopt other sequences.

Specifically, when executing step 601, method 600 generates instructions according to one or more of the operation mode, data type, and working mode to be executed. In one embodiment, the operation mode can be an operation mode formed by at least one or more of one or more multipliers, one or more adders, an adder tree composed of adders, a scalar processing circuit, a vector processing circuit, an input-output circuit, etc. participating in the operation. In another embodiment, the data type includes multiple data types, such as integer 16-bit data (expressed as int16), fixed-point 8-bit data (expressed as fix8), floating-point 16-bit data (expressed as float16) or floating-point 32-bit data (expressed as float32), etc.

At step 602, method 600 may generate instructions according to the current workload of the processor. At step 603, method 600 may receive program instructions from outside the processor or receive machine instructions formed by mutation of program instructions. In parallel, at step 604, method 600 may receive microinstructions or microoperation instructions, which may be control signals obtained by parsing the instructions or finer-grained instructions or operations.

After executing any one of the above steps 601, 602, 603 and 604, the method 600 proceeds to step 605, where the method 600 can select one of the multiple elimination modes based on the instruction, for example, through the aforementioned mode circuit. After selecting an elimination mode, at step 606, the method 600 can determine whether the selected elimination mode is the same as the current elimination mode of the processing circuit. When the two are different, the method 600 instructs the timing circuit to change the current elimination mode to the selected elimination mode, and steps 607 and 608 will be executed for this purpose; on the contrary, when the two are the same, the timing circuit is instructed to remain in the current elimination mode, and the process returns to step 605.

In step 607, the method 600 performs synchronization operations on multiple processing circuits according to the instructions to determine whether the multiple processing circuits are in an idle state, that is, the optional preprocessing operation described above in conjunction with FIG. 3. Next, when it is determined that the multiple processing circuits are in an idle state, at step 608, the method 600 instructs the corresponding multiple timing circuits to make corresponding adjustments to the clock signals of the multiple processing circuits. For example, at least one clock edge signal of the processing circuit is eliminated to reduce the power of the processing circuit; or, at least one eliminated clock edge signal is restored to increase the power of the processing circuit. For the clock edge elimination operation, in terms of time, the present disclosure proposes that the clock edge signal eliminated by each timing circuit does not overlap or overlaps less with the clock edge signal eliminated by other timing circuits. Further, in the scenario of no overlap or little overlap, the present disclosure also proposes that the eliminated clock edge signal and the clock edge signal eliminated by other timing circuits can be arranged alternately at predetermined intervals. In addition, in some implementation scenarios, step 607 may not be performed and step 608 may be performed directly.

Fig. 7 is a schematic diagram showing the structure of a processor according to an embodiment of the present disclosure. It is understood that the processor described herein can execute the embodiments described above in conjunction with Figs. 5-6, and the technical details described in Figs. 5-6 are also applicable to the description of Fig. 7.

As shown in FIG7 , the processor of the present disclosure may generally include an instruction fetch circuit 702 and an instruction execution circuit 704. In one or more embodiments, the instruction fetch circuit 702 may be configured to fetch instructions for adjusting the power of the processor. Further, when the processor includes one or more processing circuits, the instruction fetch circuit 702 may be configured to fetch instructions for adjusting the power of the one or more processing circuits on the processor.

In one or more embodiments, the instruction execution circuit 704 may be configured to adjust the power of the processor based on the instruction. Specifically, when the processor further includes a plurality of timing control circuits, wherein each timing control circuit is connected to one or more of the plurality of processing circuits, the instruction execution circuit 704 may be configured to manipulate part or all of the plurality of timing control circuits according to the instruction to instruct the timing control circuit to adjust the power of the one or more processing circuits connected thereto.

Based on the above description in combination with Figure 7, those skilled in the art can also understand that the processor shown in Figure 7 can also be implemented in an integrated circuit device. Therefore, the present disclosure also discloses an integrated circuit device, which includes the aforementioned processor.

FIG8 is a structural diagram showing a combined processing device 800 according to an embodiment of the present disclosure. As shown in the figure, the combined processing device 800 includes a processing device 802, which may include the aforementioned processor of the present disclosure and may be configured to execute the aforementioned control method described in conjunction with the accompanying drawings. In one or more embodiments, the processing device may also be the aforementioned chip or integrated circuit device. In addition, the combined processing device also includes a universal interconnect interface 804 and other processing devices 806. The processing device 802 according to the present disclosure can interact with other processing devices 806 through the universal interconnect interface 804 to jointly complete the operation specified by the user.

According to the scheme disclosed herein, the other processing device may include one or more types of processors among general and/or special processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), an artificial intelligence processor, etc., and the number of processors may not be limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the processing device disclosed herein (which may be embodied as an artificial intelligence-related computing device) and external data and control, and perform functions including but not limited to data transfer, and complete basic control of the start and stop of the machine learning computing device; other processing devices may also collaborate with machine learning-related computing devices to jointly complete computing tasks.

According to the solution disclosed herein, the universal interconnect interface can be used to transmit data and control instructions between the processing device and other processing devices. For example, the processing device can obtain the required input data from other processing devices via the universal interconnect interface and write it into the storage device (or memory) on the processing device chip. Further, the processing device can obtain control instructions from other processing devices via the universal interconnect interface and write them into the control cache on the processing device chip. Alternatively or optionally, the universal interconnect interface can also read the data in the storage module of the processing device and transmit it to other processing devices.

Optionally, the combined processing device may further include a storage device 808, which may be connected to the processing device and the other processing devices, respectively. In one or more embodiments, the storage device may be used to store data of the processing device and the other processing devices, especially data that cannot be fully stored in the internal or on-chip storage device of the processing device or other processing devices.

According to different application scenarios, the combined processing device disclosed in the present invention can be used as a SOC chip system for mobile phones, robots, drones, video acquisition equipment and other devices, effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Certain components such as cameras, displays, mice, keyboards, network cards or wifi interfaces.

In some embodiments, the present disclosure further discloses a chip, which includes the above processing device or the combined processing device. In other embodiments, the present disclosure further discloses a chip packaging structure, which includes the above chip.

In some embodiments, the present disclosure also discloses a board card, which includes the above chip packaging structure. Referring to FIG. 9 , it provides the above exemplary board card, which, in addition to the above chip 902 , may also include other supporting components, including but not limited to: a storage device 904 , an interface device 906 , and a control device 908 .

The memory device is connected to the chip in the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 910. Each group of memory cells is connected to the chip via a bus. It is understood that each group of memory cells may be DDRSDRAM ("Double Data Rate SDRAM").

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out at the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

In one embodiment, each group of the storage units includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is arranged in the chip to control the data transmission and data storage of each of the storage units.

The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 912 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces. This disclosure does not limit the specific manifestations of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). In one or more embodiments, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and/or multiple processing circuits in the chip.

In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the above-mentioned board. According to different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a means of transportation, a household appliance, and/or a medical device. The means of transportation include an airplane, a ship and/or a vehicle; the household appliances include a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, and a range hood; the medical equipment includes an MRI, an ultrasound machine and/or an electrocardiograph.

It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided in the present disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, optical, acoustic, magnetic or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software program modules.

If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including a number of instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

The foregoing content can be better understood in accordance with the following terms:

Clause A1. A processor comprising:

a plurality of processing circuits, wherein each processing circuit is configured to perform an arithmetic operation;

a plurality of timing control circuits, wherein each timing control circuit is connected to a corresponding one or more of the plurality of processing circuits and is configured to adjust a clock signal of the connected processing circuit; and

The control circuit is configured to control part or all of the multiple timing control circuits according to the instruction, so as to instruct the controlled timing control circuit to adjust the clock signal of the processing circuit connected thereto.

Clause A2. A processor according to clause A1, wherein in adjusting a clock signal of a connected processing circuit, the timing circuit is configured to:

reducing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit; or

The frequency of the clock signal of the processing circuit is increased according to the control circuit.

Clause A3. The processor of clause A2, wherein in reducing or increasing the frequency of the clock signal, the timing control circuit is configured to perform, based on the manipulation of the control circuit:

Eliminating at least one clock edge signal in a clock signal to reduce the frequency of the clock signal; or

The eliminated clock edge signal is restored to increase the frequency of the clock signal.

Item A4. A processor according to Item A3, wherein in eliminating at least one clock edge signal in a clock signal, each of the timing control circuits, under the control of the control circuit, is configured to make the clock edge signal it eliminates not overlap or overlap less with the clock edge signals eliminated by other timing control circuits.

Item A5. A processor according to Item A4, wherein the eliminated clock edge signal does not overlap or overlaps less with the clock edge signals eliminated by other timing control circuits, including that the eliminated clock edge signal and the clock edge signals eliminated by other timing control circuits are staggered at predetermined intervals.

Clause A6. The processor of clause A5, further comprising:

a mode circuit configured to associate each of a plurality of the predetermined intervals with an elimination mode for eliminating a clock edge signal,

The control circuit is further configured to query the mode circuit according to the instruction to obtain a corresponding elimination mode, so as to determine whether to instruct the timing control circuit to operate in the elimination mode.

Clause A7. The processor of clause A6, wherein in determining whether to instruct the timing circuit to operate in the elimination mode, the control circuit is further configured to:

comparing the obtained elimination pattern with the current elimination pattern of the timing control circuit to determine whether the two are the same; and

In response to the obtained elimination mode being different from the current elimination mode, the timing control circuit is instructed to change the current elimination mode to the obtained elimination mode, so as to adjust the clock signal of the processing circuit accordingly.

Clause A8. The processor of clause A7, wherein in response to the obtained erasure mode being the same as the current erasure mode, the control circuit is further configured to:

The timing circuit is instructed to remain in the current elimination mode.

Clause A9. A processor according to any one of clauses A1-A8, wherein in operating the part or all of the plurality of timing control circuits according to the instruction, the control circuit is further configured to:

Before adjusting the clock signals of the plurality of processing circuits accordingly, a synchronization operation is performed on the plurality of processing circuits being controlled.

Clause A10. The processor of clause A9, wherein in the synchronous operation, the control circuit is further configured to:

determining whether the plurality of processing circuits are in an idle state; and

In response to determining that the plurality of processing circuits are in the idle state, the corresponding plurality of timing control circuits are instructed to adjust the clock signals of the plurality of processing circuits accordingly.

Item A11. A processor according to Item A10, wherein the instruction is an instruction received from an external input of the processor.

Item A12. A processor according to Item A10, wherein the instruction is an instruction generated by the processor based on one or more of an operation mode, a data type, and a working mode to be executed.

Clause A13. A processor as described in clause A10, wherein the instructions are instructions generated based on a current workload of the processor.

Clause A14. An integrated circuit device comprising a processor according to any one of clauses A1-A13.

Clause A15. A method for controlling a processor, wherein the processor comprises a plurality of processing circuits, a plurality of timing circuits and a control circuit, wherein the processing circuits are configured to perform arithmetic operations and each timing circuit is connected to a corresponding one or more processing circuits, the method comprising:

instructing the control circuit to operate part or all of the plurality of timing control circuits according to the instruction; and

In response to the manipulation of the control circuit, the manipulated timing control circuit is instructed to adjust the clock signal of the processing circuit connected thereto.

Clause A16. The method of clause A15, wherein in adjusting the clock signal of the connected processing circuit, the method further comprises instructing the timing circuit to perform:

reducing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit; or

The frequency of the clock signal of the processing circuit is increased according to the control circuit.

Clause A17. The method of clause A16, wherein in reducing or increasing the frequency of the clock signal, the method further comprises instructing the timing circuit to perform:

Eliminating at least one clock edge signal in a clock signal to reduce the frequency of the clock signal; or

The eliminated clock edge signal is restored to increase the frequency of the clock signal.

Item A18. A method according to Item A17, wherein in eliminating at least one clock edge signal in a clock signal, the method includes, in response to manipulation of the control circuit, indicating that the clock edge signal eliminated by the manipulated timing circuit does not overlap or has little overlap with the clock edge signals eliminated by other timing circuits.

Item A19. A method according to Item A18, wherein the eliminated clock edge signal does not overlap or overlaps less with the clock edge signals eliminated by other timing control circuits, including that the eliminated clock edge signal is staggered at predetermined intervals with the clock edge signals eliminated by other timing control circuits.

Clause A20. The method of clause A19, wherein the processor further comprises a mode circuit, the method further comprising:

instructing the mode circuit to associate each of a plurality of the predetermined intervals with a corresponding one of a plurality of elimination modes for an elimination clock edge signal; and

The control circuit is instructed to query the mode circuit according to the instruction to obtain a corresponding elimination mode, so as to determine whether to instruct the timing control circuit to operate in the elimination mode.

Clause A21. The method of clause A20, wherein in determining whether to instruct the timing circuit to operate in the elimination mode, the method further comprises instructing the control circuit to perform:

comparing the obtained elimination pattern with the current elimination pattern of the timing control circuit to determine whether the two are the same; and

In response to the obtained elimination mode being different from the current elimination mode, the timing control circuit is instructed to change the current elimination mode to the obtained elimination mode, so as to adjust the clock signal of the processing circuit accordingly.

Clause A22. The method of clause A21, wherein in response to the obtained elimination mode being the same as the current elimination mode, the method further comprises instructing the control circuit to perform:

The timing circuit is instructed to remain in the current elimination mode.

Clause A23. A method according to any one of clauses A15-A22, wherein in operating some or all of the plurality of timing control circuits according to the instruction, the method further comprises instructing the control circuit to execute:

Before adjusting the clock signals of the plurality of processing circuits accordingly, a synchronization operation is performed on the plurality of processing circuits being controlled.

Clause A24. The method of clause A23, wherein in the synchronous operation, the control circuit is further instructed to perform:

determining whether the plurality of processing circuits are in an idle state; and

In response to determining that the plurality of processing circuits are in the idle state, the corresponding plurality of timing control circuits are instructed to adjust the clock signals of the plurality of processing circuits accordingly.

Item A25. A method according to Item A24, wherein the instruction is an instruction received from an external input of the processor.

Item A26. A method according to Item A24, wherein the instruction is an instruction generated by the processor based on one or more of an operation mode, a data type, and a working mode to be executed.

Clause A27. A method according to clause A24, wherein the instructions are instructions generated based on a current workload of the processor.

It should be understood that the terms "first", "second", "third", and "fourth" in the claims, specifications, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and/or their collections.

It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and/or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present disclosure, the specific implementation methods and the scope of application of the present disclosure, all belong to the scope of protection of the present disclosure. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims (21)

1. A processor, comprising: a plurality of processing circuits, wherein each processing circuit is configured to perform an arithmetic operation; a plurality of timing control circuits, wherein each timing control circuit is connected to a corresponding one or more of the plurality of processing circuits and is configured to adjust a clock signal of the connected processing circuit; a mode circuit including a plurality of elimination modes and configured to associate each of a plurality of predetermined intervals with an elimination mode that eliminates a clock edge signal; and A control circuit configured to query the mode circuit to obtain a corresponding elimination mode according to the instruction, so as to determine whether to instruct the timing control circuit to operate in the elimination mode; and to manipulate part or all of the plurality of timing control circuits according to the instruction, so as to instruct the manipulated timing control circuit to perform the adjustment on the clock signal of the processing circuit connected thereto; In adjusting the clock signal of the connected processing circuit, the timing control circuit is configured to: Eliminating at least one clock edge signal in the clock signal according to the manipulation of the control circuit to reduce the frequency of the clock signal of the processing circuit; or increasing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit; In which, in eliminating at least one clock edge signal in the clock signal, each timing control circuit is configured, under the control of the control circuit, to make the clock edge signal eliminated by it not overlap or overlap less with the clock edge signals eliminated by other timing control circuits, and the eliminated clock edge signal and the clock edge signals eliminated by other timing control circuits are arranged alternately at the predetermined interval. 2. The processor according to claim 1, wherein in increasing the frequency of the clock signal, the timing control circuit is configured to perform, according to the control of the control circuit: The eliminated clock edge signal is restored to increase the frequency of the clock signal. 3. The processor of claim 1 , wherein in determining whether to instruct the timing circuit to operate in the elimination mode, the control circuit is further configured to: comparing the obtained elimination pattern with the current elimination pattern of the timing control circuit to determine whether the two are the same; and In response to the obtained elimination mode being different from the current elimination mode, the timing control circuit is instructed to change the current elimination mode to the obtained elimination mode, so as to adjust the clock signal of the processing circuit accordingly. 4. The processor according to claim 3, wherein in response to the obtained erasure mode being the same as the current erasure mode, the control circuit is further configured to: The timing circuit is instructed to remain in the current elimination mode. 5. The processor according to any one of claims 1 to 4, wherein in controlling the part or all of the plurality of timing control circuits according to the instruction, the control circuit is further configured to: Before adjusting the clock signals of the plurality of processing circuits accordingly, a synchronization operation is performed on the plurality of processing circuits being controlled. 6. The processor of claim 5, wherein in the synchronous operation, the control circuit is further configured to: determining whether the plurality of processing circuits are in an idle state; and In response to determining that the plurality of processing circuits are in the idle state, the corresponding plurality of timing control circuits are instructed to adjust the clock signals of the plurality of processing circuits accordingly. 7. The processor according to claim 6, wherein the instruction is an instruction received from an external input of the processor. 8. The processor according to claim 6, wherein the instruction is an instruction generated by the processor according to one or more of an operation mode, a data type, and a working mode to be executed. 9. The processor of claim 6, wherein the instructions are instructions generated based on a current workload of the processor. 10. An integrated circuit device comprising a processor according to any one of claims 1-9. 11. A method for controlling a processor, wherein the processor comprises a plurality of processing circuits, a plurality of timing circuits, a mode circuit and a control circuit, wherein the processing circuit is configured to perform arithmetic operations, and each timing circuit is connected to one or more corresponding processing circuits, the mode circuit comprises a plurality of elimination modes, and is configured to associate each of a plurality of predetermined intervals with an elimination mode for eliminating a clock edge signal, the method comprising: Instructing the control circuit to query the mode circuit to obtain a corresponding elimination mode according to the instruction, so as to determine whether to instruct the timing control circuit to operate in the elimination mode; instructing the control circuit to operate part or all of the plurality of timing control circuits according to the instruction; and In response to the manipulation of the control circuit, instructing the manipulated timing control circuit to adjust the clock signal of the processing circuit connected thereto; In adjusting the clock signal of the connected processing circuit, the method further includes instructing the timing control circuit to execute: Eliminating at least one clock edge signal in the clock signal according to the manipulation of the control circuit to reduce the frequency of the clock signal of the processing circuit; or increasing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit; In eliminating at least one clock edge signal in the clock signal, the method includes, in response to the manipulation of the control circuit, instructing the manipulated timing circuit to eliminate the clock edge signal that does not overlap or has little overlap with the clock edge signals eliminated by other timing circuits, and the eliminated clock edge signal and the clock edge signals eliminated by other timing circuits are arranged alternately at the predetermined interval. 12. The method according to claim 11, wherein in increasing the frequency of the clock signal, the method further comprises instructing the timing control circuit to perform: The eliminated clock edge signal is restored to increase the frequency of the clock signal. 13. The method of claim 11, wherein in determining whether to instruct the timing control circuit to operate in the elimination mode, the method further comprises instructing the control circuit to perform: comparing the obtained elimination pattern with the current elimination pattern of the timing control circuit to determine whether the two are the same; and In response to the obtained elimination mode being different from the current elimination mode, the timing control circuit is instructed to change the current elimination mode to the obtained elimination mode, so as to adjust the clock signal of the processing circuit accordingly. 14. The method according to claim 13, wherein in response to the obtained elimination mode being the same as the current elimination mode, the method further comprises instructing a control circuit to execute: The timing circuit is instructed to remain in the current elimination mode. 15. The method according to any one of claims 11 to 14, wherein in controlling the part or all of the plurality of timing control circuits according to the instruction, the method further comprises instructing the control circuit to execute: Before adjusting the clock signals of the plurality of processing circuits accordingly, a synchronization operation is performed on the plurality of processing circuits being controlled. 16. The method according to claim 15, wherein in the synchronous operation, the control circuit is further instructed to execute: determining whether the plurality of processing circuits are in an idle state; and In response to determining that the plurality of processing circuits are in the idle state, the corresponding plurality of timing control circuits are instructed to adjust the clock signals of the plurality of processing circuits accordingly. The method according to claim 16 , wherein the instruction is an instruction received from an external input of the processor. 18. The method according to claim 16, wherein the instruction is an instruction generated by a processor according to one or more of an operation mode, a data type, and a working mode to be executed. 19. The method of claim 16, wherein the instructions are instructions generated based on a current workload of a processor. 20. A computer device comprising a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the method according to any one of claims 11 to 19. 21. A computer-readable storage medium having a computer program/instruction stored thereon, wherein the computer program/instruction, when executed by a processor, implements the method according to any one of claims 11 to 19.