CN113030586A - Energy measuring device based on peak holding method - Google Patents
Energy measuring device based on peak holding method Download PDFInfo
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- CN113030586A CN113030586A CN202110171578.3A CN202110171578A CN113030586A CN 113030586 A CN113030586 A CN 113030586A CN 202110171578 A CN202110171578 A CN 202110171578A CN 113030586 A CN113030586 A CN 113030586A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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Abstract
The invention belongs to the technical field of signal energy measurement, and particularly relates to an energy measurement device based on a peak preserving method. The circuit comprises a peak holding circuit, an FPGA-ADC circuit and a charge bleeder circuit; the peak holding circuit is used for converting input pulse signal energy into direct-current voltage, and is electrically connected with the FPGA-ADC circuit; the FPGA-ADC circuit is used for realizing analog-to-digital conversion and energy measurement of signals and is electrically connected with the charge bleeding circuit; the charge leakage circuit is used for quickly leaking charges and waiting for the next measurement after the energy is measured, and the charge quick leakage is electrically connected with the peak holding circuit. The invention is suitable for multi-channel energy measurement and has the characteristics of simple structure, high measurement precision and low cost.
Description
Technical Field
The invention belongs to the technical field of signal energy measurement, and particularly relates to an energy measurement device based on a peak preserving method.
Background
Currently, energy measurement methods are classified into various methods, such as a Digital integration method based on an Analog Digital Converter (ADC) chip, a Time Over Threshold (TOT) technique based on pulse width measurement, and the like. Among them, the Peak Hold (Peak Hold) circuit is widely used in electrical signal energy measuring devices, such as CT, PET systems, etc., due to its simple structure and high accuracy.
The mainstream energy measurement technology in the market at present is based on that a commercial medium-high speed ADC chip performs analog-to-digital conversion on an analog electric signal, and then the obtained digital information is sent to an FPGA chip to realize energy measurement through an integral algorithm. However, the scheme has the problems that the number of channels of the PET detectors is large, and a large number of commercial medium-high speed ADC chips are needed for implementation, which increases the system cost and brings large power consumption, and severely limits the integration level of the electronic system.
In addition, some of the devices also use the TOT technology to realize energy measurement, but the dynamic range and the linearity of the devices are poor;
in addition, some peak hold schemes are also adopted and completed by using an ASIC and a commercial ADC chip, but the problems of high cost and inflexible configuration are present.
Therefore, it is necessary to design an energy measuring device suitable for multi-channel energy measurement, which has a simple structure, high measurement accuracy and low cost.
In order to improve the energy measurement precision of the system, the invention uses an analog peak holding circuit to convert an input pulse current signal into a direct current level of which the amplitude is in direct proportion to the signal energy, and then uses an FPGA-ADC to complete high-precision energy measurement. The invention has the advantages of simple structure, high measurement precision and low cost, and is very suitable for the application occasions of multi-channel energy measurement.
For example, in the method for processing ultrahigh-pass-rate current-type digitized pulses based on the FPGA described in the chinese patent application No. CN201810481263.7, the front stage amplifies weak current signals of the detector through an ultrahigh-speed current preamplifier and transmits the amplified weak current signals to the digital circuit part, the amplified weak current signals enter the FPGA and are extracted through a digital high-pass filter in the fast channel to obtain trigger signals, and the slow channel starts to integrate the original current signals to obtain original energy amplitude information of the pulse signals while receiving the trigger signals. Although the current amplification is carried out through the composite current preamplification circuit, the original pulse information can be well kept, the measurement of pulse information such as single particle signal energy and time of a particle signal with the dosage rate of 1GSPS is solved, the conventional high-speed digital multichannel analysis capability can be improved by multiple times through a parallel processing mode, and the pulse counting passing rate of 1GHz can be achieved, the method has the defects that the energy information of the input pulse signal can be converted into a direct current level through multiple steps, the processing efficiency is low, more hardware links are needed in the whole method, the cost is higher, and the method is not beneficial to wide application.
Disclosure of Invention
The invention provides an energy measuring device based on a peak-preserving method, which is suitable for multi-channel energy measurement, and has the advantages of simple structure, high measurement precision and low cost, in order to overcome the problems of high system cost, large power consumption, poor dynamic range and linearity and inflexible configuration in the prior art of the prior energy measuring technology.
In order to achieve the purpose, the invention adopts the following technical scheme:
the energy measuring device based on the peak holding method comprises a peak holding circuit, an FPGA-ADC circuit and a charge bleeder circuit; the peak holding circuit is used for converting input pulse signal energy into direct-current voltage, and is electrically connected with the FPGA-ADC circuit; the FPGA-ADC circuit is used for realizing analog-to-digital conversion and energy measurement of signals and is electrically connected with the charge bleeding circuit; the charge leakage circuit is used for quickly leaking charges and waiting for the next measurement after the energy is measured, and the charge quick leakage is electrically connected with the peak holding circuit.
Preferably, the peak hold circuit includes an operational amplifier a1 and a holding capacitor CholdAnd a resistance RV-I(ii) a The resistor RV-IThe inverting input interface of the operational amplifier A1 is electrically connected; the non-inverting input interface signal of the operational amplifier A1 is grounded; the holding capacitor CholdOne end of each of which is connected to a resistor RV-IElectrically connected with the inverting input interface of the operational amplifier A1, the holding capacitor CholdThe other end of the operational amplifier is electrically connected with the output end of the operational amplifier A1; the output end of the operational amplifier A1 is electrically connected with the FPGA-ADC circuit。
Preferably, the FPGA-ADC circuit comprises an FPGA chip and a resistor Rs; the resistor Rs is electrically connected with the FPGA chip; the output end of the operational amplifier A1 is electrically connected with the FPGA chip.
Preferably, the charge draining circuit comprises a switch SW, a resistor R1 and a resistor R2; the switch SW is electrically connected with the FPGA chip; one end of the resistor R1 is electrically connected with the switch SW, and the other end of the resistor R1 is respectively connected with the holding capacitor CholdResistance RV-IAnd the inverting input interface of the operational amplifier A1 is electrically connected; one end of the resistor R2 is electrically connected with the switch SW, and the other end of the resistor R2 is respectively connected with the holding capacitor CholdAnd is electrically connected to the output of the operational amplifier a 1.
Preferably, the FPGA chip internally comprises a clock generator, an internal comparator and a carry chain TDC structure; a signal output interface of the clock generator is electrically connected with one end of a resistor Rs, and the other end of the resistor Rs is electrically connected with a negative input interface of the internal comparator; the output end of the internal comparator is electrically connected with the carry chain TDC structure; the positive input interface of the internal comparator is electrically connected with the output end of the operational amplifier A1.
Preferably, the clock generator is in a phase-locked loop structure.
Preferably, the FPGA chip further includes a parasitic capacitor Cp therein.
Preferably, the parasitic capacitor Cp and the resistor Rs constitute a low-pass filter circuit.
Compared with the prior art, the invention has the beneficial effects that: (1) the peak holding circuit composed of the operational amplifier, the holding capacitor and the resistor is utilized, and the input pulse signal energy can be directly converted into direct-current voltage; (2) the invention realizes the FPGA-ADC function by using an off-chip resistor, and can convert the analog to digital of the direct-current voltage; (3) the method comprises the following steps that a tristate gate and a time sequence control logic of an FPGA chip are utilized, after analog-to-digital conversion is finished, the charge on a holding capacitor is released rapidly, and low dead time measurement is achieved; (4) the invention has the advantages of simple structure, low cost and high precision.
Drawings
FIG. 1 is a schematic block diagram of an energy measuring device based on a peak preserving method according to the present invention;
FIG. 2 is a schematic diagram of the FPGA-ADC circuit of the present invention for performing measurement;
FIG. 3 is a schematic diagram of a carry chain TDC structure according to the present invention;
FIG. 4 is a flow chart of the energy measurement device based on the peak keeping method for energy measurement according to the present invention;
FIG. 5 is a diagram of a simulation effect of the energy measuring device based on the peak preserving method according to the present invention;
fig. 6 is a diagram of a simulation result of an input-output conversion curve corresponding to fig. 5.
In the figure: and an FPGA chip 1.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention, the following description will explain the embodiments of the present invention with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
Example 1:
the energy measuring device based on the peak hold method as shown in fig. 1 comprises a peak hold circuit, an FPGA-ADC circuit and a charge bleeding circuit; the peak holding circuit is used for converting input pulse signal energy into direct-current voltage, and is electrically connected with the FPGA-ADC circuit; the FPGA-ADC circuit is used for realizing analog-to-digital conversion and energy measurement of signals and is electrically connected with the charge bleeding circuit; the charge leakage circuit is used for quickly leaking charges and waiting for the next measurement after the energy is measured, and the charge quick leakage is electrically connected with the peak holding circuit.
Further, the peak holding circuit comprises an operational amplifier A1 and a holding capacitor CholdAnd a resistance RV-I(ii) a The resistor RV-IThe inverting input interface of the operational amplifier A1 is electrically connected; the operational amplifierThe in-phase input interface signal of A1 is grounded; the holding capacitor CholdOne end of each of which is connected to a resistor RV-IElectrically connected with the inverting input interface of the operational amplifier A1, the holding capacitor CholdThe other end of the operational amplifier is electrically connected with the output end of the operational amplifier A1; the output end of the operational amplifier A1 is electrically connected with the FPGA-ADC circuit. The input pulse voltage signal passes through a resistor RV-IThen converted into a current signal and then charged into a holding capacitor C of an operational amplifier A1holdThe above. When the signal is charged, the capacitor C is keptholdThe dc level of which is proportional to the energy of the input signal. The output signal is pulled up to the measurable range of the back end FPGA-ADC circuit, and then is input to a pin of the FPGA chip for analog-to-digital conversion.
Further, the FPGA-ADC circuit comprises an FPGA chip 1 and a resistor Rs; the resistor Rs is electrically connected with the FPGA chip; the output end of the operational amplifier A1 is electrically connected with the FPGA chip.
Furthermore, the FPGA chip internally comprises a clock generator, an internal comparator and a carry chain TDC structure; a signal output interface of the clock generator is electrically connected with one end of a resistor Rs, and the other end of the resistor Rs is electrically connected with a negative input interface of the internal comparator; the output end of the internal comparator is electrically connected with the carry chain TDC structure; the positive input interface of the internal comparator is electrically connected with the output end of the operational amplifier A1. The positive input interface of the internal comparator is also externally connected with a reference voltage Vref。
Further, the clock generator adopts a phase-locked loop structure.
The clock generator generates a sampling clock, forms a quasi-triangular wave after passing through the low-pass filter circuit, and compares the quasi-triangular wave with an input analog signal through an internal comparator of the FPGA chip to obtain a pulse to be detected. The pulse width of the pulse to be measured is related to the energy of the input signal, the pulse width of the pulse to be measured can be approximately in direct proportion to the amplitude of the input analog signal, the pulse width of the pulse to be measured is measured, the analog-to-digital conversion can be completed, and the energy of the input signal is reversely deduced. The pulse width measurement is completed based on a carry chain TDC structure, and the specific principle is shown in FIG. 2. In fig. 2, c denotes the input analog signal, a denotes the pulse to be measured, and b denotes the amplitude of the input analog signal.
In order to improve the dynamic range of time measurement, a time interpolation mode combining thick time and thin time is adopted. The pulse signal to be detected enters a carry chain TDC structure in the FPGA chip, a carry unit of the carry chain TDC structure comprises taps, and each tap corresponds to one trigger unit. The taps of the carry chain TDC architecture are latched using respective flip-flop chains to obtain tap state levels. The states of the front edge and the rear edge of the pulse to be detected on the carry chain taps at different moments are different, and the fine timestamp information of the front edge and the rear edge of the pulse signal to be detected can be obtained by coding the states of the taps through a coding circuit. The invention utilizes the same carry chain to mark the time state information of the front edge and the back edge of the pulse to be measured at the same time. The coarse time counter can be used for obtaining coarse timestamp information of the front edge and the rear edge of the signal to be detected, and the coarse timestamp information and the rear edge of the signal to be detected can be obtained by combining the coarse timestamp information and the rear timestamp information through packaging logic. And subtracting the front edge time from the back edge time to obtain the pulse signal width. In addition, due to the non-uniformity of the delay between the taps of the carry chain, a non-linear correction of the delay is required. When the system is initialized, the pulse signal generator generates a large number of pulse signals to be measured through being driven by a clock which is not homologous with the system clock, fine time measurement is carried out, the nonlinear correction circuit calculates a correction coefficient according to the number of each counted fine time, and the correction coefficient is stored in a Random Access Memory (RAM) inside the FPGA chip as a Look-up table (LUT). The structure of the carry chain TDC is shown in detail in fig. 3.
Further, as shown in fig. 3, the FPGA chip further includes a parasitic capacitor Cp therein. One end of the parasitic capacitor Cp is electrically connected with the resistor Rs and the negative input interface of the internal comparator respectively, and the other end of the parasitic capacitor Cp is grounded through a signal.
The parasitic capacitance Cp and the resistance Rs constitute a low-pass filter circuit.
Further, the charge draining circuit comprises a switch SW, a resistor R1 and a resistor R2; the switch SW is electrically connected with the FPGA chip; one end of the resistor R1 is electrically connected with the switch SW, and the other end of the resistor R1 is respectively connected with the holding capacitor CholdResistance RV-IAnd the inverting input interface of the operational amplifier A1 is electrically connected; one end of the resistor R2 is electrically connected with the switch SW, and the other end of the resistor R2 is respectively connected with the holding capacitor CholdAnd is electrically connected to the output of the operational amplifier a 1. The resistor R1 and the resistor R2 are bleeder resistors.
The charge bleeder circuit is used for controlling the switch SW through the IO of the FPGA chip after the energy measurement is finished, so that the holding capacitor CholdThe charge on the sensor is quickly discharged and waits for the next measurement. Before the energy measurement starts, the switch SW to which the resistors R1 and R2 are connected is opened, and the signal is held in the holding capacitor CholdAnd (4) charging.
When the FPGA-ADC circuit detects the shape of the input level and judges that the signal flat top appears, the base level is subtracted from the direct-current level voltage to obtain a final energy value, and then the switch SW is closed. The process flow diagram of the entire energy measurement described above is shown in fig. 4.
Furthermore, in order to better illustrate the technical effects of the present invention, the PSPICE software is used to simulate the circuit in the apparatus of the present invention, and the transient waveform is shown in fig. 5. Simulation results show that the circuit in the device works normally, the input signal can be integrated into a direct current level, and the discharge process is correct.
The input signal amplitude is adjusted and then an input-output transfer curve is plotted as shown in fig. 6. The simulation results shown in fig. 6 show that the circuit in the device of the present invention operates with good linearity and a large dynamic range.
The peak holding circuit composed of the operational amplifier, the holding capacitor and the resistor is utilized, and the input pulse signal energy can be directly converted into direct-current voltage; the invention realizes the FPGA-ADC function by using an off-chip resistor, and can convert the analog to digital of the direct-current voltage; and after the analog-to-digital conversion is finished, the charge on the holding capacitor is quickly released by using a three-state gate and a time sequence control logic of the FPGA chip, so that the measurement of low dead time is realized.
Based on the FPGA-ADC principle, the invention uses a simple peak holding circuit composed of an operational amplifier and a capacitor device to convert the energy information of the input pulse signal into a direct current level, and uses an FPGA chip to control the charging and discharging time sequence of a holding capacitor to complete energy measurement. The hardware of the invention only needs a common operational amplifier, a switch, a plurality of resistors and capacitors, and three IO pins of the FPGA chip, and the specific analog-to-digital conversion and measurement are realized by using codes.
The foregoing has outlined rather broadly the preferred embodiments and principles of the present invention and it will be appreciated that those skilled in the art may devise variations of the present invention that are within the spirit and scope of the appended claims.
Claims (8)
1. The energy measuring device based on the peak holding method is characterized by comprising a peak holding circuit, an FPGA-ADC circuit and a charge bleeder circuit; the peak holding circuit is used for converting input pulse signal energy into direct-current voltage, and is electrically connected with the FPGA-ADC circuit; the FPGA-ADC circuit is used for realizing analog-to-digital conversion and energy measurement of signals and is electrically connected with the charge bleeding circuit; the charge leakage circuit is used for quickly leaking charges and waiting for the next measurement after the energy is measured, and the charge quick leakage is electrically connected with the peak holding circuit.
2. The energy measurement device based on the peak hold method according to claim 1, wherein the peak hold circuit comprises an operational amplifier A1, a hold capacitor CholdAnd a resistance RV-I(ii) a The resistor RV-IThe inverting input interface of the operational amplifier A1 is electrically connected; the non-inverting input interface signal of the operational amplifier A1 is grounded; the holding capacitor CholdOne end of each of which is connected to a resistor RV-IElectrically connected with the inverting input interface of the operational amplifier A1, the holding capacitor CholdThe other end of the operational amplifier is electrically connected with the output end of the operational amplifier A1; the output end of the operational amplifier A1 is electrically connected with the FPGA-ADC circuit.
3. The energy measurement device based on the peak hold method according to claim 2, wherein the FPGA-ADC circuit comprises an FPGA chip and a resistor Rs; the resistor Rs is electrically connected with the FPGA chip; the output end of the operational amplifier A1 is electrically connected with the FPGA chip.
4. The energy measurement device based on the peak hold method according to claim 3, characterized in that the charge bleeding circuit comprises a switch SW, a resistor R1 and a resistor R2; the switch SW is electrically connected with the FPGA chip; one end of the resistor R1 is electrically connected with the switch SW, and the other end of the resistor R1 is respectively connected with the holding capacitor CholdResistance RV-IAnd the inverting input interface of the operational amplifier A1 is electrically connected; one end of the resistor R2 is electrically connected with the switch SW, and the other end of the resistor R2 is respectively connected with the holding capacitor CholdAnd is electrically connected to the output of the operational amplifier a 1.
5. The energy measurement device based on the peak-hold method according to claim 4, characterized in that the FPGA chip internally comprises a clock generator, an internal comparator and a carry chain TDC structure; a signal output interface of the clock generator is electrically connected with one end of a resistor Rs, and the other end of the resistor Rs is electrically connected with a negative input interface of the internal comparator; the output end of the internal comparator is electrically connected with the carry chain TDC structure; the positive input interface of the internal comparator is electrically connected with the output end of the operational amplifier A1.
6. The energy measurement device based on the peak-hold method according to claim 5, wherein the clock generator employs a phase-locked loop structure.
7. The peak-hold method based energy measurement device of claim 5 or 6, wherein the FPGA chip further comprises a parasitic capacitance Cp inside.
8. The peak-hold method based energy measurement device of claim 7, wherein the parasitic capacitance Cp and the resistance Rs constitute a low-pass filter circuit.
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| CN202110171578.3A CN113030586A (en) | 2021-02-08 | 2021-02-08 | Energy measuring device based on peak holding method |
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| CN202110171578.3A CN113030586A (en) | 2021-02-08 | 2021-02-08 | Energy measuring device based on peak holding method |
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Citations (4)
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| ATA13288A (en) * | 1988-01-25 | 1989-01-15 | Avl Verbrennungskraft Messtech | CHARGE AMPLIFIER CIRCUIT |
| CN102183779A (en) * | 2010-12-29 | 2011-09-14 | 中国科学院空间科学与应用研究中心 | Multidirectional high energy particle detector |
| CN107167673A (en) * | 2017-05-10 | 2017-09-15 | 南京大学 | A kind of sensor of detectable charge variation feature |
| CN111610549A (en) * | 2020-05-13 | 2020-09-01 | 明峰医疗系统股份有限公司 | Direct Comparison FPGA-ADC Device Based on Single Carry Chain |
-
2021
- 2021-02-08 CN CN202110171578.3A patent/CN113030586A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATA13288A (en) * | 1988-01-25 | 1989-01-15 | Avl Verbrennungskraft Messtech | CHARGE AMPLIFIER CIRCUIT |
| CN1034646A (en) * | 1988-01-25 | 1989-08-09 | 内燃机及测量技术有限公司Avl公司 | Charge amplifier circuit |
| CN102183779A (en) * | 2010-12-29 | 2011-09-14 | 中国科学院空间科学与应用研究中心 | Multidirectional high energy particle detector |
| CN107167673A (en) * | 2017-05-10 | 2017-09-15 | 南京大学 | A kind of sensor of detectable charge variation feature |
| CN111610549A (en) * | 2020-05-13 | 2020-09-01 | 明峰医疗系统股份有限公司 | Direct Comparison FPGA-ADC Device Based on Single Carry Chain |
Non-Patent Citations (1)
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| 苏弘 等: "一种新型电荷灵敏前置放大器和成形峰保持混合电路", 《核电子学与探测技术》 * |
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