CN108848326A - A kind of high dynamic range MCP detector front end reading circuit and its reading method - Google Patents

Abstract

The invention discloses a high dynamic range MCP detector front-end readout circuit and a readout method thereof, belonging to the technical field of semiconductor image sensing, comprising a signal input module, a dynamic range extension module, a buffer module, a high-speed comparator module, a time Digital conversion module and logic circuit module; among them, the photocurrent signal from the detector enters the front-end readout circuit through the signal input module, and then integrates and expands the dynamic range through the dynamic range expansion module, and the integrated voltage signal is buffered The buffer module performs buffer processing, and then transmits to the high-speed comparator module, and the high-speed comparator module includes a first comparator and a second comparator. In the present invention, the process of judging the strength of the input signal is placed inside the pixel for processing, which does not require complicated back-end processing, simplifies the design process of the back-end circuit, and makes the overall chip structure simple, with high pixel filling ratio and chip area Good utilization.

Description

A high dynamic range MCP detector front-end readout circuit and its readout method

technical field

The invention belongs to the technical field of semiconductor image sensing, and specifically designs a high dynamic range MCP detector front-end readout circuit and a readout method thereof.

Background technique

Fast neutron photography technology can obtain detailed internal characteristics of materials through in-depth analysis of the object to be tested, so as to realize the function of non-destructive testing of complex objects and structures. Science and other basic science fields have a wide range of needs and applications.

Single-photon detectors used in the field of fast neutron photography not only need to have single-photon sensitivity, but also need to be able to mark the photons arriving at each moment with high precision, and record the high-precision spatial two-dimensional coordinates of the photon at the same time, that is, Three-dimensional high spatiotemporal resolution detectors with single photon sensitivity are required.

Microchannel plate (MCP) can work in the pulse counting mode, and has a response time of tens of picoseconds and a spatial resolution of several microns, making it the preferred area array photoelectric conversion device for single photon detectors. One, combining it with different charge distribution and processing devices, can form a three-dimensional imaging detector with single-photon sensitivity. In addition, MCP has the advantages of being able to work in a strong magnetic field and having very little dark noise.

Dynamic range (DR) is an important indicator of a single photon detector, which marks the light intensity range that the detector can handle, and the unit of dynamic range is expressed in decibels (dB). One of the factors limiting the dynamic range is the size of the integral capacitance inside the pixel (that is, the well capacity). The larger the capacitance, the greater the detectable light intensity.

In the process of single-photon detection, in order to meet the characteristics of ultra-high brightness and ultra-wide energy spectrum of the photon emission source, the readout circuit must have a high dynamic range, but if only the integration capacitance is increased, the unit pixel area will also decrease. increase. Therefore, in the design process of the front-end readout circuit, it is necessary to consider the compromise between performance and area. It is necessary to reduce the area, reduce power consumption, and improve the dynamic range.

In recent years, the research in the field of fast neutron radiography has attracted widespread attention from the academic community, and the scientific research results of new materials and high-performance MCP single-photon detectors have been continuously proposed internationally. The research involved is less, and the research on the high-performance ASIC chip specially designed for MCP detector signal reading is basically in the blank. In addition, the traditional MCP detector front-end readout circuit design does not optimize the performance parameter of dynamic range, resulting in a very small input signal range of the entire single-photon detection system, and the application field is relatively limited.

In order to give full play to the advantages of MCP’s ability to detect single photons and apply it in fast neutron imaging systems, the traditional readout circuit structure cannot guarantee high-precision spatial resolution and high-precision time at the same time under high count rate conditions. Resolution ability, when the number of charges output by the MCP is too large, the traditional circuit architecture based on the charge amplifier will cause signal saturation and cannot accurately calculate the number of charges. At present, the existing readout signal processing solutions are not ideal in improving system performance such as dynamic range and resolution, and the industry has not proposed an ideal solution that can improve dynamic range and reduce chip area.

Contents of the invention

In order to solve the above-mentioned technical problems, the present invention provides a high dynamic range MCP detector front-end readout circuit and a readout method thereof, using multiple charge transfer logic (similar to the asynchronous logic successive approximation analog-to-digital conversion based on charge redistribution) device) to provide an ultra-wide dynamic range of the input signal.

The present invention realizes through following technical scheme:

A high dynamic range MCP detector front-end readout circuit, including a signal input module, a dynamic range extension module, a buffer module (AMP), a high-speed comparator module (CMP), a time-to-digital conversion module (TDC) and a logic circuit module ( LOGIC); wherein, the photocurrent signal from the detector enters the front-end readout circuit through the signal input module, and then undergoes integration and dynamic range expansion processing through the dynamic range extension module, and the integrated voltage signal is buffered through the buffer module , then transmitted to the high-speed comparator module, the high-speed comparison module includes the first comparator CMP1 and the second comparator CMP2, the comparison result of the first comparator is converted into a digital signal through the time-to-digital conversion module, and then stored in data, The comparison result of the second comparator generates the switch control signal of the dynamic range expansion module through the logic circuit module.

Further, the signal input module includes two input signal electrodes PAD and TP, wherein PAD is an MCP electron cloud charge collecting electrode, and TP is an input signal electrode for testing, and both are connected to the same output node through a test switch Test .

Further, the dynamic range extension module includes a first sampling capacitor C ₁ , a second sampling capacitor C ₂ , a first switch S ₁ , a second switch S ₂ and a third switch S ₃ ; wherein the first sampling capacitor C ₁ and the second sampling capacitor C ₂ are used for charge storage, one end of C ₁ is connected to the wire ground (GND), the other end is connected to S ₁ , and the node is A; one end of C ₂ is connected to the wire ground, and the other end It is connected with S ₂ together, node B, the other ends of S ₁ and S ₂ are connected to reference potential V _REF , and the two ends of S ₃ are connected to nodes A and B respectively.

Further, the buffer module is a unity-gain amplifier, which adopts an amplifier structure with differential input and single-ended output, and its inverting input terminal and output terminal are connected together so that the closed-loop gain is 1.

Further, the threshold voltages of the first comparator and the second comparator are different; the first comparator is used to determine the arrival time of the input signal; the second comparator is used to determine the saturation state of the front-end readout circuit.

Further, the time-to-digital conversion module includes a coarse counting module and a fine counting module, the coarse counting module is used for roughly counting the arrival time, and the fine counting module is used for detailed counting of the arrival time to improve the resolution, and then The counting result is output to static random access memory (SRAM) for storage.

Further, the logic module includes a combinational logic part composed of an AND gate or an OR gate and a two-phase non-overlapping clock generation part, and calculates the first switch S ₁ and the second switch S 1 according to the output signal of the second comparator. The logical relationship between S ₂ and the control signal of the third switch S ₃ is then returned to the dynamic range expansion module.

The above-mentioned front-end readout circuit of the high dynamic range MCP detector can store the charge in the two integrating capacitors C ₁ and C ₂ according to the logic relationship of the control signals of the three switches S ₁ , S ₂ , and S ₃ (given by the logic module). Shift between them to get a higher dynamic range of the input signal. Specifically, the readout method of the front-end readout circuit of the high dynamic range MCP detector, the specific steps are as follows:

1. In the initial state, the first switch S ₁ and the second switch S ₂ are closed, the third switch S ₃ is opened, and the first sampling capacitor C ₁ and the second sampling capacitor C ₂ are reset to V _REF , the reference voltage V _REF The power supply voltage is 3.3V;

2. When an electron cloud signal is emitted, the emission part of the detection system will generate a start signal: START signal. When the START signal arrives, the circuit starts to start, and the first switch S ₁ and the second switch S ₂ are turned on;

3. The time-to-digital conversion module starts timing after receiving the start signal, and the entire readout circuit waits for the arrival of the electronic cloud signal; when the PAD receives the input charge, the first sampling capacitor C ₁ starts to integrate, and the integrated voltage is transmitted through the buffer module to the high-speed comparator module;

4. The reference voltage V _TH1 of the first comparator CMP1 is the power supply voltage 3.3V. When there is a charge input, the output of the comparator is reversed, and the comparison result is used as the STOP signal of the time-to-digital conversion module to stop timing. The arrival time measured by the digital conversion module is converted into a digital signal and stored in the SRAM memory;

5. The output signal of the buffer module will also be transmitted to the second comparator CMP2, and compared with the reference voltage V _TH2 , to confirm whether the readout circuit is in a saturated state; if the input node voltage is negative, it means that the circuit is in a saturated state. After the saturation state, the second switch S ₂ is turned on, the third switch S ₃ is turned off, and half of the charge in the first sampling capacitor C ₁ is injected into the second sampling capacitor C ₂ , thereby increasing the charge on the first sampling capacitor C ₁ voltage; then the _second switch S2 is turned on, the _third switch S3 is disconnected, the connection between the first sampling capacitor _C1 and the _second sampling capacitor C2 is disconnected, and the _second sampling capacitor C2 is reset and discharged; Judging the charge size of the first sampling capacitor C ₁ again, opening the second switch S ₂ again, closing the third switch S ₃ , and performing charge transfer between the first sampling capacitor C ₁ and the second sampling capacitor C ₂ ; and so on until The circuit is out of saturation, that is, the voltage at the input terminal of the buffer module rises above 0V, and the second comparator CMP2 returns to the initial potential;

6. Turn off the first switch S ₁ , the second switch S ₂ and the third switch S ₃ , the buffer module outputs the integral voltage of the first sampling capacitor C ₁ , and record the times N and the number of discharges of the first sampling capacitor C ₁ The output residual voltage V _s , the total charge released by discharge is Q ₀ , the output residual charge is Q _s =C ₁ V _s , and the total input charge is Q ₀ +Q _s .

Compared with prior art, advantage of the present invention is as follows:

1. Based on the fact that MCP has no dark current (not dark count), combined with the advantages of the high dynamic CMOS image sensor circuit architecture, the readout circuit of the present invention adopts multiple charge transfer logic (similar to the asynchronous logic successive approximation based on charge redistribution) type analog-to-digital converter), which can provide an ultra-wide dynamic range of the input signal.

2. The structure of the dynamic range expansion module adopted in the present invention is simple, only needing to use two capacitors to achieve a larger dynamic range and reduce the pixel area.

3. The system integration is high. The invention puts the determination process of the input signal strength into the pixel for processing, without complicated back-end processing process, simplifies the design process of the back-end circuit, makes the overall chip structure simple, and the pixel The filling ratio is high, and the chip area utilization rate is good.

Description of drawings

Fig. 1 is the structural representation of the conventional MCP detector front-end readout circuit;

Fig. 2 is the structural representation of the MCP detector front-end readout circuit of the present invention;

Fig. 3 is the working timing diagram of the MCP detector front-end readout circuit of the present invention;

Fig. 4 is the transient operating characteristics and simulation results of Embodiment 1 of the present invention;

Detailed ways

The MCP neutron detector readout circuit of the present invention is fully compatible with the 0.18 μm standard CMOS process, and the chip will be described in detail below with reference to the drawings and embodiments.

Example 1

As shown in Figure 2, a high dynamic range MCP detector front-end readout circuit includes a signal input module, a dynamic range extension module, a buffer module (AMP), a high-speed comparator module (CMP), a time-to-digital conversion module (TDC ) and logic circuit module (LOGIC); among them, the photocurrent signal from the detector enters the front-end readout circuit through the signal input module, and then integrates and expands the dynamic range through the dynamic range extension module, and the integrated voltage signal passes through The buffer module performs buffer processing, and then transmits to the high-speed comparator module. The high-speed comparison module includes a first comparator CMP1 and a second comparator CMP2, and the comparison result of the first comparator is converted into a digital signal by a time-to-digital conversion module , and then perform data storage, and the comparison result of the second comparator generates a switch control signal of the dynamic range expansion module through the logic circuit module.

The signal input module includes two input signal electrodes, PAD and TP, wherein PAD is an MCP electron cloud charge collecting electrode, and TP is an input signal electrode for testing, and both are connected to the same output node through a test switch Test. Among them, the signal input module includes two electrodes, PAD and TP, which are the input part of the entire front-end readout circuit, and they are all metal layers defined separately in the CMOS process, which are related to the process.

The dynamic range extension module includes a first sampling capacitor C ₁ , a second sampling capacitor C ₂ , a first switch S ₁ , a second switch S ₂ and a third switch S ₃ ; wherein, the first sampling capacitor C ₁ and The _second sampling capacitor C2 is used for storing charges, and its capacitance is equal. One end of C ₁ is connected to the wire ground (GND), the other end is connected to S ₁ , and the node is A; one end of C ₂ is connected to the wire ground, and the other end is connected to S ₂ , node B, S ₁ and S ₂ One end is connected to the reference potential V _REF , and the two ends of S ₃ are respectively connected to nodes A and B. Both the first switch S ₁ and the second switch S ₂ are used as reset switches of the integrating capacitor, and they adopt a complementary CMOS structure design. In order to further optimize the efficiency of charge transfer, the third switch S ₃ is a Boostrap switch. In order to save area and reduce the influence of parasitic on the capacitance value, both the first sampling capacitor C ₁ and the second sampling capacitor C ₂ adopt MOM capacitor structure.

The buffer module is a unity gain amplifier (AMP), which adopts an amplifier structure with differential input and single-ended output, and its reverse input terminal and output terminal are connected together so that the closed-loop gain is 1.

The amplifier adopts a rail-to-rail amplifier structure, which can directly adopt the circuit structure in "The Essence of Analog Integrated Circuit Design" by Willy Sansen.

The high-speed comparator module compares analog signals to obtain time data and the switch logic relationship of the dynamic range expansion module. It is composed of five-stage Cascade cascaded amplifiers and cross-coupled comparators, wherein the cross-coupled amplifier The structure of P386 in "CMOS Analog Integrated Circuit Design (Second Edition)" by Phillip E. Allen can be directly adopted. The threshold voltages of the first comparator and the second comparator are different; the first comparator is used to determine the arrival time of the input signal; the second comparator is used to determine the saturation state of the front-end readout circuit.

What described time-to-digital conversion module adopted is the operating principle of the vernier method, and it comprises coarse counting module and fine counting module, and what coarse counting module obtains is the counting result of high position, and what fine counting module obtains is the counting result of low position, they jointly A digital signal representing the arrival time is composed, and then output to SRAM for storage.

The logic module includes a combined logic part composed of AND gates and OR gates and a two-phase non-overlapping clock generation part, wherein the AND gates and OR gates are all composed of standard logic units provided by CMOS technology. According to the output signal of the second comparator, the logic relationship of the control signals of the first switch S ₁ , the second switch S ₂ and the third switch S ₃ is calculated, and then returned to the dynamic range extension module.

The working sequence of the present embodiment is shown in Fig. 3, such during the working process:

The system clock used in the present invention is 320MHz. In the initial state, S ₁ and S ₂ are closed, S ₃ is opened, and the two integral capacitors C ₁ and C ₂ are reset to V _REF . In the present invention, the reference voltage V _REF is a power supply voltage of 3.3V. When the starting signal START arrives, the circuit starts to start, and the switches S ₁ and S ₂ are opened. The TDC module starts timing after receiving the start signal, and the entire readout circuit waits for the arrival of the electronic cloud signal. When the PAD receives the input charge, the C ₁ capacitor starts integrating. The integrated voltage is transmitted to the high-speed comparator module through the unity gain amplifier AMP. The reference voltage VTH1 of the arrival time judgment comparator CMP1 is the power supply voltage 3.3V, so as long as there is charge input, the output of the comparator will be reversed. The comparison result is used as the STOP signal of the TDC module to stop timing, during which the arrival time measured by the TDC module is converted into a digital signal and stored in the SRAM memory.

In addition, the output signal of AMP is also transmitted to the input dynamic range comparator CMP2, and compared with the reference voltage VTH ₂ , it is confirmed whether the readout circuit reaches a saturated state. When the number of electron cloud charges received by the PAD is large, the voltage will rapidly drop to a negative value due to the small charging capacitor _C1 , causing the output of the amplifier AMP to be saturated, and the voltage of the AMP input node is 0V. The reference voltage of CMP2 is set to 0V. When the circuit reaches a saturated state, the integral voltage at _C1 is negative, and the output voltage of AMP remains at 0V. At this time, CMP2 turns over. The comparison result generates control signals of S ₂ and S ₃ through the LOGIC module. That is, after entering the saturation state, open S ₂ and close S ₃ to inject half of the charge in C ₁ into C ₂ , thereby increasing the voltage on C ₁ . Then turn _on S2, turn off _S3 , disconnect _C1 and _C2 , and reset and discharge _C2 . Judge the charge of C ₁ again. If the input node voltage is still negative, it means that the circuit is still in a saturated state. Open S ₂ again and close S ₃ to transfer charge between C ₁ and C ₂ . This cycle continues until the circuit is out of saturation, the voltage at the AMP input terminal rises above 0V, and CMP2 returns to the initial potential. Finally, all the switches S ₁ , S ₂ , and S ₃ are turned off, and the buffer module outputs the integrated voltage of C ₁ . Record the discharge times N of the capacitor C ₁ and its output residual voltage V _s (which can be further converted into a digital signal), and then the input charge Q=C ₁ ×(V _REF -V _S )×2 ^N can be obtained.

Fig. 4 is the simulation result of the analog part of the front end of the circuit, the horizontal axis is the simulation time, and the unit is ns. During the simulation, the input charge is set to be 1×10 ⁷ electrons, and the integral capacitors C ₁ and C ₂ in the pixel circuit are both 200fF. According to Q=CV, when the input capacitance of the traditional circuit is 200fF, when the electric charge reaches 4.125×10 ⁶ circuit, the circuit will reach a saturated state. The clock of the whole system is 320MHz, and the interval between two reset signals is 20ns. In order to ensure that the charge will not be lost during the discharge process of _C1 by using _C2 , the control switch signals _of S2 and S3 need to be _two -phase non-overlapping clocks. Since the capacitors C ₁ and C ₂ have the same size, the amount of charge transferred each time should be half of the total amount of input charge. It can be seen from Figure 4 that when the input charge is 10 ⁷ electrons, two discharges are required before the input voltage becomes positive. value. After simulation, it can be seen that the input voltage is finally kept at 1.3838V, and the remaining charging voltage of the capacitor is 2.026V, so the initial charging voltage is 2 ² ×2.013=8.042V (8V under ideal conditions).

Claims (8)

1. A high dynamic range MCP detector front-end readout circuit is characterized in that it comprises a signal input module, a dynamic range extension module, a buffer module, a high-speed comparator module, a time-to-digital conversion module and a logic circuit module; wherein, from The photocurrent signal of the detector enters the front-end readout circuit through the signal input module, and then integrates and expands the dynamic range through the dynamic range expansion module. The integrated voltage signal is buffered by the buffer module and then transmitted to the high-speed comparison Comparator module, described high-speed comparator module comprises the first comparator CMP1 and the second comparator CMP2, the comparison result of the first comparator is converted into digital signal through time digital conversion module, then carries out data storage, the comparison of the second comparator As a result, the switch control signal of the dynamic range expansion module is generated through the logic circuit module. 2. A kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, described signal input module comprises PAD and TP two input signal electrodes, and wherein PAD is MCP electron cloud charge collection electrode, TP is an input signal electrode for testing, and both are connected to the same output node through a test switch Test. 3. A kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, it is characterized in that, described dynamic range extension module comprises first sampling capacitance C ₁ , second sampling capacitance C ₂ , the second A switch S ₁ , a second switch S ₂ and a third switch S ₃ ; wherein, the first sampling capacitor C ₁ and the second sampling capacitor C ₂ are used to store charges, one end of C ₁ is connected to the ground end of the wire, and the other end is connected to the S ₁ is connected together, the node is A; one end of C ₂ is connected to the ground terminal of the wire, the other end is connected with S ₂ , node B, the other end of S ₁ and S ₂ are connected to the reference potential V _REF , both ends of S ₃ connected to nodes A and B respectively. 4. a kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, described buffer module is unity gain amplifier, what adopted is the amplifier structure of differential input single-ended output, its The inverting input is connected to the output for a closed-loop gain of 1. 5. A kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, the threshold voltage of described first comparator and second comparator are different; The first comparator is used for determining input The arrival time of the signal; the second comparator is used to determine the saturation state of the front-end readout circuit. 6. A kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, described time digital conversion module comprises coarse counting module and fine counting module, and coarse counting module is used for arrival time For rough counting, the fine counting module is used for detailed counting of the arrival time to improve resolution, and then the counting results are output to the static random access memory for storage. 7. A kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, described logic module comprises the combined logic part that is made of AND gate, OR gate and two-phase non-overlapping The clock generating part calculates the logic relationship of the control signals of the first switch S ₁ , the second switch S ₂ and the third switch S ₃ according to the output signal of the second comparator, and then returns it to the dynamic range extension module. 8. the readout method of a kind of high dynamic range MCP detector front-end readout circuit as claimed in claim 1, is characterized in that, concrete steps are as follows: 1. In the initial state, the first switch S ₁ and the second switch S ₂ are closed, the third switch S ₃ is opened, and the first sampling capacitor C ₁ and the second sampling capacitor C ₂ are reset to V _REF , the reference voltage V _REF The power supply voltage is 3.3V; 2. When an electronic cloud signal is emitted, the emission part of the detection system will generate a start signal: START signal. When the START signal arrives, the circuit starts to start, and the first switch S ₁ and the second switch S ₂ are turned on; 3. The time-to-digital conversion module starts timing after receiving the start signal, and the entire readout circuit waits for the arrival of the electronic cloud signal; when the PAD receives the input charge, the first sampling capacitor C ₁ starts to integrate, and the integrated voltage is transmitted through the buffer module to the high-speed comparator module; 4. The reference voltage V _TH1 of the first comparator CMP1 is the power supply voltage 3.3V. When there is a charge input, the output of the comparator is reversed, and the comparison result is used as the STOP signal of the time-to-digital conversion module to stop timing. The arrival time measured by the digital conversion module is converted into a digital signal and stored in the SRAM memory; 5. The output signal of the buffer module will also be transmitted to the second comparator CMP2, and compared with the reference voltage V _TH2 , to confirm whether the readout circuit is in a saturated state; if the input node voltage is negative, it means that the circuit is in a saturated state. After the saturation state, the second switch S ₂ is turned on, the third switch S ₃ is turned off, and half of the charge in the first sampling capacitor C ₁ is injected into the second sampling capacitor C ₂ , thereby increasing the charge on the first sampling capacitor C ₁ voltage; then the _second switch S2 is turned on, the _third switch S3 is disconnected, the connection between the first sampling capacitor _C1 and the _second sampling capacitor C2 is disconnected, and the _second sampling capacitor C2 is reset and discharged; Judging the charge size of the first sampling capacitor C ₁ again, opening the second switch S ₂ again, closing the third switch S ₃ , and performing charge transfer between the first sampling capacitor C ₁ and the second sampling capacitor C ₂ ; and so on until The circuit is out of saturation, that is, the voltage at the input terminal of the buffer module rises above 0V, and the second comparator CMP2 returns to the initial potential; 6. Turn off the first switch S ₁ , the second switch S ₂ and the third switch S ₃ , the buffer module outputs the integral voltage of the first sampling capacitor C ₁ , and record the times N and the number of discharges of the first sampling capacitor C ₁ The output residual voltage V _s , the total amount of charge released by each discharge is Q ₀ , the output residual charge is Q _s =C ₁ V _s , and the total input charge is Q ₀ +Q _s .