CN111048540B - A gated pixel unit and 3D image sensor - Google Patents

Abstract

The invention relates to a gate-controlled pixel unit and a 3D image sensor, wherein the gate-controlled pixel unit comprises: the photoelectric conversion and control module is used for converting the received optical signals into voltage signals and obtaining control signals and light intensity information according to the voltage signals; the time-voltage conversion module is used for measuring the time interval information according to the control signal to obtain distance information; the selection output module selects and outputs distance information or light intensity information according to the received selection signal. The gate-controlled pixel unit can be switched between the SPAD working mode and the APD working mode at will by adjusting the bias voltage of the photoelectric conversion and control module so as to realize the measurement of the distance of a target object and the measurement of the illumination intensity reflected by the target object, thereby obtaining the distance information and the light intensity information of the target object.

Description

A gated pixel unit and 3D image sensor

technical field

The invention belongs to the technical field of image sensors, and in particular relates to a gated pixel unit and a 3D image sensor.

Background technique

An image sensor is a semiconductor device that converts an optical signal input from the outside into an electrical signal (ie, performs photoelectric conversion) to provide image information corresponding to the optical signal. Recently, 3D (Three dimensional) image sensors that provide distance information and image information based on optical signals have been proposed. 3D image sensors have important applications in lidar, medical research, artificial intelligence and other fields, and are currently a hot research direction.

Usually, the traditional 3D image sensor realizes three-dimensional imaging through Time of Flight (TOF) method. The test principle is shown in Figure 1. The start signal triggers the laser pulse signal transmitter to emit laser pulses synchronously. After a period of time, the laser pulse reaches the surface of the target object and is reflected back. After a period of time, the laser pulse is received by the sensor chip and generates an end signal. The time interval experienced by this process can be quantified by the sensor chip, that is, the time interval t between the start signal and the end signal in Figure 1, and then the distance information s between the sensor and the target object can be obtained, where c represents the speed of light.

The traditional 3D image sensor pixel unit is mainly composed of a photoelectric conversion device, a time to digital conversion circuit (Time to Digital Converter, TDC for short), and a background light suppression circuit. Its measurement accuracy is mainly determined by the conversion performance of the photoelectric conversion device and the resolution of the TDC. At the same time, because it is easily affected by ambient light and noise caused by hot carriers, a background light suppression circuit is needed to extract the effective photon signal from the noise light signal. It can be seen that the internal circuit structure of the pixel unit of the traditional 3D image sensor is relatively complex, the effective filling rate of the pixel is low, and the pixel area is large, which is not suitable for designing and producing a large-scale pixel array.

Therefore, it is of great significance and application prospect to design a 3D image sensor pixel unit with high filling rate, small area, easy large-scale integration and ambient light suppression function.

Contents of the invention

In order to solve the above problems in the prior art, the present invention provides a gated pixel unit and a 3D image sensor. The technical problem to be solved in the present invention is realized through the following technical solutions:

The present invention provides a gated pixel unit, including: a photoelectric conversion and control module, a time-voltage conversion module and a selection output module, wherein,

The photoelectric conversion and control module is used to convert the received optical signal into a voltage signal, and obtain a control signal and light intensity information according to the voltage signal;

The time-voltage conversion module measures the time interval information according to the control signal to obtain distance information;

The selection output module selects and outputs the distance information or the light intensity information according to the received selection signal.

In one embodiment of the present invention, the photoelectric conversion and control module includes: an AND gate, a NAND gate, a first NMOS transistor, a first PMOS transistor, a first inverter, and an avalanche photodiode, wherein,

The input end of the AND gate receives the first reset signal and the gating signal, and the output end is connected to the first input end of the NAND gate;

The second input terminal of the NAND gate is respectively connected to the drain of the first NMOS transistor and the input terminal of the first inverter, and the output terminal is connected to the time-voltage conversion module;

The gate of the first NMOS transistor receives the gating signal, the source is connected to the cathode of the avalanche photodiode, and the drain is connected to the drain of the first PMOS transistor;

The gate of the first PMOS transistor receives the first reset signal, the source is connected to the reset voltage terminal, and the drain is respectively connected to the input terminal of the first inverter and the selection output module;

The output end of the first inverter is connected to the time-voltage conversion module;

The anode of the avalanche photodiode is connected to the negative voltage terminal.

In an embodiment of the present invention, the time-voltage conversion module includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a second inverter, a first capacitor, and a second capacitor, wherein,

The source of the second PMOS transistor is connected to the voltage terminal, the gate is connected to the first bias voltage terminal, and the drain is connected to the source of the third PMOS transistor;

The gate of the third PMOS transistor is connected to the second bias voltage terminal, and the drain is respectively connected to the source of the fourth PMOS transistor and the source of the fifth PMOS transistor;

The gate of the fourth PMOS transistor is connected to the output terminal of the NAND gate;

The input end of the second inverter is connected to the output end of the NAND gate, and the output end is connected to the gate of the fifth PMOS transistor;

The drain of the fifth PMOS transistor is connected to the ground terminal;

The gate of the second NMOS transistor receives the first capacitor reset signal, the drain is connected to the drain of the third NMOS transistor, and the source is connected to the ground terminal;

The gate of the third NMOS transistor is connected to the output terminal of the first inverter, and the source is respectively connected to the drain of the fourth NMOS transistor and the selection output module;

The gate of the fourth NMOS transistor receives the second capacitor reset signal, and the source is connected to the ground terminal;

The first capacitor is connected in series between the drain of the fourth PMOS transistor and the ground terminal;

The second capacitor is connected in series between the source of the third NMOS transistor and the ground terminal.

In an embodiment of the present invention, the selection output module includes a fifth NMOS transistor, a sixth NMOS transistor and a source follower, wherein,

The gate of the fifth NMOS transistor receives a first selection signal, the source is connected to the drain of the first PMOS transistor, and the drain is connected to the input terminal of the source follower;

The gate of the sixth NMOS transistor receives the second selection signal, the drain is connected to the source of the third NMOS transistor, and the source is connected to the input terminal of the source follower;

The source follower is used to output received pixel information.

In an embodiment of the present invention, the source follower includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor, wherein,

The gate of the sixth PMOS transistor is connected to the third bias voltage terminal, the source is connected to the voltage terminal, and the drain is connected to the source of the seventh PMOS transistor;

The gate of the seventh PMOS transistor receives the column selection signal, and the drain is connected to the source of the eighth PMOS transistor;

The gate of the eighth PMOS transistor is respectively connected to the drain of the fifth NMOS transistor and the source of the sixth NMOS transistor, and the drain is connected to the ground terminal.

In one embodiment of the present invention, a column amplifier is further included, the column amplifier is connected to the output terminal of the source follower, and is used for amplifying and outputting the pixel information.

The present invention provides a 3D image sensor, including a pixel array, a reading output circuit module and a quantization circuit module, wherein,

The pixel array is used to obtain the pixel information of the target object, and the pixel array includes any one of the gated pixel units described in the above embodiments;

The read output circuit module is used to read and output the pixel information one by one in sequence;

The quantization circuit module is used to convert the output pixel information into digital information and output it.

Compared with prior art, the beneficial effect of the present invention is:

1. In the gated pixel unit of the present invention, by adjusting the bias voltage of the photoelectric conversion and control module, the gated pixel unit can be switched arbitrarily between the SPAD working mode and the APD working mode, so as to realize the measurement of the distance to the target object and the measurement of the light intensity reflected by the target object, thereby obtaining the distance information and light intensity information of the target object.

2. The gated pixel unit of the present invention does not have a time-to-digital converter circuit, which can greatly reduce the area of the pixel unit, thereby greatly reducing its power consumption, which is beneficial to the integrated design of large-scale pixel arrays.

3. The 3D image sensor of the present invention uses the gated pixel unit to measure the distance of the target object through the gated ranging method, and can only control the 3D image sensor to be in the ON state within a short time interval within a measurement cycle, so that the 3D image sensor is in the OFF state at other times, which greatly reduces the interference of dark counts on the measurement results.

The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following special examples are given.

Description of drawings

Fig. 1 is a schematic diagram of a time-of-flight ranging method provided by an embodiment of the present invention;

Fig. 2 is a schematic diagram of a gated ranging method provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a gated pixel unit provided by an embodiment of the present invention;

Fig. 4 is a voltage-current characteristic curve diagram of an avalanche photodiode provided by an embodiment of the present invention;

FIG. 5 is a circuit diagram of a gated pixel unit provided by an embodiment of the present invention;

FIG. 6 is a timing diagram of mode switching of a gated pixel unit provided by an embodiment of the present invention;

FIG. 7 is a working timing diagram of a gated pixel unit in a SPAD working mode provided by an embodiment of the present invention.

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, a gated pixel unit and a 3D image sensor proposed according to the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

The aforementioned and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of specific implementations with accompanying drawings. Through the description of the specific implementation, the technical means and functions adopted by the present invention to achieve the intended purpose can be understood more deeply and specifically. However, the attached drawings are only for reference and description, and are not used to limit the technical solution of the present invention.

Embodiment one

Please refer to Fig. 2, Fig. 2 is a principle diagram of a gated distance measurement method provided by the embodiment of the present invention. As shown in the figure, the time information and distance obtained in the TOF distance measurement method are in one-to-one correspondence. Assume that the total distance to be measured is S, and the corresponding total time interval to be measured is T. The time interval can be divided into N parts, that is, T ₁ , T ₂ , ..., T _N-1 , _TN in the figure, and the distances corresponding to each time interval are S ₁ , S ₂ , ..., S _N-1 , S _N . Assuming that in a certain measurement period, it is necessary to measure whether the 3D image sensor receives the laser pulse signal within the time interval of T _i (1≤i≤N), then it is only necessary to control the to /> The 3D image sensor is in the off state during the rest of the measurement period and does not respond to the laser pulse signal. Then, if the 3D image sensor receives photons within the T _i time interval, it will generate an end signal, that is, the distance between the target object and the 3D image sensor is /> If the 3D image sensor does not receive photons within the T _i time interval, no end signal will be generated, and the 3D image sensor is controlled to be turned on only within the T _i+1 time interval in the next measurement period, and is turned off at other times, and the above steps are repeated until the distance between the target object and the 3D image sensor is measured.

This embodiment proposes a gated pixel unit applied to a 3D image sensor based on the gated ranging method. Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of a gated pixel unit provided by an embodiment of the present invention. As shown in the figure, the gated pixel unit of this embodiment includes: a photoelectric conversion and control module 1, a time-voltage conversion module 2, and a selection output module 3, wherein the photoelectric conversion and control module 1 is used to convert the received optical signal into a voltage signal, and obtain a control signal and light intensity information according to the voltage signal; The control signal measures the time interval information to obtain distance information; the selection output module 3 selects and outputs the distance information or the light intensity information according to the received selection signal.

In this embodiment, the optical signal includes the laser echo signal and the ambient light signal. The photoelectric conversion and control module 1 completes the conversion from the optical signal to the voltage signal through the avalanche photodiode. At the same time, it can adjust the bias voltage of the avalanche photodiode anode to make it work in APD (photodiode) mode, and then obtain the light intensity information of the target object. It can also adjust the bias voltage of the avalanche photodiode. Further, the distance information of the target object is obtained, and the selection output module 3 realizes a selection function, and controls the output to switch between the distance information and the light intensity information.

In this embodiment, the avalanche photodiode is installed in the photoelectric conversion and control module 1 as a photoelectric converter. Please refer to FIG. 4 . FIG. 4 is a voltage-current characteristic curve of an avalanche photodiode provided by an embodiment of the present invention. It can be seen from the figure that the avalanche photodiode works in different modes due to different applied reverse bias voltages. When the reverse bias voltage is small, the device works in APD mode, and the reverse current generated is proportional to the light intensity; when the reverse bias voltage is near the avalanche breakdown voltage but lower than the breakdown voltage, the device absorbs a photon to excite a limited number of electron-hole pairs, and the device works in a linear mode, which has a linear amplification effect on photogenerated carriers and has a limited gain; when the reverse bias voltage is greater than the avalanche breakdown voltage, the device works in Geiger mode (Geiger mode), in which a single photon can trigger an APD avalanche The avalanche current is generated, and the avalanche gain is theoretically infinite. Therefore, the avalanche photodiode in the Geiger mode is called a single photon avalanche diode (SPAD), and the Geiger mode is also called the SPAD mode.

Specifically, the specific circuit diagram of the gated pixel unit in this embodiment is shown in FIG. 5 . FIG. 5 is a circuit diagram of a gated pixel unit provided in an embodiment of the present invention. It can be seen from the figure that the photoelectric conversion and control module 1 includes: AND gate U₁, NAND gate U₂, the first NMOS transistor NM1, the first PMOS transistor PM1, the first inverter I₁and the avalanche photodiode Diode, where, the AND gate U₁The input terminal receives the first reset signal RST and the gating signal TRN, and the output terminal is connected to the NAND gate U₂The first input terminal of NAND gate U₂The second input end of the first NMOS transistor NM1 is respectively connected to the drain of the first inverter I₁The input end of the first NMOS transistor NM1 is connected to the time-voltage conversion module 2; the gate of the first NMOS transistor NM1 receives the gating signal TRN, the source is connected to the cathode of the avalanche photodiode Diode, and the drain is connected to the drain of the first PMOS transistor PM1; the gate of the first PMOS transistor PM1 receives the first reset signal RST, the source is connected to the reset voltage terminal Vex, and the drain is respectively connected to the first inverter I₁The input terminal and selection output module 3; the first inverter I₁The output terminal of the avalanche photodiode Diode is connected to the negative voltage terminal Vsub.

In this embodiment, the avalanche photodiode Diode is used as a photoelectric converter to convert the received optical signal into a voltage signal. The negative voltage terminal Vsub provides a bias voltage for the anode of the avalanche photodiode Diode, and the reset voltage terminal Vex provides a bias voltage for the cathode of the avalanche photodiode Diode. By adjusting the voltage of the negative voltage terminal Vsub, the avalanche photodiode Diode can be operated in APD mode or SPAD mode. The first reset signal RST is used to reset the avalanche photodiode Diode to SPAD mode. The gating signal TRN is used to control the opening position of the gating window, and determine the time interval of measurement in the gating ranging method, so that the first NMOS transistor NM1 is turned on within the time interval of measurement.

Further, the time-voltage conversion module 2 includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a second inverter I₂, the first capacitor C1 and the second capacitor C2, wherein the source of the second PMOS transistor PM2 is connected to the voltage terminal VDD, the gate is connected to the first bias voltage terminal Vb1, and the drain is connected to the source of the third PMOS transistor PM3; the gate of the third PMOS transistor PM3 is connected to the second bias voltage terminal Vb2, and the drain is respectively connected to the source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5; the gate of the fourth PMOS transistor PM4 is connected to the NAND gate U₂The output terminal of the second inverter I₂The input terminal is connected to the NAND gate U₂the output terminal of the fifth PMOS transistor PM5; the drain of the fifth PMOS transistor PM5 is connected to the ground terminal GND; the gate of the second NMOS transistor NM2 receives the first capacitor reset signal RST_1, the drain is connected to the drain of the third NMOS transistor NM3, and the source is connected to the ground terminal GND; the gate of the third NMOS transistor NM3 is connected to the first inverter I₁The output terminal and source of the fourth NMOS transistor NM4 are respectively connected to the drain of the fourth NMOS transistor NM4 and the selection output module 3; the gate of the fourth NMOS transistor NM4 receives the reset signal RST_2 of the second capacitor, and the source is connected to the ground terminal GND; the first capacitor C1 is connected in series between the drain of the fourth PMOS transistor PM4 and the ground terminal GND; the second capacitor C2 is connected in series between the source of the third NMOS transistor NM3 and the ground terminal GND.

In this embodiment, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 constitute a pair of current sources with cascode structure, which are used to charge the first capacitor C1, and control the charging time of the first capacitor C1 according to the control signal output by the NAND gate _U2 , so as to realize fine time quantification. , and then obtain accurate distance information of the target object. The first bias voltage terminal Vb1 and the second bias voltage terminal Vb2 provide gate bias voltages for the second PMOS transistor PM2 and the third PMOS transistor PM3 respectively. The first capacitor reset signal RST_1 is used to control the reset of the first capacitor C1, and the second capacitor reset signal RST_2 is used to control the reset of the first capacitor C2.

Further, the selection output module 3 includes a fifth NMOS transistor NM5, a sixth NMOS transistor NM6 and a source follower 301, wherein the gate of the fifth NMOS transistor NM5 receives the first selection signal SEL1, the source is connected to the drain of the first PMOS transistor PM1, and the drain is connected to the input terminal of the source follower 301; the gate of the sixth NMOS transistor NM6 receives the second selection signal SEL2, the drain is connected to the source of the third NMOS transistor NM3, and the source is connected to the source follower The input terminal of 301; the source follower 301 is used to output the received pixel information. Specifically, the source follower 301 includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, wherein the gate of the sixth PMOS transistor PM6 is connected to the third bias voltage terminal Vb3, the source is connected to the voltage terminal VDD, and the drain is connected to the source of the seventh PMOS transistor PM7; the gate of the seventh PMOS transistor PM7 receives the column selection signal COL, and the drain is connected to the source of the eighth PMOS transistor PM8; the gate of the eighth PMOS transistor PM8 is respectively connected to the drain of the fifth NMOS transistor NM5 and the source and drain of the sixth NMOS transistor NM6 are connected to the ground terminal GND.

In this embodiment, the first selection signal SEL1 controls the conduction of the fifth NMOS transistor NM5 to output the light intensity information, and the second selection signal SEL2 controls the conduction of the sixth NMOS transistor NM6 to output the distance information. The light intensity information and the distance information are output to subsequent circuits through the source follower 301 as pixel information. During the working process of the 3D image sensor, the pixel information of each pixel unit in the pixel array is selected and output according to the column selection signal COL. In other embodiments of the present invention, the gated pixel unit further includes a column amplifier 4 connected to the output terminal of the source follower 301 for amplifying and outputting the pixel information.

The gated pixel unit proposed based on the gated ranging method in this embodiment can be switched between the SPAD working mode and the APD working mode arbitrarily by adjusting the bias voltage of the avalanche photodiode Diode in the photoelectric conversion and control module 1, so as to realize the measurement of the distance to the target object and the measurement of the light intensity reflected back by the target object, thereby obtaining the distance information and light intensity information of the target object. At the same time, there is no need for a time-to-digital converter circuit inside the gated pixel unit, so the area of the pixel unit can be greatly reduced, so that its power consumption is also greatly reduced, which is beneficial to the integrated design of large-scale pixel arrays.

The working principle of the gated pixel unit in this embodiment is as follows. Please refer to FIG. 6. FIG. 6 is a mode switching timing diagram of a gated pixel unit provided by the embodiment of the present invention. As shown in the figure, the switching between the SPAD working mode and the APD working mode is realized by adjusting the negative voltage terminal Vsub of the avalanche photodiode Diode, and at the same time, the first selection signal SEL1 and the second selection signal SEL2 need to be controlled to switch the output path. When the pixel unit is in the SPAD working mode, the first selection signal SEL1 is at a low level, the fifth NMOS transistor NM5 is not turned on, the second selection signal SEL2 is at a high level, and the sixth NMOS transistor NM6 is turned on, then the measurement information in the SPAD working mode is output, that is, the measurement information on the distance of the target object. When the pixel unit is in the APD working mode, the second selection signal SEL2 is at a low level, the sixth NMOS transistor NM6 is not turned on, the first selection signal SEL1 is at a high level, and the fifth NMOS transistor NM5 is turned on, then the measurement information in the APD working mode is output, that is, the measurement information of the light intensity of the target object. Please refer to FIG. 7 . FIG. 7 is a working timing diagram of a gated pixel unit in the SPAD working mode according to an embodiment of the present invention. As shown in the figure, before the gated pixel unit works, the first capacitor C1 and the second capacitor C2 are reset by the first capacitor reset signal RST_1 and the second capacitor reset signal RST_2 respectively, so that the charges stored on the first capacitor C1 and the second capacitor C2 become zero. After the reset is completed, the voltages on the first capacitor C1 and the second capacitor C2 are both zero. When it is necessary to measure the distance information of the target object, adjust the voltage of the negative voltage terminal Vsub to make the avalanche photodiode Diode work in Geiger mode, and then start to measure. The LASER signal is the laser pulse signal emitted by the laser pulse signal transmitter, which represents the beginning of a measurement cycle. The gating signal TRN becomes effective after a delay of a period of time after the LASER signal is emitted, and is used to control the opening position of the gating window. NM1 is turned on, and when the gating signal TRN becomes effective high level, the first reset signal RST becomes low level, so that the first PMOS transistor PM1 is turned on. At this time, the total voltage drop at both ends of the positive and negative electrodes of the avalanche photodiode Diode is Vex+Vsub, so that the avalanche photodiode Diode works in the Geiger mode, that is, the SPAD mode. Then the first reset signal RST quickly recovers to a high level, so that the first PMOS transistor PM1 is turned off. At this time, the gating signal TRN is still at a high level, so the first NMOS transistor NM1 is still in a conducting state. At the same time, the first reset signal RST and the gating signal TRN pass through the AND gate _U1 . The START signal output by the AND gate _U1 is at a high level. The cascode current source charges the first capacitor C1. If the avalanche photodiode Diode receives photons during the period when the gating signal TRN is at a high level (that is, during the measurement period), then due to the avalanche multiplication effect, a large avalanche current will be generated on the avalanche photodiode Diode, causing the node FD to discharge to a low level. Since the node FD becomes a low-level signal, the signal of the node Φ becomes a high-level signal, and the current source of the cascode structure stops charging the first capacitor C1, and at the same time, the low-level signal of the node FD becomes a high-level signal through the first inverter to control the conduction of the third NMOS transistor NM3, so that when a photon is detected, the second capacitor C2 shares the charge on the first capacitor C1 and stores valid information on the second capacitor C2. Finally, at the end of the measurement cycle, the first capacitor reset signal RST1 generates a high-level signal to The charge on the first capacitor C1 is released to zero, and the reset is completed.

When it is necessary to measure the light intensity information of the target object, the avalanche photodiode Diode works in APD mode by adjusting the voltage of the negative voltage terminal Vsub to generate a limited photoelectric conversion gain. At this time, the light intensity and photocurrent have a linear relationship, that is, the greater the light intensity reflected by the object, the greater the photocurrent.

During a measurement period described above, if the first selection signal SEL1 received by the selection output module 3 is valid, the fifth NMOS transistor NM5 is turned on, and the voltage of the negative voltage terminal Vsub is adjusted to make the avalanche photodiode Diode work in the APD mode, and the light intensity information obtained by measurement is output; distance information.

It is worth noting that each time interval in the gated ranging method needs to be measured multiple times, so as to further suppress the influence of the ambient light signal and make the measurement result more accurate. Through multiple measurements at the same time interval, the voltage stored on the second capacitor C2 can be approximated to the average value of the voltage on the first capacitor C1 in multiple measurements. Finally, after the measurement of each time interval is finished, the second selection SEL2 signal is set to a high level, so that the sixth NMOS transistor NM6 is turned on, and the voltage on the second capacitor C2 is output through the source follower 301 composed of the sixth PMOS transistor PM6, the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8, and the voltage on the second capacitor C2 can be quantified by a subsequent quantization circuit to obtain finer time division and higher time resolution.

Embodiment two

This embodiment provides a 3D image sensor, including a pixel array, a reading output circuit module and a quantization circuit module, wherein the pixel array is used to obtain pixel information of a target object, and the pixel array includes several gated pixel units described in Embodiment 1, and the several gated pixel units form an n*n two-dimensional array; the read output circuit module is used to read and output the pixel information one by one in sequence; the quantization circuit module is used to convert the output pixel information into digital information and output it. The circuits of the reading output circuit module and the quantization circuit module are similar to those of traditional image sensors, and will not be repeated here.

The 3D image sensor of this embodiment measures the target object based on the gated ranging method. In one measurement period, it is only necessary to control the 3D image sensor to be in the on state within a short time interval, and to be in the off state during other time periods, which can effectively reduce the interference of the ambient light signal to the 3D image sensor when receiving effective laser echo signals.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. A gate-controlled pixel cell, comprising: a photoelectric conversion and control module (1), a time-voltage conversion module (2) and a selection output module (3), wherein,

the photoelectric conversion and control module (1) is used for converting a received optical signal into a voltage signal and obtaining a control signal and light intensity information according to the voltage signal;

the time-voltage conversion module (2) measures time interval information according to the control signal to obtain distance information;

the selection output module (3) selects and outputs the distance information or the light intensity information according to the received selection signal;

wherein the photoelectric conversion and control module (1) comprises: AND gate (U) ₁ ) NAND gate (U) ₂ ) A first NMOS tube (NM 1), a first PMOS tube (PM 1), a first inverter (I) ₁ ) And avalanche photodiodes (Diode), wherein,

said AND gate (U) ₁ ) The input end of the (C) is used for receiving a first Reset Signal (RST) and a gate control signal (TRN), and the output end is connected with the NAND gate (U) ₂ ) Is connected to the first input terminal of the first circuit;

the NAND gate (U) ₂ ) Is connected to the drain of the first NMOS tube (NM 1) and the first inverter (I) ₁ ) The output end of the power supply is connected with the time-voltage conversion module (2);

the grid electrode of the first NMOS tube (NM 1) receives the gate control signal (TRN), the source electrode is connected with the cathode of the avalanche photodiode (Diode), and the drain electrode is connected with the drain electrode of the first PMOS tube (PM 1);

the grid electrode of the first PMOS tube (PM 1) receives the first Reset Signal (RST), the source electrode is connected with a reset voltage end (Vex), and the drain electrodes are respectively connected with the first inverter (I) ₁ ) And said selection output module (3);

the first inverter (I ₁ ) The output end of the (C) is connected with the time-voltage conversion module (2);

an anode of the avalanche photodiode (Diode) is connected to a negative voltage terminal (Vsub).

2. The gate-controlled pixel unit according to claim 1, wherein the time-voltage conversion module (2) comprises a second PMOS transistor (PM 2), a third PMOS transistor (PM 3), a fourth PMOS transistor (PM 4), a fifth PMOS transistor (PM 5), a second NMOS transistor (NM 2), a third NMOS transistor (NM 3), a fourth NMOS transistor (NM 4), a second inverter (I) ₂ ) A first capacitance (C1) and a second capacitance (C2), wherein,

the source electrode of the second PMOS tube (PM 2) is connected with a voltage end (VDD), the grid electrode of the second PMOS tube is connected with a first bias voltage end (Vb 1), and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube (PM 3);

the grid electrode of the third PMOS tube (PM 3) is connected with a second bias voltage end (Vb 2), and the drain electrode of the third PMOS tube (PM 4) is respectively connected with the source electrode of the fifth PMOS tube (PM 5);

the grid electrode of the fourth PMOS tube (PM 4) is connected with the NAND gate (U) ₂ ) An output terminal of (a);

the second inverter (I ₂ ) Is connected to the input of the NAND gate (U) ₂ ) The output end of the fifth PMOS tube (PM 5) is connected with the grid electrode of the fifth PMOS tube;

the drain electrode of the fifth PMOS tube (PM 5) is connected with a ground end (GND);

the grid electrode of the second NMOS tube (NM 2) receives a first capacitance reset signal (RST_1), the drain electrode of the second NMOS tube (NM 3) is connected with the drain electrode, and the source electrode of the second NMOS tube is connected with the ground end (GND);

the grid electrode of the third NMOS tube (NM 3) is connected with the first phase inverter (I) ₁ ) The source electrode of the second NMOS tube (NM 4) is respectively connected with the drain electrode of the second NMOS tube (NM 4) and the selection output module (3);

the grid electrode of the fourth NMOS tube (NM 4) receives a second capacitance reset signal (RST_2), and the source electrode is connected with the ground end (GND);

the first capacitor (C1) is connected in series between the drain electrode of the fourth PMOS tube (PM 4) and the grounding end (GND);

the second capacitor (C2) is connected in series between the source of the third NMOS tube (NM 3) and the ground terminal (GND).

3. Gating pixel cell according to claim 2, wherein the selection output module (3) comprises a fifth NMOS transistor (NM 5), a sixth NMOS transistor (NM 6) and a source follower (301), wherein,

the grid electrode of the fifth NMOS tube (NM 5) receives a first selection signal (SEL 1), the source electrode of the fifth NMOS tube (NM 5) is connected with the drain electrode of the first PMOS tube (PM 1), and the drain electrode of the fifth NMOS tube is connected with the input end of the source follower (301);

the grid electrode of the sixth NMOS tube (NM 6) receives a second selection signal (SEL 2), the drain electrode of the sixth NMOS tube (NM 3) is connected with the source electrode of the third NMOS tube, and the source electrode of the sixth NMOS tube is connected with the input end of the source follower (301);

the source follower (301) is configured to output the received pixel information.

4. A gate-controlled pixel cell according to claim 3, wherein the source follower (301) comprises a sixth PMOS transistor (PM 6), a seventh PMOS transistor (PM 7) and an eighth PMOS transistor (PM 8), wherein,

the grid electrode of the sixth PMOS tube (PM 6) is connected with a third bias voltage end (Vb 3), the source electrode of the sixth PMOS tube is connected with the voltage end (VDD), and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube (PM 7);

the grid electrode of the seventh PMOS tube (PM 7) receives a column selection signal (COL), and the drain electrode of the seventh PMOS tube (PM 8) is connected with the source electrode of the eighth PMOS tube;

the grid electrode of the eighth PMOS tube (PM 8) is respectively connected with the drain electrode of the fifth NMOS tube (NM 5) and the source electrode of the sixth NMOS tube (NM 6), and the drain electrode is connected with the grounding end (GND).

5. A gate-controlled pixel cell according to claim 3, further comprising a column amplifier (4), the column amplifier (4) being connected to the output of the source follower (301) for amplifying and outputting the pixel information.

6. A3D image sensor is characterized by comprising a pixel array, a reading output circuit module and a quantization circuit module, wherein,

the pixel array is used for acquiring pixel information of a target object, and comprises a plurality of gate-controlled pixel units according to any one of claims 1-5;

the reading output circuit module is used for reading and outputting the pixel information one by one in sequence;

the quantization circuit module is used for converting the output pixel information into digital information and outputting the digital information.