CN112885849B - Display panel and display device - Google Patents

Abstract

The present invention provides a display panel and a display device. The display panel includes a flexible substrate and a thin film transistor layer disposed on the flexible substrate; wherein a positively charged first semiconductor layer is disposed between the flexible substrate and the thin film transistor layer. In the present invention, a positively charged first semiconductor layer is disposed between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel the diffusion of positively charged impurity particles in the flexible substrate , so that it cannot enter the interface between the polysilicon in the thin film transistor layer and the gate insulating layer, thereby effectively improving the temperature instability effect of the negative bias voltage of the thin film transistor layer.

Description

Display panel and display device

technical field

The present invention relates to the field of display technology, and in particular, to a display panel and a display device.

Background technique

Due to the simple circuit process and low price of P-type MOS (Metal-Oxide-Semiconductor, metal-oxide-semiconductor) transistors, it is widely used in TFT (Thin Film Transistor, thin film) of LTPS (Low Temperature Poly-Silicon, low temperature polysilicon). transistor) device. In the actual use process, due to the influence of gate electric field and ambient temperature, the absolute value of the threshold voltage of the TFT device will increase, the carrier mobility will decrease, the transconductance will decrease, and the on-state current will decrease, that is, NBTI (Negative Bias Temperature Instability, Negative Bias Temperature Instability) effect, NBTI effect is an important reason for the failure of TFT devices.

In the prior art, a flexible substrate is usually used as the substrate substrate of a bendable display panel. It is found through experiments that the NBTI effect of a TFT device using a flexible substrate is more significant than that of a glass substrate TFT device. According to the current research, the main reason for the NBTI effect is that the silicon-hydrogen bond (Si-H) on the polysilicon surface breaks under the action of gate voltage and high temperature, and the H atom escapes, resulting in the dangling bond of Si and the formation of the interface. traps, resulting in the NBTI effect. When a flexible substrate is used, the positive ions in the flexible substrate diffuse to the interface between the polysilicon and the gate insulating layer under the action of the gate electric field, and are trapped by the interface traps, which will aggravate the occurrence of the NBTI effect and lead to TFT Device failure. Therefore, it is necessary to improve this defect.

SUMMARY OF THE INVENTION

The embodiment of the present invention provides a display panel, which is used to solve the problem that the flexible substrate is used as the substrate substrate in the display panel in the prior art, but the positive ions in the flexible substrate will diffuse to the thin film transistor layer, resulting in the failure of the thin film transistor layer. technical issues.

An embodiment of the present invention provides a display panel, comprising a flexible substrate and a thin film transistor layer disposed on the flexible substrate; wherein a positively charged transistor is disposed between the flexible substrate and the thin film transistor layer the first semiconductor layer.

In the display panel provided by the embodiment of the present invention, the display panel further includes a barrier layer provided on the flexible substrate, and a first buffer layer provided on the barrier layer, wherein the first buffer layer is A semiconductor layer is provided between the barrier layer and the first buffer layer.

In the display panel provided by the embodiment of the present invention, the display panel further includes a barrier layer provided on the flexible substrate, a first buffer layer provided on the barrier layer, and a first buffer layer provided on the first buffer layer. A second buffer layer above the buffer layer, wherein the first semiconductor layer is provided between the first buffer layer and the second buffer layer.

In the display panel provided by the embodiment of the present invention, the display panel further includes a second semiconductor layer, and the second semiconductor layer is provided between the barrier layer and the first buffer layer.

In the display panel provided by the embodiment of the present invention, the second semiconductor layer is positively charged.

In the display panel provided by the embodiment of the present invention, the display panel further includes a power supply line, and the first semiconductor layer is electrically connected to the power supply line through a first via hole.

In the display panel provided by the embodiment of the present invention, the thin film transistor layer is a P-type metal oxide semiconductor transistor layer.

In the display panel provided by the embodiment of the present invention, the first semiconductor layer is a P-type semiconductor layer.

In the display panel provided by the embodiment of the present invention, the P-type semiconductor layer is doped with boron ions.

An embodiment of the present invention further provides a display device, including the above-mentioned display panel.

Beneficial effects: In a display panel and a display device provided by the embodiments of the present invention, by arranging a positively charged first semiconductor layer between the flexible substrate and the thin film transistor layer, the positively charged first semiconductor layer can repel the The diffusion of positively charged impurity particles in the flexible substrate prevents them from entering the interface between the polysilicon and the gate insulating layer in the thin film transistor layer, thereby effectively improving the negative bias temperature instability effect of the thin film transistor layer .

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments.

FIG. 1 is a schematic diagram of a basic structure of a display panel according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the basic structure of another display panel provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of the basic structure of another display panel provided by an embodiment of the present invention.

FIG. 4 is a schematic diagram of the basic structure of still another display panel provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, for clarity and ease of understanding and description, the dimensions and thicknesses of components depicted in the drawings are not to scale.

As shown in FIG. 1 , a schematic diagram of a basic structure of a display panel provided by an embodiment of the present invention, the display panel includes a flexible substrate 10 and a thin film transistor layer 20 disposed on the flexible substrate 10; wherein, the A positively charged first semiconductor layer 30 is disposed between the flexible substrate 10 and the thin film transistor layer 20 .

It should be noted that the flexible substrate 10 is an organic thin film composed of carbon, hydrogen and other elements, such as polyimide. Polyimide is mainly synthesized from dibasic anhydrides and dibasic amines. It has excellent mechanical properties and dielectric properties, and can maintain flexibility and bendability.

It should be noted that the thin film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, a layer Inter-insulating layer 206, source/drain metal layer 207. The active layer 201 includes an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is located on the flexible substrate 10 and covers the active layer 201; the first gate insulating layer 202 A gate layer 203 is located on the first gate insulating layer 202; the second gate insulating layer 204 is located on the first gate insulating layer 202 and covers the first gate layer 203; The second gate layer 205 is located on the second gate insulating layer 204 ; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205 ; The source/drain metal layer 207 is located on the interlayer insulating layer 206 and is electrically connected to the p-channel 2012 of the active layer 201 through via holes, which penetrate through the interlayer insulating layer. Layer 206 , the second gate insulating layer 204 and part of the first gate insulating layer 202 , the source/drain metal layer 207 includes a source electrode 2071 and a drain electrode 2072 .

In an embodiment, the second gate layer 205 is AC grounded. In this embodiment of the present invention, a second gate layer is provided between the first gate layer 203 and the source/drain metal layer 207 205 , which can play an electrostatic shielding role and reduce the parasitic capacitance between the first gate layer 203 and the source/drain metal layer 207 .

In one embodiment, the thin film transistor layer 20 is a P-type metal oxide semiconductor transistor layer. It can be understood that, the P-type metal oxide semiconductor transistor layer transmits current by the flow of holes. Wherein, when no power is applied, there is no conduction between the source electrode 2071 and the drain electrode 2072; when a sufficient positive voltage is applied to the source electrode 2071 (the first gate layer 203 is grounded) , the surface of the n-type substrate 2011 under the first gate layer 203 presents a p-type inversion layer, which becomes a channel connecting the source electrode 2071 and the drain electrode 2072 . That is, by controlling the voltage difference between the source electrode 2071 and the first gate layer 203 , the on or off of the P-type metal oxide semiconductor transistor layer can be controlled.

It can be understood that because the P-type metal oxide semiconductor transistor layer is the n-type substrate 2011, the majority carriers are electrons and the minority carriers are holes, corresponding to the source/drain metal layer. The doping type of the contact region of 207 is p-type (ie, p-channel 2012), so the working condition of the p-type metal oxide semiconductor transistor layer is relative to the source electrode on the first gate layer 203 2071 applies a negative voltage, that is, negatively charged electrons are applied to the first gate layer 203. If the display panel is in a high temperature environment at this time, it will cause a negative bias temperature instability (NBTI) effect, namely The absolute value of the threshold voltage of the thin film transistor layer 20 increases, the carrier mobility decreases, the transconductance decreases, and the on-state current decreases, resulting in the failure of the thin film transistor layer 20 .

Specifically, after applying negative bias voltage and temperature stress to the thin film transistor layer 20, the following electrochemical reaction model occurs at the interface of Si and SiO ₂ in the thin film transistor layer 20 and in the oxide layer: this model assumes a certain Substance Y diffuses to the interface of Si and SiO ₂ and reacts electrochemically with the Si-H bond to generate an interface state Si≡Si and an unknown substance X, Si≡SiH+Y→Si≡Si+X, namely The silicon-hydrogen bond (Si-H) breaks under the action of gate voltage and high temperature, and the H atom escapes, resulting in the dangling bond of Si and the formation of interface traps.

In conclusion, the interface defect of Si and SiO ₂ is the main reason for the failure of the thin film transistor layer 20 . Specifically, the thin film transistor layer 20 fails due to the generation and passivation of positive charges during the NBTI effect, that is, the formation of interface states (interface traps). Among them, under the high temperature negative gate voltage, the holes of the inversion layer of the thin film transistor layer 20 are thermally excited and pass through the interface of Si and SiO ₂ . Due to the existence of a large number of Si-H bonds at the interface, the thermal excitation The hole and the Si-H bond act under certain conditions to generate H atoms, H ⁺ or H-containing substances, thereby leaving Si dangling bonds at the interface, and due to the H atoms, H ⁺ or H-containing substances. Instability, H atoms, H ⁺ or H-containing substances will diffuse away from the interface of the active layer 201 to the interface of the first gate layer 203 , thereby generating interface defects and positive charges. In addition, due to the generation of positive charges at the interface defects of SiO ₂ , the number of majority carriers (holes) in the inversion layer will be reduced, and the generation of positive charges in SiO ₂ will form an electric field opposite to the gate voltage. The electric field, which will impair the performance of the thin film transistor layer 20 (eg, increase in absolute value of threshold voltage, decrease in carrier mobility, decrease in transconductance, decrease in on-state current, etc.), will cause the thin film to accumulate over time. Transistor layer 20 fails.

By treating the surface of the active layer 201 to replace the silicon-hydrogen (Si-H) bond with a silicon-fluorine (Si-F) bond or a silicon-deuterium (Si-D) bond, the silicon-hydrogen bond (Si-H) can be improved. H) breaks under the action of gate voltage and high temperature, H atoms escape, and dangling bonds of Si are generated, forming interface traps, resulting in the negative bias temperature instability (NBTI) effect. Specifically, it is because the bonding force between fluorine or deuterium and silicon atoms is stronger, and it is not easy to break. However, if the flexible substrate 10 is used as the base substrate of the display panel, the flexible substrate 10 will also decompose to generate positive ions under the influence of gate voltage and high temperature, which will diffuse in the direction of the thin film transistor layer 20, The negative bias temperature instability (NBTI) effect is further exacerbated. In this embodiment of the present invention, by disposing a positively charged first semiconductor layer 30 between the flexible substrate 10 and the thin film transistor layer 20, the positively charged first semiconductor layer 30 can repel the flexible substrate The diffusion of positively charged impurity particles in 10 prevents them from entering the interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving the negative bias temperature of the thin film transistor layer 20 Instability (NBTI) effects.

In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. That is, the first semiconductor layer 30 is an impurity semiconductor whose hole concentration is much higher than that of free electrons. The method for forming the first semiconductor layer 30 is as follows: pure silicon crystals are doped with trivalent elements to replace the positions of silicon atoms in the crystal lattice, thereby forming a P-type semiconductor. Among them, holes are mainly provided by impurity atoms, and free electrons are formed by thermal excitation. The more impurity atoms are doped, the higher the concentration of multi-subs (holes) and the stronger the electrical conductivity.

In one embodiment, the P-type semiconductor layer is doped with boron ions. In the embodiment of the present invention, the first semiconductor layer 30 is heavily doped with boron ions to make it a P-type semiconductor. The heavily doped P-type semiconductor layer contains a plurality of positive charge centers, which can repel all The diffusion of positively charged impurity particles in the flexible substrate 10 prevents them from entering the interface between the active layer 201 and the first gate insulating layer 202 , thereby effectively improving the thin film transistor layer 20 . Negative Bias Temperature Instability (NBTI) Effect.

It should be noted that the P-type semiconductor layer is doped with boron ions, and these boron ions form a plurality of positive charge centers in the P-type semiconductor layer, but due to the high-temperature activation process, these boron ions will interact with surrounding silicon atoms. Tightly bonded with no diffusion with gate electric field.

In an embodiment, the display panel further includes a barrier layer 40 provided on the flexible substrate 10 and a first buffer layer 50 provided on the barrier layer 40, wherein the first buffer layer 50 The semiconductor layer 30 is provided between the barrier layer 40 and the first buffer layer 50 . The functions of the barrier layer 40 and the first buffer layer 50 are both to prevent the intrusion of water and oxygen in the external environment from causing the thin film transistor layer 20 to fail.

In one embodiment, a planarization layer 208 is provided on the interlayer insulating layer 206 and the source/drain metal layer 207 , and a pixel definition layer 209 is provided on the planarization layer 208 . The function of the planarization layer 208 is to eliminate the height difference between the interlayer insulating layer 206 and the source/drain metal layer 207, and the pixel definition layer 209 is to define the pixel area for subsequent preparation. The organic light-emitting material forms a light-emitting functional layer (not shown). Wherein, the method for preparing the organic light-emitting material is inkjet printing or evaporation.

Next, please refer to FIG. 2 , which is a schematic diagram of the basic structure of another display panel provided by an embodiment of the present invention. The display panel includes a flexible substrate 10 , a thin film transistor layer 20 disposed on the flexible substrate 10 , and a flexible substrate 10 . A positively charged first semiconductor layer 30 between the flexible substrate 10 and the thin film transistor layer 20 .

The display panel further includes a power line 2073, and the first semiconductor layer 30 is electrically connected to the power line 2073 through a first via hole.

It should be noted that the flexible substrate 10 is an organic thin film composed of carbon, hydrogen and other elements, such as polyimide. Polyimide is mainly synthesized from dibasic anhydrides and dibasic amines. It has excellent mechanical properties and dielectric properties, and can maintain flexibility and bendability.

It should be noted that the thin film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, a layer Inter-insulating layer 206, source/drain metal layer 207. The active layer 201 includes an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is located on the flexible substrate 10 and covers the active layer 201; the first gate insulating layer 202 A gate layer 203 is located on the first gate insulating layer 202; the second gate insulating layer 204 is located on the first gate insulating layer 202 and covers the first gate layer 203; The second gate layer 205 is located on the second gate insulating layer 204 ; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205 ; The source/drain metal layer 207 is located on the interlayer insulating layer 206 and is electrically connected to the p-channel 2012 of the active layer 201 through via holes, which penetrate through the interlayer insulating layer. Layer 206 , the second gate insulating layer 204 and part of the first gate insulating layer 202 , the source/drain metal layer 207 includes a source electrode 2071 and a drain electrode 2072 .

It can be understood that the power supply line 2073 provides a positive potential for the display panel. In the embodiment of the present invention, the first semiconductor layer 30 is electrically connected to the power supply line 2073 through a first via hole, so that the first semiconductor layer 30 is electrically connected to the power supply line 2073. A semiconductor layer 30 is positively charged, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10 so that they cannot enter the interface between the active layer 201 and the first gate insulating layer 202 , thereby effectively improving the negative bias temperature instability (NBTI) effect of the thin film transistor layer 20 .

In one embodiment, the power supply line 2073 may be prepared in the same layer as the source/drain metal layer 207 of the thin film transistor layer 20 .

In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. Wherein, the P-type semiconductor layer is doped with boron ions. In the embodiment of the present invention, on the basis that the first semiconductor layer 30 is electrically connected to the power supply line 2073 through the first via hole, the first semiconductor layer 30 is further heavily doped with boron ions, so that it becomes P-type semiconductor, the heavily doped P-type semiconductor layer contains a plurality of positively charged centers, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10 and prevent them from entering the active The interface between the layer 201 and the first gate insulating layer 202 further improves the negative bias temperature instability (NBTI) effect of the thin film transistor layer 20 .

Next, please refer to FIG. 3 , which is a schematic diagram of the basic structure of yet another display panel provided by an embodiment of the present invention. The display panel includes a flexible substrate 10 , a thin film transistor layer 20 disposed on the flexible substrate 10 , and a flexible substrate 10 . A positively charged first semiconductor layer 30 between the flexible substrate 10 and the thin film transistor layer 20 .

The display panel further includes a barrier layer 40 disposed on the flexible substrate 10 , a first buffer layer 50 disposed on the barrier layer 40 , and a first buffer layer 50 disposed on the first buffer layer 50 . The second buffer layer 60 , wherein the first semiconductor layer 30 is provided between the first buffer layer 50 and the second buffer layer 60 .

In an embodiment, the first buffer layer 50 is made of silicon nitride material, and the second buffer layer 60 is made of silicon oxide compound material.

It should be noted that water vapor in the external environment is also one of the causes of the NBTI effect. Trying to reduce the content of water vapor in the display panel can also reduce the NBTI effect. In the embodiment of the present invention, by disposing the first buffer layer 50 and the second buffer layer 60 on the flexible substrate 10 , the diffusion of water vapor can be effectively prevented.

Next, please refer to FIG. 4 , which is a schematic diagram of the basic structure of yet another display panel provided by an embodiment of the present invention. The display panel includes a flexible substrate 10 , a barrier layer 40 disposed on the flexible substrate 10 , a barrier layer 40 disposed on the flexible substrate 10 , and a A first buffer layer 50 on the barrier layer 40 , a second buffer layer 60 on the first buffer layer 50 , and between the first buffer layer 50 and the second buffer layer 60 . The first semiconductor layer 30 in between, and the thin film transistor layer 20 disposed on the second buffer layer 60 .

Wherein, the display panel further includes a second semiconductor layer 70 disposed between the barrier layer 40 and the first buffer layer 50 .

In one embodiment, the second semiconductor layer 70 is positively charged. It can be understood that the second semiconductor layer 70 is positively charged, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10, so that they cannot enter the active layer 201 and the first gate insulating layer. 202 interface, thereby further improving the negative bias temperature instability (NBTI) effect of the thin film transistor layer 20 .

An embodiment of the present invention further provides a display device, including a driving chip and the above-mentioned display panel. The display device provided by the embodiment of the present invention may be a product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital camera, and a navigator.

To sum up, the embodiments of the present invention provide a display panel and a display device. By arranging a positively charged first semiconductor layer between a flexible substrate and a thin film transistor layer, the positively charged first semiconductor layer It can repel the diffusion of positively charged impurity particles in the flexible substrate, so that they cannot enter the interface between the polysilicon and the gate insulating layer in the thin film transistor layer, thereby effectively improving the negative bias temperature instability of the thin film transistor layer. It solves the technical problem that the flexible substrate is used as the base substrate in the display panel in the prior art, but the positive ions in the flexible substrate will diffuse to the thin film transistor layer, resulting in the failure of the thin film transistor layer.

A display panel and a display device provided by the embodiments of the present invention are described above in detail. It should be understood that the exemplary embodiments described herein should be regarded as descriptive only, and are used to help understand the method and the core idea of the present invention, but not to limit the present invention.

Claims (10)

1. The display panel is characterized by comprising a flexible substrate and a thin film transistor layer arranged on the flexible substrate;

and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer.

2. The display panel of claim 1, further comprising a barrier layer disposed over the flexible substrate, a first buffer layer disposed over the barrier layer, wherein the first semiconductor layer is disposed between the barrier layer and the first buffer layer.

3. The display panel of claim 1, further comprising a barrier layer disposed over the flexible substrate, a first buffer layer disposed over the barrier layer, a second buffer layer disposed over the first buffer layer, wherein the first semiconductor layer is disposed between the first buffer layer and the second buffer layer.

4. The display panel of claim 3, further comprising a second semiconductor layer disposed between the barrier layer and the first buffer layer.

5. The display panel according to claim 4, wherein the second semiconductor layer is positively charged.

6. The display panel according to claim 2 or 3, wherein the display panel further comprises a power supply line, and the first semiconductor layer is electrically connected to the power supply line through a first via hole.

7. The display panel of claim 1, wherein the thin-film transistor layer is a P-type metal-oxide-semiconductor transistor layer.

8. The display panel according to claim 7, wherein the first semiconductor layer is a P-type semiconductor layer.

9. The display panel according to claim 8, wherein the P-type semiconductor layer is doped with boron ions.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.

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