CN112885849A - Display panel and display device - Google Patents
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- CN112885849A CN112885849A CN202110127089.8A CN202110127089A CN112885849A CN 112885849 A CN112885849 A CN 112885849A CN 202110127089 A CN202110127089 A CN 202110127089A CN 112885849 A CN112885849 A CN 112885849A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000010409 thin film Substances 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims description 21
- 229910052796 boron Inorganic materials 0.000 claims description 8
- -1 boron ions Chemical class 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 20
- 239000012535 impurity Substances 0.000 abstract description 17
- 239000002245 particle Substances 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 231
- 239000002184 metal Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000005527 interface trap Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 150000008064 anhydrides Chemical class 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910052805 deuterium Inorganic materials 0.000 description 2
- 150000004985 diamines Chemical class 0.000 description 2
- 238000003487 electrochemical reaction Methods 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical compound [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a display panel and a display device. The display panel comprises a flexible substrate and a thin film transistor layer arranged on the flexible substrate; and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer. According to the invention, the positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel the diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter the interface between the polycrystalline silicon in the thin film transistor layer and the grid insulation layer, and the negative bias temperature instability effect of the thin film transistor layer is effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
Since the P-type MOS (Metal-Oxide-Semiconductor) Transistor has a simple circuit process and a Low price, it is widely used in a Thin Film Transistor (TFT) device of LTPS (Low Temperature polysilicon). In the actual use process, due to the influence of the gate electric field, the ambient Temperature and other factors, the absolute value of the threshold voltage of the TFT device is increased, the carrier mobility is reduced, the transconductance is reduced, and the on-state current is reduced, that is, the NBTI (Negative Bias Temperature Instability) effect is an important cause of the TFT device failure.
In the prior art, a flexible substrate is usually adopted as a substrate base plate of a bendable display panel, and experiments show that the NBTI effect of the TFT device adopting the flexible substrate is more remarkable than that of the TFT device adopting a glass substrate. According to the current research, the main reason causing the NBTI effect is that silicon-hydrogen bonds (Si-H) on the surface of the polycrystalline silicon are broken under the action of gate voltage and high temperature, H atoms escape, Si dangling bonds are generated, interface traps are formed, and the NBTI effect is caused. When the flexible substrate is adopted, positive ions in the flexible substrate are diffused to the interface of the polycrystalline silicon and the grid insulating layer under the action of a grid electric field and are captured by an interface trap, so that the NBTI effect is aggravated, and the TFT device is caused to lose efficacy. Therefore, it is necessary to improve this defect.
Disclosure of Invention
The embodiment of the invention provides a display panel, which is used for solving the technical problem that in the display panel in the prior art, a flexible substrate is used as a substrate, but positive ions in the flexible substrate can be diffused to a thin film transistor layer, so that the thin film transistor layer fails.
The embodiment of the invention provides a display panel, which comprises a flexible substrate and a thin film transistor layer arranged on the flexible substrate; and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a barrier layer disposed on the flexible substrate, and a first buffer layer disposed on the barrier layer, wherein the first semiconductor layer is disposed between the barrier layer and the first buffer layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a barrier layer disposed on the flexible substrate, a first buffer layer disposed on the barrier layer, and a second buffer layer disposed on the first buffer layer, wherein the first semiconductor layer is disposed between the first buffer layer and the second buffer layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a second semiconductor layer, and the second semiconductor layer is disposed between the barrier layer and the first buffer layer.
In the display panel provided by the embodiment of the invention, the second semiconductor layer is positively charged.
In the display panel provided by the embodiment of the invention, the display panel further includes a power line, and the first semiconductor layer is electrically connected to the power line through the first via hole.
In the display panel provided in the embodiment of the invention, the thin film transistor layer is a P-type metal oxide semiconductor transistor layer.
In the display panel provided in the embodiment of the invention, the first semiconductor layer is a P-type semiconductor layer.
In the display panel provided by the embodiment of the invention, the P-type semiconductor layer is doped with boron ions.
The embodiment of the invention also provides a display device which comprises the display panel.
Has the advantages that: according to the display panel and the display device provided by the embodiment of the invention, the positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel the diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter the interface between polycrystalline silicon in the thin film transistor layer and the grid insulation layer, and the negative bias temperature instability effect of the thin film transistor layer is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.
Fig. 1 is a schematic diagram of a basic structure of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the size and thickness of components illustrated in the drawings are not to scale for clarity and ease of understanding and description.
As shown in fig. 1, a basic structure of a display panel according to an embodiment of the present invention includes a flexible substrate 10, a thin-film transistor layer 20 disposed on the flexible substrate 10; a positively charged first semiconductor layer 30 is disposed between the flexible substrate 10 and the thin-film transistor layer 20.
The flexible substrate 10 is an organic thin film made of carbon, hydrogen, or the like, such as polyimide. The polyimide is mainly synthesized from dicarboxylic anhydride and diamine, has excellent mechanical property and dielectric property, and can keep flexibility and flexibility.
It should be noted that the thin-film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, an interlayer insulating layer 206, and a source/drain metal layer 207. Wherein the active layer 201 comprises an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is positioned above the flexible substrate 10 and covers the active layer 201; the first gate layer 203 is located over the first gate insulating layer 202; the second gate insulating layer 204 is located over the first gate insulating layer 202 and covers the first gate layer 203; the second gate layer 205 is located over the second gate insulating layer 204; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205; the source/drain metal layer 207 is disposed on the interlayer insulating layer 206 and electrically connected to the p-channel 2012 of the active layer 201 through a via hole, the via hole penetrates through the interlayer insulating layer 206, the second gate insulating layer 204 and a portion of the first gate insulating layer 202, and the source/drain metal layer 207 includes a source 2071 and a drain 2072.
In an embodiment, the second gate layer 205 is ac grounded, and the embodiment of the invention may perform an electrostatic shielding function by disposing the second gate layer 205 between the first gate layer 203 and the source/drain metal layer 207, so as to reduce a parasitic capacitance between the first gate layer 203 and the source/drain metal layer 207.
In one embodiment, the thin-film transistor layer 20 is a P-type metal oxide semiconductor transistor layer. It is understood that the P-type metal oxide semiconductor transistor layer is used for transmitting current by the flowing of holes. Wherein, when not powered, the source 2071 and the drain 2072 are not conductive; when a sufficient positive voltage is applied to the source 2071 (the first gate layer 203 is grounded), a p-type inversion layer is formed on the surface of the n-type substrate 2011 under the first gate layer 203, which becomes a channel connecting the source 2071 and the drain 2072. That is, the P-type metal oxide semiconductor transistor layer can be turned on or off by controlling a voltage difference between the source 2071 and the first gate layer 203.
It is understood that, since the pmos transistor layer is an n-type substrate 2011, the majority carriers are electrons, the minority carriers are holes, and the doping type of the contact region corresponding to the source/drain metal layer 207 is P-type (i.e., P-channel 2012), the operating condition of the pmos transistor layer is that a negative voltage is applied on the first gate layer 203 relative to the source 2071, i.e., negative charge electrons are applied on the first gate layer 203, and when the display panel is in a high temperature environment, a Negative Bias Temperature Instability (NBTI) effect is caused, which may cause an increase in the absolute value of the threshold voltage of the thin-film transistor layer 20, a decrease in the carrier mobility, a decrease in transconductance, and a decrease in the on-state current, resulting in a failure of the thin-film transistor layer 20.
Specifically, after applying negative bias and temperature stress to the thin-film transistor layer 20, the thin-film transistor layerSi and SiO in the tube layer 202The following electrochemical reaction model occurs at the interface and within the oxide layer: this model assumes that some species Y diffuses into Si and SiO2The interface and Si-H bond are subjected to electrochemical reaction to generate an interface state Si ≡ Si & and an unknown substance X, Si ≡ SiH + Y → Si ≡ Si ● + X, namely, a silicon-hydrogen bond (Si-H) is broken under the effects of gate voltage and high temperature, H atoms are escaped, a dangling bond of Si is generated, and an interface trap is formed.
In summary, Si and SiO2Is the primary cause of failure of thin-film-transistor layer 20. Specifically, the thin-film transistor layer 20 fails due to the generation and passivation of positive charges, i.e., the formation of interface states (interface traps), during the NBTI effect. Wherein, under high temperature and negative grid pressure, the cavity of the inversion layer of the thin film transistor layer 20 is thermally excited and tunnels to Si and SiO2Due to the presence of a large number of Si-H bonds at the interface, the thermally excited holes react with the Si-H bonds under certain conditions to form H atoms, H+Or a substance containing H, thereby leaving a dangling bond of Si at the interface, and H atoms, H+Or instability of H-containing substances, H atoms, H+Or the H-containing substance diffuses away from the interface of the active layer 201 toward the interface of the first gate layer 203, thereby generating interface defects and positive charges. In addition, SiO2Will result in a reduction of the number of majority carriers (holes) in the inversion layer due to the generation of positive charges, SiO2The generation of positive charges in (b) will create an electric field opposite to the gate voltage electric field, which may impair the performance of the thin-film transistor layer 20 (e.g., increase in absolute value of threshold voltage, decrease in carrier mobility, decrease in transconductance, decrease in on-state current, etc.), and over time, may cause the thin-film transistor layer 20 to fail.
By treating the surface of the active layer 201 and replacing silicon-hydrogen (Si-H) bonds with silicon-fluorine (Si-F) bonds or silicon-deuterium (Si-D) bonds, the silicon-hydrogen bonds (Si-H) can be improved to be broken under the gate voltage and high temperature, H atoms escape, Si dangling bonds are generated, interface traps are formed, and therefore the Negative Bias Temperature Instability (NBTI) effect is caused. Specifically, the fluorine or deuterium has a stronger bonding force with a silicon atom and is not easily broken. However, if the flexible substrate 10 is used as a substrate of a display panel, the flexible substrate 10 may also be decomposed and generate positive ions under the influence of a gate voltage and a high temperature, and the positive ions may diffuse in the direction of the thin-film transistor layer 20, which further aggravates a Negative Bias Temperature Instability (NBTI) effect. In the embodiment of the present invention, the positively charged first semiconductor layer 30 is disposed between the flexible substrate 10 and the thin film transistor layer 20, and the positively charged first semiconductor layer 30 can repel diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter an interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving a Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. That is, the first semiconductor layer 30 is an impurity semiconductor having a hole concentration much greater than a free electron concentration. The method for forming the first semiconductor layer 30 includes: and doping trivalent elements into the pure silicon crystal to replace the bits of the silicon atoms in the crystal lattice so as to form the P-type semiconductor. The holes are mainly provided by impurity atoms, free electrons are formed by thermal excitation, the more impurity atoms are doped, the higher the concentration of majority (holes) is, and the stronger the conductivity is.
In one embodiment, the P-type semiconductor layer is doped with boron ions. In the embodiment of the invention, boron ions are adopted to heavily dope the first semiconductor layer 30 to form a P-type semiconductor, and the heavily doped P-type semiconductor layer contains a plurality of positive electric centers, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter the interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
The P-type semiconductor layer is doped with boron ions, which form a plurality of positive electric centers in the P-type semiconductor layer, but due to the high-temperature activation process, the boron ions are tightly bonded to surrounding silicon atoms and are not diffused by the gate electric field.
In one embodiment, the display panel further includes a barrier layer 40 disposed on the flexible substrate 10, and a first buffer layer 50 disposed on the barrier layer 40, wherein the first semiconductor layer 30 is disposed between the barrier layer 40 and the first buffer layer 50. Barrier layer 40 and first buffer layer 50 both function to prevent water and oxygen from penetrating from the external environment and causing thin-film transistor layer 20 to fail.
In one embodiment, a planarization layer 208 is disposed on the interlayer insulating layer 206 and the source/drain metal layer 207, and a pixel defining layer 209 is disposed on the planarization layer 208. The planarization layer 208 functions to eliminate a height difference between the interlayer insulating layer 206 and the source/drain metal layer 207, and the pixel defining layer 209 functions to define a pixel region for subsequent preparation of an organic light emitting material to form a light emitting function layer (not shown). The method for preparing the organic luminescent material is ink-jet printing or evaporation.
Referring to fig. 2, a basic structure of another display panel according to an embodiment of the present invention is shown, where the display panel includes a flexible substrate 10, a thin film transistor layer 20 disposed on the flexible substrate 10, and a positively charged first semiconductor layer 30 disposed between the flexible substrate 10 and the thin film transistor layer 20.
The display panel further includes a power line 2073, and the first semiconductor layer 30 is electrically connected to the power line 2073 through a first via hole.
The flexible substrate 10 is an organic thin film made of carbon, hydrogen, or the like, such as polyimide. The polyimide is mainly synthesized from dicarboxylic anhydride and diamine, has excellent mechanical property and dielectric property, and can keep flexibility and flexibility.
It should be noted that the thin-film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, an interlayer insulating layer 206, and a source/drain metal layer 207. Wherein the active layer 201 comprises an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is positioned above the flexible substrate 10 and covers the active layer 201; the first gate layer 203 is located over the first gate insulating layer 202; the second gate insulating layer 204 is located over the first gate insulating layer 202 and covers the first gate layer 203; the second gate layer 205 is located over the second gate insulating layer 204; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205; the source/drain metal layer 207 is disposed on the interlayer insulating layer 206 and electrically connected to the p-channel 2012 of the active layer 201 through a via hole, the via hole penetrates through the interlayer insulating layer 206, the second gate insulating layer 204 and a portion of the first gate insulating layer 202, and the source/drain metal layer 207 includes a source 2071 and a drain 2072.
It can be understood that, the power line 2073 provides a positive potential for the display panel, and the embodiment of the invention electrically connects the first semiconductor layer 30 to the power line 2073 through the first via hole, so that the first semiconductor layer 30 is constantly positively charged, which can repel the diffusion of the positively charged impurity particles in the flexible substrate 10 and make them unable to enter the interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
In one embodiment, the power line 2073 may be fabricated in the same layer as the source/drain metal layer 207 of the thin-film transistor layer 20.
In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. Wherein the P-type semiconductor layer is doped with boron ions. In the embodiment of the present invention, on the basis that the first semiconductor layer 30 is electrically connected to the power line 2073 through the first via hole, boron ions are further adopted to heavily dope the first semiconductor layer 30 to form a P-type semiconductor, and the heavily doped P-type semiconductor layer contains a plurality of positive electrical centers, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter the interface between the active layer 201 and the first gate insulating layer 202, thereby further improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
Referring to fig. 3, a basic structure of another display panel according to an embodiment of the present invention is shown, where the display panel includes a flexible substrate 10, a thin film transistor layer 20 disposed on the flexible substrate 10, and a positively charged first semiconductor layer 30 disposed between the flexible substrate 10 and the thin film transistor layer 20.
The display panel further includes a barrier layer 40 disposed on the flexible substrate 10, a first buffer layer 50 disposed on the barrier layer 40, and a second buffer layer 60 disposed on the first buffer layer 50, wherein the first semiconductor layer 30 is disposed between the first buffer layer 50 and the second buffer layer 60.
In one embodiment, the first buffer layer 50 is made of a silicon nitride material, and the second buffer layer 60 is made of a silicon oxide material.
It should be noted that moisture in the external environment is also one of the causes of the NBTI effect, and the NBTI effect can be reduced by trying to reduce the content of moisture in the display panel. In the embodiment of the present invention, the first buffer layer 50 and the second buffer layer 60 are disposed on the flexible substrate 10, so that the diffusion of water vapor can be effectively prevented.
Referring to fig. 4, a basic structure of another display panel according to an embodiment of the present invention is shown, where the display panel includes a flexible substrate 10, a barrier layer 40 disposed on the flexible substrate 10, a first buffer layer 50 disposed on the barrier layer 40, a second buffer layer 60 disposed on the first buffer layer 50, a first semiconductor layer 30 disposed between the first buffer layer 50 and the second buffer layer 60, and a thin film transistor layer 20 disposed on the second buffer layer 60.
Wherein the display panel further comprises a second semiconductor layer 70, and the second semiconductor layer 70 is disposed between the barrier layer 40 and the first buffer layer 50.
In one embodiment, the second semiconductor layer 70 is positively charged. It is understood that the second semiconductor layer 70 is positively charged, which can repel the diffusion of the positively charged impurity particles in the flexible substrate 10 from entering the interface between the active layer 201 and the first gate insulating layer 202, thereby further improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
The embodiment of the invention also provides a display device which comprises the driving chip and the display panel. The display device provided by the embodiment of the invention can be as follows: products or components with display functions such as mobile phones, tablet computers, televisions, displays, notebook computers, digital cameras, navigators and the like.
In summary, according to the display panel and the display device provided in the embodiments of the present invention, the positively charged first semiconductor layer is disposed between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter an interface between polysilicon in the thin film transistor layer and the gate insulating layer, thereby effectively improving a negative bias temperature instability effect of the thin film transistor layer, and solving a technical problem that in a display panel in the prior art, positive ions in the flexible substrate can diffuse into the thin film transistor layer, which causes failure of the thin film transistor layer, because the flexible substrate is used as the substrate.
The display panel and the display device provided by the embodiments of the present invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely illustrative for facilitating understanding of the method of the present invention and its core ideas, and not restrictive.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110127089.8A CN112885849B (en) | 2021-01-29 | 2021-01-29 | Display panel and display device |
Applications Claiming Priority (1)
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