CN112865561B - A diode-clamped back-to-back bridgeless three-level rectifier - Google Patents

Abstract

A diode-clamped back-to-back bridgeless three-level rectifier comprises a power supply inductor series branch; a bidirectional transistor connected in parallel with the power supply inductor branch; a bidirectional transistor connected in series with the power supply inductor branch; The midpoint voltage of the series capacitor is clamped by a diode bank. The three-level rectifier loop is composed of 4 fully-controlled power switch tubes, 6 common diodes, and 2 polar capacitors. Compared with traditional two-level rectifier circuits, the voltage stress requirements on circuit components are reduced. When the rectifier circuit works, there are no more than three semiconductor devices, and the circuit operation loss is small; only one switch tube needs to be changed for the circuit operation mode switching, which effectively reduces the circuit switching loss. The DC bus is operated by two capacitors in series, which effectively reduces the output current ripple.

Description

A diode-clamped back-to-back bridgeless three-level rectifier

technical field

The invention relates to the technical field of single-phase three-level active rectifiers, in particular to a diode-clamped back-to-back bridgeless three-level rectifier.

Background technique

The power factor correction circuit can improve the power factor of the electrical equipment and reduce the reactive power generated by the equipment. The flow of reactive power in the power grid will inevitably increase the loss of electric energy transmission in the power grid, thereby causing economic losses. In order to reduce the reactive power input by the load side to the power grid and isolate the high-order harmonics in the power grid that are harmful to the electrical equipment, more and more targeted power electronic devices are put into the electrical equipment. At the same time, adding power electronic devices to electrical equipment can effectively solve these harmful high-order harmonics. Diode clamped back-to-back bridgeless three-level rectifier The bidirectional tube three-level rectifier can maintain a stable voltage to the load output under the condition of high power factor, and is suitable for many occasions. Compared with traditional two-level rectifiers, three-level rectifiers have smaller ripple levels; less device voltage stress; better power factor and power density.

SUMMARY OF THE INVENTION

The invention provides a diode-clamped back-to-back bridgeless three-level rectifier, which reduces the voltage stress requirement on circuit elements compared with the traditional two-level rectifier circuit. By clamping the mid-point of the series capacitor by the diode, the voltage stress on the switch tube is reduced, and the cost of the switch tube is reduced; when two polar capacitors are used in series, the capacitor voltage is reduced; the semiconductor device flowing through the rectifier circuit works No more than 3, the circuit operating loss is small; only one switch tube needs to be changed to switch the circuit operating mode, which effectively reduces the circuit switching loss. The DC bus is operated by two capacitors in series, which effectively reduces the output current ripple.

The technical scheme adopted in the present invention is:

A diode-clamped back-to-back bridgeless three-level rectifier, comprising:

Switch tubes S ₁ , S ₂ , S ₃ , S ₄ , diodes D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , inductance L, capacitors C ₁ , C ₂ ;

One side of the AC power supply is connected to one end of the inductor L, and the other end of the inductor L is respectively connected to the drain _of the switch S1, the anode _of the diode D1, and the cathode of the diode D2 _;

_The other side of the AC power supply is respectively connected to the drain of the switch S2, the source _of the switch S3, and the drain of the switch S4 _;

_The source of the switch tube S1 is connected to the source of the switch tube S2 _;

The cathode of the diode D1 is respectively connected to the cathode of the diode _D3 and _one end of the capacitor _C1 ;

_The anode of the diode D2 is respectively connected to the anode of the diode D4 and the other end of the capacitor _{C2 ;}

_The drain of the switch tube S3 is respectively connected to the anode of the diode _D3 and the cathode of the diode D5 _;

_The source of the switch tube S4 is respectively connected to the cathode of the diode _D4 and the anode of the diode D6 _;

_The other end of the capacitor _C1 is respectively connected to the anode of the diode D5, the cathode of the diode D6, and one end of the capacitor _{C2 ;}

_Two ends of the load R are respectively connected to _one end of the capacitor C1 and the other end of the capacitor C2.

Among them, 4 fully controlled power switches: S ₁ , S ₂ , S ₃ , S ₄ , 6 common diodes: D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , these switching devices and diodes composed of a diode clamp circuit.

A back-to-back branch composed of inductor L, switch tubes S ₁ and S ₂ .

A single-phase three-level arrangement structure is composed of semiconductor bidirectional switches S ₃ , S ₄ , diodes D ₁ , D ₂ , D ₃ , D ₄ , and capacitors C ₁ and C ₂ connected in series.

The diode clamping structure is composed of diode groups D ₅ and D ₆ .

The output-side parallel voltage-stabilizing branch is composed of capacitors C ₁ and C ₂ in series.

The rectifier circuit of the present invention consists of semiconductor bidirectional switches S ₁ , S ₂ , S ₃ , S ₄ , D ₅ , D ₆ ; rectifier diodes D ₁ , D ₂ , D ₃ , D ₄ and their parallel capacitors C ₁ , C ₂ composed.

The rectifier loop included in the three-level rectifier circuit of the present invention is improved from the traditional single-phase three-level rectifier bridge, and a bridgeless back-to-back bidirectional switch circuit tube construction circuit method is introduced.

The rectifier circuit included in the rectifier circuit is improved from the traditional back-to-back bridgeless rectifier bridge, and a set of clamping diodes is added at the midpoint of the series capacitor to clamp the midpoint voltage of the series capacitor group.

The rectifier circuit charges the two diode clamping capacitors respectively through the conversion of the working mode to stabilize the output voltage of the DC side, and the input end has three voltage levels of rectifier circuits.

The rectifier circuit adds a back-to-back switch tube structure to the traditional bridgeless rectifier structure, has no reverse recovery problem of the body diode of the switch tube, and has the advantages of high reliability and high efficiency.

Due to the working characteristics of the power frequency alternating grid voltage, in order to ensure the stability of the output voltage of the three-level rectifier circuit, it is necessary to adjust different working modes in different grid voltage ranges:

1) Mode 1: The switches S ₁ , S ₂ , and S ₃ are turned off, S ₄ is turned on, and the diodes D ₁ and D ₄ work in the on state, and the loop flows through the capacitors C ₁ , C ₂ , at this time the grid voltage u _s < U _dc . Since the current on the inductor L cannot change abruptly, the capacitors C ₁ and C ₂ clamp the voltage at the load end to U _dc , and the inductor L will generate a balanced voltage to make u _ab =U _dc . At this time, the inductor releases energy, the current on the inductor L decreases, and the capacitors C ₁ and C ₂ are charged.

2) Mode 2: the switches S ₁ , S ₂ , and S ₄ are turned off, and S ₃ is turned on. When the diodes D ₁ and D ₅ work in a conducting state, the loop flows through the capacitor C ₁ . When the grid voltage u _s <+U _dc /2, since the current on the inductor L cannot be abruptly changed, the capacitor C ₁ clamps the voltage at the ab end to U _dc /2, and a balanced voltage will be generated on the inductor L so that u _ab = U _dc /2. At this time, the inductor releases energy, the current on the inductor L decreases, the capacitor C ₁ is charged, and the capacitor C ₂ is discharged; when the grid voltage us _s >+U _dc /2, since the current on the inductor L cannot change abruptly, the capacitor C ₁ will The voltage at the ab end is clamped on U _dc /2, and a balanced voltage will be generated on the inductor L to make u _ab =U _dc /2. At this time, the inductor absorbs energy, the current on the inductor L increases, the capacitor _C1 is charged, and the capacitor _C2 is discharged.

3) Mode 3: the switches S ₃ and S ₄ are both turned off, and S ₁ and S ₂ are turned on. All diodes in the circuit are cut off, and there is no power channel between the grid and the load. At this time, the grid voltage is 0<u _s <+U _dc /2. Since the current on the inductor L cannot change abruptly, the capacitors C ₁ and C ₂ clamp the voltage at the load end on U _dc , and the inductor L will generate a balanced voltage to make u _ab =0. At this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitors C ₁ and C ₂ discharge.

4) Mode 4: the switches S ₁ , S ₂ , and S ₄ are turned off and S ₃ is turned on. The diodes D ₂ and D ₃ work in the on state, and the loop flows through the capacitors C ₁ and C ₂ . At this time, the grid voltage u _s <-U _dc /2. Since the current on the inductor L cannot change abruptly, the capacitors C ₁ and C ₂ clamp the voltage at the load end to U _dc , and the inductor L will generate a balanced voltage so that -u _ab =U _dc . At this time, the inductor releases energy, the current on the inductor L decreases, and the capacitors C ₁ and C ₂ are charged.

5) Mode 5: the switches S ₁ , S ₂ , and S ₃ are turned off, and S ₄ is turned on. When the diodes D ₂ and D ₆ work in a conducting state, the loop flows through the capacitor C ₂ . When the grid voltage u _s >-U _dc /2, since the current on the inductor L cannot be abruptly changed, the capacitor C ₂ clamps the voltage at the ab end to U _dc /2, and the inductor L will generate a balanced voltage to make -u _ab =U _dc /2. At this time, the inductor releases energy, the current on the inductor L decreases, the capacitor C ₂ is charged, and the capacitor C ₁ is discharged; when the grid voltage u _s <-U _dc /2, since the current on the inductor L cannot change abruptly, the capacitor C ₂ will The voltage of the ab terminal is clamped on U _dc /2, and a balanced voltage will be generated on the inductor L so that -u _ab =U _dc /2. At this time, the inductor absorbs energy, the current on the inductor L increases, the capacitor C ₂ is charged, and the capacitor C ₁ is discharged.

6) Mode 6: the switches S ₃ and S ₄ are both turned off, and S ₁ and S ₂ are turned on. All diodes in the circuit are cut off, and there is no power channel between the grid and the load. At this time, the grid voltage is 0<u _s <-U _dc /2. Since the current on the inductor L cannot change abruptly, the capacitors C ₁ and C ₂ clamp the voltage at the load end on U _dc , and the inductor L will generate a balanced voltage to make u _ab =0. At this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitors C ₁ and C ₂ discharge.

By changing the state of the switch tube, the capacitor on the DC bus side can be charged and discharged to stabilize the DC side voltage in an ideal state. The conversion of each working mode follows the PWM (pulse distribution adjustment) to the mode of the circuit and the working time through the selection. For the proposed circuit, in the positive half cycle of the power grid, the circuit has three voltage levels: U _dc , U _dc /2, and 0, which correspond to mode 1, mode 2, and mode 3 respectively:

A diode-clamped back-to-back bridgeless three-level rectifier of the present invention has the following technical effects:

1) The three-level rectification of the present invention is clamped by a diode group, respectively clamping the midpoint of the capacitor in series with the two diodes, clamping the voltage by the capacitor, and stabilizing the AC power supply to output a stable output voltage in total.

2) The three-level rectification of the present invention utilizes the energy storage characteristics of the inductance, and uses the characteristic that the current on the inductance L cannot change abruptly to cooperate with the diode and the voltage clamping capacitor to carry out three-level rectification, so as to maintain the bus voltage stability and ensure the voltage fluctuation of the DC bus output. very small.

3) Compared with the traditional two-level rectifier circuit, the voltage stress requirement on circuit elements is reduced.

4) Since the capacitor voltage is directly clamped by the diode in series, the voltage stress on the switch tube is reduced, and the cost of the switch tube is reduced.

5) When two polar capacitors are used in series, the capacitor voltage decreases.

6) No more than 3 semiconductor devices flow through the rectifier circuit during operation, and the circuit operation loss is small.

7) Only one switch tube needs to be changed to switch the working mode of the circuit, which effectively reduces the switching loss of the circuit.

8) The DC bus is operated in series by two capacitors, which effectively reduces the output current ripple.

Description of drawings

1 is a main topology structure diagram of a diode-clamped back-to-back bridgeless three-level rectifier circuit of the present invention;

2 is a diagram of a working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

3 is a second diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

Fig. 4 is a three-level diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

FIG. 5 is a fourth diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

6 is a fifth diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

7 is a sixth diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;

FIG. 8 is a diagram of six operating modes of the circuit switch tubes S ₁ to S ₄ of the present invention;

9 is a waveform diagram of the circuit voltage U _ab of the present invention;

10 is a waveform diagram of the input voltage U _s and current i _L on the AC side of the circuit of the present invention;

FIG. 11 is a waveform diagram of the DC output voltage U _dc of the circuit of the present invention.

Fig. 12 ( ₁ ) is the pulse distribution diagram of switch tube S1 of the circuit of the present invention;

Fig. 12 ( ₂ ) is the pulse distribution diagram of switch tube S2 of the circuit of the present invention;

Fig. 12 ( ₃ ) is the pulse distribution diagram of switch tube S3 of the circuit of the present invention;

Fig. 12( ₄ ) is a pulse distribution diagram of the switch tube S4 of the circuit of the present invention.

Detailed ways

As shown in Figure 1, the diode-clamped back-to-back bridgeless three-level rectifier includes: a back-to-back structure, a diode-clamped voltage regulator structure, and a single-phase three-level structure.

The back-to-back structure includes two power switch tubes: S ₁ and S ₂ , and the two switch tubes form a back-to-back bidirectional switch structure.

The diode clamp voltage stabilization structure is clamped and stabilized by diode groups D ₅ and D ₆ to the midpoint voltage of the series capacitor groups C ₁ and C ₂ .

The structure of the diode-clamped back-to-back bridgeless three-level rectifier includes four diodes D ₁ , D ₂ , D ₃ , D ₄ , two power switching devices S ₃ , S ₄ , and capacitors C ₁ , C ₂ . _The anode of the diode D1 is connected to the cathode of D2, and its connection point is connected to one end of the AC power supply and one end of the back _- to-back bidirectional switch. _The anode of the diode _D3 is connected to the source _of the fully controlled switch tube S3, and the switch tube S3 _The drain and the source of S4 form a connection point and are connected to the other end of the power supply, the cathode of the diode D4 is connected to the drain of the fully controlled switching tube _{S4 ;} the positive electrode of the capacitor _C1 and the negative electrode of the capacitor _C2 are respectively Connect to the load, the cathode of diode _D3 is connected to the anode of capacitor _C1 , the anode of diode D4 is connected to the cathode of capacitor C2; _two fully _- controlled switch tubes S1 and S2 are opened in the back _- to _- back bidirectional direction _; the anode of clamping diode D5 and the clamping _The cathode of the bit diode _D6 is connected, and the connection point of the diodes D5 and _D6 is connected to the connection point of the series capacitors _C1 and _C2 .

The specific experimental parameters are as follows:

A diode-clamped back-to-back bridgeless three-level rectifier has an effective value of the grid voltage at the input side of 220V, a frequency of 50Hz, an output voltage of 400V at the DC side, a switching frequency of 20kHz, a filter inductance L=3mH, and the resistance of the load _RL . 80Ω, the output capacitance C ₁ =C ₂ =4700μF.

Due to the working characteristics of the public power grid, in order to ensure the stability of the output voltage of the three-level rectifier circuit, it is necessary to adjust different working modes in different grid voltage ranges:

1) Mode 1: As shown in Figure ₂ , the switch S4 is turned on, and the rest of the switches are turned off. u _s >+U _dc /2, u _ab =U _dc , the inductor L releases energy, i _L gradually decreases, and the capacitors C ₁ and C ₂ are charged.

2) Mode 2: As shown in Figure ₃ , the switch tube S3 is turned on, and the rest of the switch tubes are turned off. Since Mode 2 has two working states, it needs to be discussed separately.

When u _s >+U _dc /2, u _ab =U _dc /2, the inductor L absorbs energy at this time, i _L increases gradually, the capacitor C ₁ is charged, and C ₂ is discharged.

When u _s <+U _dc /2, u _ab =U _dc /2, the inductor L releases energy at this time, i _L gradually decreases, the capacitor C ₁ is charged, and C ₂ is discharged.

3) Mode 3: As shown in Figure 4, the switches S ₁ and S ₂ are turned on, and the rest of the switches are turned off. 0<us <+U _dc /2, u _ab =0, the inductor L absorbs energy, _{i L} increases gradually, and the capacitors C ₁ and C ₂ discharge.

4) Mode 4: As shown in Figure ₅ , the switch tube S3 is turned on, and the rest of the switch tubes are turned off. u _s <-U _dc /2, u _ab =U _dc , the inductor L releases energy, i _L gradually decreases, and the capacitors C ₁ and C ₂ are charged.

5) Mode 5: As shown in Figure ₆ , the switch tube S4 is turned on, and the rest of the switch tubes are turned off. Since Mode 2 has two working states, it needs to be discussed separately.

When u _s <-U _dc /2, u _ab =U _dc /2, the inductor L absorbs energy at this time, i _L gradually increases, the capacitor C ₂ is charged, and C ₁ is discharged.

When 0>us>-U _dc /2, u _ab =U _dc /2, the inductor L releases energy at this time, _{i L} gradually decreases, the capacitor C ₂ is charged, and C ₁ is discharged.

6) Mode 6: As shown in Figure 7, the switch tubes S ₁ and S ₂ are turned on, and the rest of the switch tubes are turned off. 0>u _s >-U _dc /2, u _ab =0, the inductor absorbs energy, i _L increases gradually, and the capacitors C ₁ and C ₂ discharge.

In the above working modes, the series capacitor groups C ₁ and C ₂ always play a role in stabilizing the output load on the DC side, and with the adjustment of parameters, the regulated output DC power supply with different output voltages can be realized.

8 , 9 , 10 and 11 are the experimental waveform diagrams of the present invention when the load is 80Ω, and the related waveform diagrams of the present invention when it is in a steady state.

8 is a diagram of six operating modes of the switch tubes S ₁ to S ₄ of the circuit of the present invention; 1 is used to represent the conduction of the switch tube, and 0 is used to represent the turn-off of the switch tube. The invention changes the circuit structure through the combination of on and off of different switch tubes to obtain different output voltages U _ab of the ab terminals. ±1 represents the output rated voltage, ±1/2 represents half of the output rated voltage, and 0 represents the ab terminal voltage is 0. FIG. 9 is a waveform diagram of the circuit voltage U _ab of the present invention; on the basis of FIG. 8 , by modulating the on and off states of the circuit switches S ₁ to S ₄ , the rated output voltage of the DC bus U _dc of the present invention is 400V When the voltage at the ab end can output the rated voltage, half of the rated voltage, and 0 three voltage levels, that is, output voltages of ±400V, ±200V, and 0V. 10 is a waveform diagram of the AC side input voltage U _s and current i _L of the circuit of the present invention; it shows that the steady-state AC input voltage U _s waveform of the present invention maintains a sinusoidal change; the AC input current i _L waveform follows the AC input voltage U _s waveform, and After the waveform is stable, it is close to a sine wave. Through the comparison of the experimental waveforms, it can be seen that the voltage and current phases of the circuit are basically the same, and the power factor correction function can be realized.

11 is a waveform diagram of the DC output voltage U _dc of the circuit of the present invention; it shows the steady-state waveform of the DC bus side voltage U _dc obtained by the present invention when the rated voltage is 400V.

Fig. 12 ( ₁ ) is the pulse distribution diagram of the switch tube S1 _of the circuit of the present invention; it is the waveform diagram of the switch pulse voltage U _S1 of the switch tube S1 of the present invention, which represents the switch pulse distribution signal, that is, the driving voltage of the switch tube being turned on and off. . When the voltage of the switch tube reaches 12V, it corresponds to the 1 signal in Figure 8, that is, the switch tube is turned on. When the voltage of the switch tube reaches 0V, it corresponds to the 0 signal in Figure 8, that is, the switch tube is turned off.

Fig. 12 ( ₂ ) is the pulse distribution diagram of the switch tube S2 of the circuit of the present invention _; it is the waveform diagram of the switch pulse voltage U _S2 of the switch tube S2 of the present invention, which represents the switch pulse distribution signal, that is, the driving voltage of the switch tube being turned on and off. . When the voltage of the switch tube reaches 12V, it corresponds to the 1 signal in Figure 8, that is, the switch tube is turned on. When the voltage of the switch tube reaches 0V, it corresponds to the 0 signal in Figure 8, that is, the switch tube is turned off.

Fig. 12 ( ₃ ) is the pulse distribution diagram of the switch tube S3 _of the circuit of the present invention; it is the waveform diagram of the switch pulse voltage U _S3 of the switch tube S3 of the present invention, which represents the switch pulse distribution signal, that is, the driving voltage of the switch tube being turned on and off. . When the voltage of the switch tube reaches 12V, it corresponds to the 1 signal in Figure 8, that is, the switch tube is turned on. When the voltage of the switch tube reaches 0V, it corresponds to the 0 signal in Figure 8, that is, the switch tube is turned off.

Fig. 12 ( ₄ ) is the pulse distribution diagram of the switch tube S4 of the circuit of the present invention _; it is the waveform diagram of the switch pulse voltage U _S4 of the switch tube S4 of the present invention, which represents the switch pulse distribution signal, that is, the driving voltage of the switch tube being turned on and off. . When the voltage of the switch tube reaches 12V, it corresponds to the 1 signal in Figure 8, that is, the switch tube is turned on. When the voltage of the switch tube reaches 0V, it corresponds to the 0 signal in Figure 8, that is, the switch tube is turned off.

Claims (1)

1. A control method of a diode clamping type back-to-back bridgeless three-level rectifier is characterized in that: the three-level rectifier comprises a switching tube S₁、S₂、S₃、S₄Diode D₁、D₂、D₃、D₄、D₅、D₆Inductor L, capacitor C₁、C₂；

One side of the AC power supply is connected with one end of an inductor L, and the other end of the inductor L is respectively connected with a switch tube S₁Drain electrode, diode D₁Anode, diode D₂A cathode, the connection node of which constitutes an end a;

the other side of the AC power supply is respectively connected with a switch tube S₂Drain electrode, switching tube S₃Source electrode, switch tube S₄A drain connected to the node to form an end point b;

switch tube S₁Source electrode connecting switch tube S₂A source electrode;

diode D₁The cathodes are respectively connected with a diode D₃Cathode and capacitor C₁One end;

diode D₂The anodes are respectively connected with a diode D₄Anode and capacitor C₂The other end;

switch tube S₃The drain electrodes are respectively connected with a diode D₃Anode, diode D₅A cathode;

switch tube S₄The source electrodes are respectively connected with a diode D₄Cathode, diode D₆An anode;

capacitor C₁The other end is respectively connected with a diode D₅Anode, diode D₆Cathode and capacitor C₂One end;

the two ends of the load R are respectively connected with a capacitor C₁One terminal, capacitor C₂The other end;

the control method of the three-level rectifier comprises the following steps: different working modes are adjusted in different power grid voltage intervals:

1) mode 1: switch tube S₁、S₂、S₃Off, S₄Conducting, diode D₁、D₄When operating in the on state, the loop passes through the capacitor C₁、C₂At this time, the grid voltage u_s<U_dc；U_dcFor the voltage across the load R, the capacitor C is connected to the inductor L₁、C₂Clamping the voltage at the load terminal to U_dcUpper, lower electricityA balance voltage u is generated on the inductor L_ab＝U_dc；u_abIs the voltage between the terminals a and b, when the inductor releases energy, the current on the inductor L decreases, and the capacitor C₁、C₂Charging;

2) mode 2: switch tube S₁、S₂、S₄Off, S₃Conducting; diode D₁、D₅When operating in the on state, the loop passes through the capacitor C₁(ii) a When the grid voltage u_s<+U_dcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L₁Clamping the voltage between terminals a and b at U_dcAt/2, a balanced voltage u is generated on the inductor L_ab＝U_dc2; at this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C₁Charging, capacitance C₂Discharging; when the grid voltage u_s>+U_dcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L₁Clamping the voltage between the terminals a and b at U_dcAt/2, a balanced voltage u is generated on the inductor L_ab＝U_dc2; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C₁Charging, capacitance C₂Discharging;

3) modality 3: switch tube S₃、S₄Are all turned off, S₁、S₂Conducting; diodes in the circuit are all cut off, and a power channel does not exist between a power grid and a load; the network voltage is now 0<u_s<+U_dc2; the current on the inductor L can not change suddenly, and the capacitor C₁、C₂Clamping the voltage at the load terminal to U_dcOn the inductor L, a balance voltage u is generated_ab0; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C₁、C₂Discharging;

4) modality 4: switch tube S₁、S₂、S₄Off S₃Conducting, diode D₂、D₃When operating in the on state, the loop passes through the capacitor C₁、C₂At this time, the grid voltage u_s<-U_dc2; due to the inductance LThe current on cannot suddenly change, the capacitor C₁、C₂Clamping the voltage at the load terminal to U_dcOn the inductor L, a balanced voltage is generated to make-u_ab＝U_dc(ii) a At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C₁、C₂Charging;

5) mode 5: switch tube S₁、S₂、S₃Off, S₄Conducting; diode D₂、D₆When operating in the on state, the loop passes through the capacitor C₂(ii) a When the grid voltage u_s>-U_dcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L₂Clamping the voltage between terminals a and b at U_dcAt/2, a balanced voltage is generated at the inductor L to make-u_ab＝U_dc2; at this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C₂Charging, capacitance C₁Discharging; when the grid voltage u_s<-U_dcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L₂Clamping the voltage between the terminals a and b at U_dcAt/2, a balanced voltage is generated at the inductor L to make-u_ab＝U_dc2; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C₂Charging, capacitance C₁Discharging;

6) modality 6: switch tube S₃、S₄Are all turned off, S₁、S₂Conducting; diodes in the circuit are all cut off, and a power channel does not exist between a power grid and a load; the network voltage is now 0<u_s<-U_dc2; the current on the inductor L cannot suddenly change, so that the capacitor C₁、C₂Clamping the voltage at the load terminal to U_dcOn the inductor L, a balance voltage u is generated_ab0; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C₁、C₂And (4) discharging.

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