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CN112635335B - Chip packaging method and chip packaging structure - Google Patents

Chip packaging method and chip packaging structure Download PDF

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Publication number
CN112635335B
CN112635335B CN202011460680.7A CN202011460680A CN112635335B CN 112635335 B CN112635335 B CN 112635335B CN 202011460680 A CN202011460680 A CN 202011460680A CN 112635335 B CN112635335 B CN 112635335B
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substrate
chip
layer
seed layer
conductive
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CN112635335A (en
Inventor
杨斌
罗绍根
崔成强
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Publication of CN112635335A publication Critical patent/CN112635335A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a chip packaging method, which comprises the steps of preparing a substrate for chip packaging and chip packaging, and comprises the following steps: providing a second substrate, and forming a plurality of conductive columns on one surface of the second substrate; providing a third substrate, forming a second seed layer on one surface of the third substrate, forming a rewiring layer on the second seed layer, and forming through holes penetrating through the rewiring layer and the second seed layer on the rewiring layer and the second seed layer; embedding the conductive posts in alignment with the via holes, and attaching the second substrate to the third substrate to obtain a substrate for chip packaging; removing one of the second substrate and the third substrate to expose one end of the conductive column; providing a plurality of chip groups, inversely installing the chip groups on the exposed side of the conductive column of the substrate for chip packaging and carrying out plastic package; and removing the other one of the second substrate and the third substrate to expose the other end of the conductive column, and electrically leading out the chip set at the exposed end of the conductive column. The invention can effectively reduce the warping phenomenon in the packaging process and improve the chip packaging effect.

Description

Chip packaging method and chip packaging structure
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a chip packaging method and a chip packaging structure.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of new generation electronic products, especially the development of products such as mobile phones, notebooks, intelligent wearable devices, etc., chips are developed in the direction of higher density, faster speed, smaller size, lower cost, etc.
In the packaging process, due to the difference of the thermal expansion coefficients of materials such as plastic, silicon and metal, the volume changes of the materials are asynchronous, so that stress is generated and warping is caused. The difference between the thermal expansion coefficients of the chip and the injection molding material enables the stress generated in the cooling process of the injection molding material to be the most main cause of the warpage generation in the packaging technology.
In addition, in the chip fan-out package process, it is usually necessary to drill a plastic package layer of the covered flip chip and fabricate a conductive post by electroplating, so as to electrically lead out the flip chip. In the process of opening the holes, the depth of the holes is not easy to control, so that the chips are easily damaged or other conductive circuits are broken down, and the yield of the chip packaging structure is influenced.
Disclosure of Invention
The invention aims to provide a chip packaging method and a chip packaging structure, which can reduce warpage and effectively improve the packaging yield of chips.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a chip packaging method is provided, which includes preparing a substrate for chip packaging and chip packaging, wherein the preparation of the substrate for chip packaging includes the following steps:
providing a second substrate, and forming a plurality of conductive columns on one surface of the second substrate;
providing a third substrate, forming a second seed layer on one surface of the third substrate, forming a rewiring layer on the second seed layer, and forming via holes penetrating through the rewiring layer and the second seed layer on the rewiring layer and the second seed layer;
aligning the conductive post with the via hole, embedding the conductive post into the via hole, and enabling the second substrate to be attached to the third substrate to obtain the substrate for chip packaging;
the chip package comprises the following steps:
removing one of the second substrate and the third substrate to expose one end of the conductive column;
providing a plurality of chip groups, inversely installing the chip groups on the exposed side of the conductive column of the substrate for chip packaging and carrying out plastic package;
and removing the other one of the second substrate and the third substrate to expose the other end of the conductive column, and electrically leading out the chip group at the exposed end of the conductive column.
According to the invention, the conductive column is directly formed on the second substrate, the through holes which are matched with the conductive column in a plugging manner are formed in the redistribution layer and the second seed layer on the third substrate, the conductive column is embedded into the through holes to obtain the substrate for packaging the chip, then two sides of a circuit (comprising the redistribution layer, the second seed layer and the conductive column) of the substrate for packaging the chip are sequentially exposed, the inverted chip set is packaged at one side of the circuit, and the other side is electrically led out, so that the fan-out packaging of the chip is realized, the warping phenomenon can be effectively reduced in the packaging process, and the chip packaging effect is improved.
As a preferred scheme of a chip packaging method, a first substrate with a plurality of grooves on the surface is provided, and a first seed layer is manufactured on the surfaces of the first substrate and the grooves;
manufacturing a barrier layer on the first seed layer, forming hole positions corresponding to the grooves on the barrier layer, and exposing the first seed layer to the hole positions;
manufacturing the conductive columns in the hole sites;
providing the second substrate, and attaching the barrier layer to the second substrate;
removing the first substrate and the first seed layer to expose the conductive posts;
preferably, the groove is concave hemispherical; or the groove is of a concave conical structure, and the groove bottom area of the groove is smaller than the area of the notch.
The preparation of the conductive columns and the preparation sequence of the via holes are not limited and can be carried out synchronously.
The depth of the groove structure and the groove on the first substrate can be determined according to the designed chip packaging position, so that after the conductive column is embedded into the via hole, one end of the conductive column is flush with one side, away from the redistribution layer, of the second seed layer.
Optionally, the barrier layer is a photosensitive dry film, and the hole site is formed through exposure and development;
or the barrier layer is made of dielectric materials, and the hole sites are formed through laser opening.
As a preferred scheme of the chip packaging method, providing the third substrate, and forming the second seed layer made of copper metal on the third substrate;
manufacturing a photosensitive dry film on the second seed layer, and forming a graphical window on the photosensitive dry film to enable the residual photosensitive dry film to at least cover the position of the second seed layer corresponding to the conductive post;
manufacturing the redistribution layer in the graphical window;
and removing the residual photosensitive dry film and the second seed layer exposed out of the rewiring layer to form the via hole, wherein the via hole penetrates through the rewiring layer and the second seed layer in the thickness direction.
According to the invention, the second seed layer made of the copper metal material is formed on the third substrate by a vacuum sputtering method, so that the stability of an electric connection structure for subsequent chip set packaging or electric leading-out can be improved.
And after the photosensitive dry film on the second seed layer is manufactured, a graphical window is opened through exposure and development.
In order to improve the electrical connection stability between the conductive pillar and the hole wall of the via hole, optionally, attaching nano metal powder to the surface of the conductive pillar and/or the via hole, aligning the conductive pillar with the via hole, embedding the conductive pillar into the via hole, and attaching the second substrate to the third substrate by hot pressing; the nano metal powder can be nano copper powder or nano titanium alloy powder and the like, preferably is nano copper powder, can be adsorbed on the surfaces of the via holes and the conductive posts through static electricity, after the conductive posts are inserted into the via holes, the nano metal powder is filled in gaps between the conductive posts and the via holes after being melted in the hot pressing process, and therefore stable electric connection between the conductive posts and the redistribution layer and between the conductive posts and the second seed layer is achieved.
Or, performing plasma cleaning on the second substrate with the conductive pillars and the third substrate with the second seed layer and the redistribution layer, then inserting the conductive pillars in alignment with the via holes, and attaching and connecting the second substrate and the third substrate through electrostatic adsorption.
In the invention, the first substrate, the second substrate and the third substrate are all glass carrier plates. The glass material is used as the first substrate, and after the conductive column is embedded into the groove of the first substrate, the first substrate can be conveniently and smoothly removed subsequently. The glass material is used as the first substrate, the second substrate and the third substrate, and the chip set can be fixed by performing laser sintering from the back of the glass material substrate when a chip is packaged subsequently.
Optionally, providing a plurality of chip groups, attaching nano metal powder to the I/O ports of the chip groups, then inversely installing the chip groups on the substrate for chip packaging from which the second substrate or the third substrate is removed, sintering one surface of the substrate for chip packaging, which is far away from the chip groups, by using laser, so that the I/O ports of the chip groups are electrically connected with the substrate for chip packaging, and then carrying out plastic package on the chip groups; electrically connecting the I/O port of the chip group with a circuit (comprising a conductive column, a second seed layer and a rewiring layer) on the substrate for chip packaging by laser sintering;
or, providing a plurality of chip groups, when I/O ports of the chip groups are flush with the surfaces of the chip groups, carrying out plasma cleaning on the chip groups and the substrates for chip packaging for removing the second substrate or the third substrate, electrically connecting the I/O ports of the chip groups with the circuits of the substrates for chip packaging through electrostatic adsorption, and then carrying out plastic package on the chip groups.
As a preferable aspect of the chip packaging method, the substrate for chip packaging may provide two positions for flip chip packaging of the chip set.
Optionally, removing the second substrate to expose the conductive pillars;
providing a plurality of chip groups, inversely installing the chip groups, electrically connecting the chip groups with the conductive columns, and plastically packaging the chip groups;
removing the third substrate and leading out the chip set electrically;
or,
removing the third substrate to expose the second seed layer and the conductive posts;
providing a plurality of chip groups, and inversely installing the chip groups and electrically connecting the chip groups with the second seed layer and/or the conductive columns;
carrying out plastic package on the chip set;
and removing the second substrate and electrically leading out the chip set.
In another aspect, a chip package structure is provided, including:
the second seed layer is made of copper metal material;
the rewiring layer is positioned on the second seed layer, and a plurality of through holes are formed in the rewiring layer and the second seed layer at intervals along the thickness direction of the rewiring layer and the second seed layer;
the blocking layer is positioned on one side, away from the second seed layer, of the rewiring layer;
one end of each conductive column is embedded into the barrier layer and is flush with one surface of the barrier layer, the rest part of each conductive column is embedded into the via hole, and the other end of each conductive column is flush with one surface, far away from the redistribution layer, of the second seed layer;
the chip groups are inversely pasted at one end of the conductive columns and are electrically connected with the conductive columns;
the plastic package layer covers the chip group;
the electric connection structure is positioned at the other end of the conductive column and used for leading out the chip group electrically;
wherein a circuit of the substrate for chip packaging is formed at least by the conductive pillar, the second seed layer and the redistribution layer.
Specifically, the via penetrates through both the second seed layer and the redistribution layer.
As a preferable scheme of the chip packaging structure, the chip packaging structure further includes a first metal connection layer, where the conductive pillar, the second seed layer, the redistribution layer, and the first metal connection layer form a circuit of the substrate for chip packaging, and the first metal connection layer is filled in a gap between an outer wall of the conductive pillar and a hole wall of the via hole, so as to electrically connect the conductive pillar, the redistribution layer, and the second seed layer. The first metal connecting layer is formed by heating and melting nano metal powder, so that the connection stability between the conductive column and the redistribution layer and between the conductive column and the second seed layer is improved, namely, the stability of the circuit is improved.
As a preferable scheme of the chip packaging structure, the chip packaging structure further includes a second metal connection layer, which is located between the I/O port of the chipset and the circuit of the substrate for chip packaging, and is used to fixedly connect the I/O port of the chipset and the circuit of the substrate for chip packaging. The second metal connecting layer is formed by heating and melting nano metal powder so as to improve the connection stability between the I/O port of the chip set and the circuit of the substrate for packaging the chip.
Optionally, the chip package structure the I/O port of the chipset is flush with the surface of the chipset, the chipset is connected to the circuit of the substrate for chip package through electrostatic adsorption, and then fixed to the circuit of the substrate for chip package through plastic package.
In the invention, the conductive column is in a conical structure, and the area of one end of the conductive column, which is flush with the surface of the second seed layer, is smaller than that of the other end of the conductive column, so that the conductive column can be conveniently and smoothly embedded into the via hole.
As a preferable aspect of the chip package structure, when the chipset is located at an end surface of the conductive pillar that is flush with the surface of the second seed layer, the I/O port of the chipset is electrically connected to the second seed layer and/or the surface of the conductive pillar, and the electrical connection structure includes:
the solder mask layer is positioned on one side, far away from the rewiring layer, of the blocking layer, and is provided with a plurality of welding positions enabling the conductive columns to be exposed;
and the metal bumps are positioned in the welding positions and are electrically connected with the surfaces of the conductive columns.
Optionally, when the chipset is located at an end surface of the conductive pillar away from the second seed layer, the I/O port of the chipset is electrically connected to the surface of the conductive pillar, and the electrical connection structure includes:
the solder mask layer is positioned on one side, close to the redistribution layer, of the barrier layer and covers the redistribution layer and the second seed layer, and a plurality of welding positions enabling the second seed layer and/or the conductive column to be exposed are formed in the solder mask layer;
and the metal bumps are positioned in the welding positions and are electrically connected with the second seed layer and/or the conductive columns.
Wherein, the barrier layer is a photosensitive dry film or a dielectric material. When the barrier layer is a photosensitive dry film, hole positions corresponding to the positions of the grooves can be formed through exposure and development, so that the conductive columns can be manufactured through electroplating; when the barrier layer is made of a dielectric layer material, laser hole opening is carried out on the barrier layer corresponding to the position of the groove, and a hole position for manufacturing the conductive post in an electroplating mode can be formed.
The invention has the beneficial effects that: according to the invention, the conductive column is directly formed on the second substrate, the through hole which is matched with the conductive column in a plugging manner is formed in the rewiring layer and the second seed layer on the third substrate, the conductive column is embedded into the through hole to prepare the substrate for packaging the chip, then two sides of the circuit of the substrate for packaging the chip are sequentially exposed, the inverted chip set is packaged at one side of the circuit, and the other side of the circuit is electrically led out, so that the fan-out packaging of the chip is realized, the warping phenomenon can be effectively reduced in the packaging process, and the chip packaging effect is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic cross-sectional view of a first substrate according to a first embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a first seed layer formed on a first substrate according to a first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a first seed layer with a barrier layer formed thereon and holes formed thereon according to a first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view illustrating the fabrication of a conductive pillar and the attachment of the conductive pillar to a second substrate according to a first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view illustrating the first substrate and the first seed layer removed according to the first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a third substrate with a second seed layer formed thereon according to a first embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating a photosensitive dry film formed on a second seed layer according to a first embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a photosensitive dry film after exposure and development according to a first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a redistribution layer after being fabricated according to a first embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating the removal of the residual photosensitive dry film and the second seed layer exposed on the redistribution layer according to the first embodiment of the invention.
Fig. 11 is a schematic cross-sectional view of a substrate for chip packaging according to a first embodiment of the invention.
Fig. 12 is a schematic cross-sectional view of a chip set flip-chip mounted on an exposed circuit of a second substrate with a chip package substrate removed according to a first embodiment of the invention.
Fig. 13 is a schematic cross-sectional view of the chip set after being molded according to the first embodiment of the invention.
Fig. 14 is a schematic cross-sectional view of the third substrate removed, the solder mask formed, and the solder joints formed according to the first embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of a bonding site after a metal bump is implanted according to an embodiment of the invention.
Fig. 16 is a schematic cross-sectional view of a chip set according to a third embodiment of the present invention, which is flip-chip mounted on an exposed circuit of a third substrate with a chip package substrate removed.
Fig. 17 is a schematic cross-sectional view of the packaged chip set according to the third embodiment of the invention.
Fig. 18 is a schematic cross-sectional view of the third embodiment of the present invention after removing the second substrate, forming the solder mask and opening the solder joint.
Fig. 19 is a schematic cross-sectional view of the third embodiment of the invention after the metal bump is implanted at the bonding site.
In the figure:
11. a first substrate; 12. a groove; 13. a first seed layer; 14. a barrier layer; 15. a conductive post; 16. a second substrate; 21. a third substrate; 22. a second seed layer; 23. photosensitive dry film; 24. a rewiring layer; 25. a via hole; 31. a chipset; 32. a solder resist layer; 33. a metal bump; 34. and (7) plastic packaging layer.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example one
Step S10, preparing the conductive pillar, specifically including:
step S10a, providing a first substrate 11 made of glass and having a surface with a plurality of tapered grooves 12 as shown in fig. 1, and manufacturing a first seed layer 13 (refer to fig. 2) on the first substrate 11 and the surfaces of the grooves 12 by vacuum sputtering; in other embodiments, the groove 12 may also be concave hemispherical;
step S10b, as shown in fig. 3, a barrier layer 14 (photosensitive dry film) is formed on the first seed layer 13, a hole corresponding to the position of the groove 12 is formed on the barrier layer 14 through exposure and development, and the first seed layer 13 is exposed to the hole; in other embodiments, the barrier layer 14 is a dielectric material and the holes are formed by laser drilling.
Step S10c, as shown in fig. 4, manufacturing the conductive post 15 in the hole site by electroplating, where the conductive post 15 is flush with the upper surface of the barrier layer 14;
step S10d, providing a second substrate 16 made of glass, and attaching the barrier layer 14 to the second substrate 16, where the second substrate 16 is made of glass, so as to facilitate attaching a temporary bonding material to the second substrate 16 and fixing the chip set by laser sintering;
step S10e, removing the first substrate 11 and the first seed layer 13 by bonding, so as to expose the conductive pillar 15, where the conductive pillar 15 has a bump protruding from the surface of the barrier layer 14, as shown in fig. 5.
Step S20, preparing a via hole, specifically including:
step S20a, as shown in fig. 6, providing a third substrate 21 made of glass, and forming the second seed layer 22 made of copper metal on the third substrate 21 by vacuum sputtering;
step S20b, as shown in fig. 7, a photosensitive dry film 23 is manufactured on the second seed layer 22, and a patterning window is opened on the photosensitive dry film 23 through exposure and development, so that the remaining photosensitive dry film at least covers the position of the second seed layer 22 corresponding to the conductive post 15 (fig. 8);
step S20c, as shown in fig. 9, manufacturing the redistribution layer 24 in the patterned window by electroplating;
step S20d, as shown in fig. 10, removes the residual photosensitive dry film 23 and the second seed layer 22 exposed from the redistribution layer 24 to form the via 25.
Step S30, press-fitting the substrate for chip packaging shown in fig. 11: attaching nanometer copper powder to the surfaces of the conductive pillars 15 and/or the via holes 25, aligning the conductive pillars 15 with the via holes 25, embedding the conductive pillars 15 into the via holes 25, and melting and filling the nanometer copper powder between the gaps of the conductive pillars 15 and the via holes 25 through hot pressing to form a first metal connection layer, so that the conductive pillars 15 are stably and electrically connected with the redistribution layer 24 and the second seed layer 22; the circuit of the substrate for circuit packaging is composed of a conductive column 15, a redistribution layer 24, a second seed layer 22 and a first metal connection layer; the first metal connection layer is not shown in the figure.
Step S40, chip packaging, specifically including:
step S40a, removing the second substrate 16 of the base for chip packaging, so that one end surface of the conductive post 15 in the circuit of the base for chip packaging flush with the barrier layer 14 is exposed;
step S40b, providing a plurality of the chip sets 31, attaching the copper nanoparticles to the I/O ports of the chip sets 31, then flip-chip mounting the chip sets on the surfaces of the conductive pillars 15, and sintering the surface of the third substrate 21 away from the chip sets 31 by using laser, so that the I/O ports of the chip sets 31 are electrically connected to the conductive pillars 15, as shown in fig. 12. The second metal connecting layer is formed after the nanometer copper powder between the I/O port of the chipset 31 and the conductive column 15 is sintered and melted by laser;
step S40c, as shown in fig. 13, plastic-sealing the chipset 31 to form a plastic-sealed layer 34;
step S40d, removing the third substrate 21, and coating photosensitive ink on the exposed surface of the barrier layer 14 to form a solder mask layer 32;
step S40e, exposing and developing the solder resist layer 32 to form a solder joint exposing the conductive pillar 15 and/or the second seed layer 22, as shown in fig. 14;
step S40f, providing a metal bump 33, and implanting the metal bump 33 into the soldering site to electrically connect with the conductive pillar 15 and/or the second seed layer 22, so as to electrically lead out the chipset 31, referring to fig. 15; the metal bump 33 is solder, silver solder or gold-tin alloy solder, and the embodiment is preferably a solder ball made of solder.
In other embodiments, the number of the chipsets and the number of the chips in each chipset are determined according to specific design requirements, and are not particularly limited.
As shown in fig. 15, the chip package structure manufactured by the chip package method of the present embodiment includes:
a second seed layer 22, wherein the second seed layer 22 is a copper metal material;
the redistribution layer 24 is positioned on the second seed layer 22, and a plurality of through holes 25 are formed in the redistribution layer 24 and the second seed layer 22 at intervals along the thickness direction of the two layers;
a barrier layer 14 on a side of the redistribution layer 24 away from the second seed layer 22;
one end of each conductive pillar 15 is embedded into the barrier layer 14 and is flush with one surface of the barrier layer 14, the rest of each conductive pillar is embedded into the via hole 25, and the other end of each conductive pillar 15 is flush with one surface, far away from the redistribution layer 24, of the second seed layer 22; at least the second seed layer 22, the redistribution layer 24, and the conductive pillars 15 form a circuit of a substrate for chip packaging;
a plurality of chip sets 31 flip-chip bonded to the conductive posts 15 on the same level side as the barrier layer 14 and electrically connected to the conductive posts 15;
a molding layer 34 covering the chip set 31;
and the electric connection structure is positioned on one side of the circuit of the substrate for packaging the chip, which is far away from the chip set 31, and is used for electrically leading out the chip set 31.
The chip packaging structure in the embodiment is not easy to warp and has high production yield.
Further, the chip package structure further includes a first metal connection layer, and the first metal connection layer is filled in the gap between the conductive pillar 15 and the via hole 25, so as to electrically connect the conductive pillar 15, the redistribution layer 24, and the second seed layer 22. The first metal connection layer is formed by laser sintering of nano metal powder between the conductive pillars 15 and the via holes 25, and the first metal connection layer, the conductive pillars 15, the redistribution layer 24 and the second seed layer 22 form a circuit of the substrate for chip packaging.
Further, the chip packaging structure further includes a second metal connection layer, which is located between the I/O port of the chipset 31 and the circuit of the substrate for chip packaging, and is used to fixedly connect the I/O port of the chipset 31 and the circuit of the substrate for chip packaging. The second metal connection layer is formed by laser sintering of nano metal powder between the I/O port of the chipset 31 and the circuit of the substrate for chip packaging.
The conductive post 15 is a tapered structure, and an area of one end of the conductive post 15, which is flush with the surface of the second seed layer 22, is smaller than an area of the other end of the conductive post 15, so that the conductive post 15 can be smoothly embedded into the via hole 25.
Wherein, the chipset 31 is located on an end surface of the conductive pillar 15 away from the second seed layer 22, the I/O port of the chipset 31 is electrically connected with the surface of the conductive pillar 15, and the electrical connection structure includes:
the solder mask layer 32 is positioned on one side, close to the redistribution layer 24, of the barrier layer 14 and covers the redistribution layer 24 and the second seed layer 22, and a plurality of welding positions for exposing the second seed layer 22 and/or the conductive column 15 are formed in the solder mask layer 32;
and a plurality of metal bumps 33 located in the soldering positions and electrically connected with the second seed layer 22 and/or the conductive pillars 15.
Example two
This embodiment is substantially the same as the first embodiment (refer to the drawings in the first embodiment, and the same components are denoted by the same reference numerals in the first embodiment), except for the bonding manner in the step S30 of preparing the substrate for chip packaging by pressing.
Specifically, the step S30 of chip packaging in this embodiment includes the following steps:
and carrying out plasma cleaning on the second substrate 16 with the conductive posts 15 and the third substrate 21 with the second seed layer 22 and the redistribution layer 24, then inserting the conductive posts 15 into the through holes 25, and attaching and connecting the second substrate 16 and the third substrate 21 through electrostatic adsorption.
The chip package structure manufactured by the method of this embodiment is substantially the same as that of the first embodiment, except that the circuit of the circuit package substrate is composed of the conductive pillar 15, the second seed layer 22 and the redistribution layer 24, and does not include the first metal connection layer.
EXAMPLE III
The present embodiment is substantially the same as the first embodiment, except for the packaging position of the chipset in the chip package of step S40.
Specifically, the step S40 of chip packaging in this embodiment includes the following steps:
step S40A, removing the third substrate 21 of the base for chip packaging, and exposing the conductive pillars 15 and the second seed layer 22 in the circuit of the base for chip packaging;
step S40B, providing a plurality of the chipsets 31, when the I/O ports of the chipsets 31 are flush with the surface of the chipsets 31, performing plasma cleaning on the chipsets 31 and the bases for chip packaging after removing the third substrate 21, and electrically connecting the I/O ports of the chipsets 31 with the conductive pillars 15 and/or the second seed layer 22 by electrostatic adsorption, referring to fig. 16; before the electrostatic adsorption and bonding, the chipset 31 and the circuit of the substrate for chip packaging need to be plasma-cleaned to remove surface impurities and improve the electrostatic adsorption and bonding effect.
Step S40C, plastic-packaging the chipset 31, referring to fig. 17;
step S40D, removing the second substrate 16, and coating photosensitive ink on the exposed surface of the barrier layer 14 to form a solder mask layer 32;
step S40E, exposing and developing the solder resist layer 32 to form a solder joint exposing the conductive pillar 15, referring to fig. 18;
step S40F, providing a metal bump 33, and implanting the metal bump 33 into the soldering site to electrically connect with the conductive pillar 15, so as to electrically lead out the chipset 31, referring to fig. 19; the metal bump 33 is solder, silver solder or gold-tin alloy solder, and the embodiment is preferably a solder ball made of solder.
The chip packaging structure manufactured by the method of the embodiment is basically the same as that of the embodiment, and the difference is the packaging position of the chip group.
Specifically, as shown in fig. 19, the chip package structure in the present embodiment includes:
a second seed layer 22, wherein the second seed layer 22 is a copper metal material;
the redistribution layer 24 is positioned on the second seed layer 22, and a plurality of through holes 25 are formed in the redistribution layer 24 and the second seed layer 22 at intervals along the thickness direction of the two layers;
a barrier layer 14 on a side of the redistribution layer 24 away from the second seed layer 22;
one end of each conductive pillar 15 is embedded into the barrier layer 14 and is flush with one surface of the barrier layer 14, the rest of each conductive pillar is embedded into the via hole 25, and the other end of each conductive pillar 15 is flush with one surface, far away from the redistribution layer 24, of the second seed layer 22; at least the second seed layer 22, the redistribution layer 24, and the conductive pillars 15 form a circuit of a substrate for chip packaging;
the chip groups 31 are flip-chip bonded to the sides of the conductive columns 15, which are flush with the second seed layer 22, and are electrically connected with the conductive columns 15 and/or the second seed layer 22;
a molding layer 34 covering the chip set 31;
and the electric connection structure is positioned on one side of the circuit of the substrate for packaging the chip, which is far away from the chip set 31, and is used for electrically leading out the chip set 31.
In this embodiment, the chipset 31 is located on an end surface of the conductive pillar 15 that is flush with the surface of the second seed layer 22, the I/O port of the chipset 31 is electrically connected to the second seed layer 22 and/or the surface of the conductive pillar 15, and the electrical connection structure includes:
the solder mask layer 32 is positioned on one side of the barrier layer 14, which is far away from the redistribution layer 24, and the solder mask layer 32 is provided with a plurality of welding positions for exposing the conductive columns 15;
and a plurality of metal bumps 33 located in the soldering positions and electrically connected with the surface of the conductive column 15.
The chip package structure of the present embodiment does not include the second metal connection layer.
Example four
This embodiment is substantially the same as the third embodiment (refer to the drawings in the third embodiment, and the same components are labeled with the same numerals in the first embodiment), except for the bonding manner in the step S30 of preparing the substrate for chip packaging by pressing.
Specifically, the step S30 of chip packaging in this embodiment includes the following steps:
and carrying out plasma cleaning on the second substrate 16 with the conductive posts 15 and the third substrate 21 with the second seed layer 22 and the redistribution layer 24, then inserting the conductive posts 15 into the through holes 25, and attaching and connecting the second substrate 16 and the third substrate 21 through electrostatic adsorption.
The chip packaging structure manufactured by the chip packaging method of the embodiment is basically the same as the third embodiment, except that the first metal connection layer is not included, and details are not repeated.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (10)

1. The chip packaging method is characterized by comprising the following steps of preparing a substrate for chip packaging and chip packaging, wherein the preparation of the substrate for chip packaging comprises the following steps:
providing a second substrate made of glass, and forming a plurality of conductive columns on one surface of the second substrate;
providing a third substrate made of glass, forming a second seed layer on one surface of the third substrate, forming a rewiring layer on the second seed layer, and forming through holes penetrating through the rewiring layer and the second seed layer on the rewiring layer and the second seed layer;
aligning the conductive post with the via hole, embedding the conductive post into the via hole, and enabling the second substrate to be attached to the third substrate to obtain the substrate for chip packaging;
the chip package comprises the following steps:
removing one of the second substrate and the third substrate to expose one end of the conductive column;
providing a plurality of chip groups, inversely installing the chip groups on the exposed side of the conductive column of the substrate for chip packaging and carrying out plastic package;
and removing the other one of the second substrate and the third substrate to expose the other end of the conductive column, and electrically leading out the chip group at the exposed end of the conductive column.
2. The chip packaging method according to claim 1,
providing a first substrate made of glass and provided with a plurality of grooves on the surface, and manufacturing a first seed layer on the surfaces of the first substrate and the grooves;
manufacturing a barrier layer on the first seed layer, forming hole positions corresponding to the grooves on the barrier layer, and exposing the first seed layer to the hole positions;
manufacturing the conductive columns in the hole sites;
providing the second substrate, and attaching the barrier layer to the second substrate;
and removing the first substrate and the first seed layer to expose the conductive posts.
3. The chip packaging method according to claim 2, wherein the barrier layer is a photosensitive dry film, and the hole is formed by exposure and development;
or the barrier layer is made of dielectric materials, and the hole sites are formed through laser opening.
4. The chip packaging method according to claim 1,
providing the third substrate, and forming the second seed layer made of the copper metal material on the third substrate;
manufacturing a photosensitive dry film on the second seed layer, and forming a graphical window on the photosensitive dry film to enable the residual photosensitive dry film to at least cover the position of the second seed layer corresponding to the conductive post;
manufacturing the redistribution layer in the graphical window;
and removing the residual photosensitive dry film and the second seed layer exposed out of the rewiring layer to form the via hole.
5. The chip packaging method according to claim 1, wherein nano metal powder is attached to the surfaces of the conductive posts and/or the via holes, the conductive posts are aligned with the via holes and embedded into the via holes, and the second substrate and the third substrate are bonded and connected by hot pressing;
or, performing plasma cleaning on the second substrate with the conductive pillars and the third substrate with the second seed layer and the redistribution layer, then inserting the conductive pillars in alignment with the via holes, and attaching and connecting the second substrate and the third substrate through electrostatic adsorption.
6. The method of claim 2, wherein the recess is in the shape of a concave hemisphere or a concave cone.
7. The chip packaging method according to claim 6, wherein a plurality of the chip groups are provided, the I/O ports of the chip groups are stained with nano metal powder and then are inversely installed on the chip packaging base without the second substrate or the third substrate, laser is adopted to sinter one surface of the chip packaging base away from the chip groups, the I/O ports of the chip groups are electrically connected with the chip packaging base, and then the chip groups are plastically packaged; or,
and providing a plurality of chip groups, when I/O ports of the chip groups are flush with the surfaces of the chip groups, carrying out plasma cleaning on the chip groups and the substrates for chip packaging for removing the second substrate or the third substrate, electrically connecting the I/O ports of the chip groups with the substrates for chip packaging through electrostatic adsorption, and then carrying out plastic package on the chip groups.
8. The chip packaging method according to claim 1, wherein the second substrate is removed to expose the conductive pillars; providing a plurality of chip groups, inversely installing the chip groups, electrically connecting the chip groups with the conductive columns, and plastically packaging the chip groups; removing the third substrate and leading out the chip set electrically; or,
removing the third substrate to expose the second seed layer and the conductive posts; providing a plurality of chip groups, and inversely installing the chip groups and electrically connecting the chip groups with the second seed layer and/or the conductive columns; carrying out plastic package on the chip set; and removing the second substrate and electrically leading out the chip set.
9. A chip packaging structure prepared by the chip packaging method according to any one of claims 1 to 8, comprising:
the second seed layer is made of copper metal material;
the rewiring layer is positioned on the second seed layer, and a plurality of through holes are formed in the rewiring layer and the second seed layer at intervals along the thickness direction of the rewiring layer and the second seed layer;
the blocking layer is positioned on one side, away from the second seed layer, of the rewiring layer;
one end of each conductive column is embedded into the barrier layer and is flush with one surface of the barrier layer, the rest part of each conductive column is embedded into the via hole, and the other end of each conductive column is flush with one surface, far away from the redistribution layer, of the second seed layer; at least the second seed layer, the redistribution layer and the conductive column form a circuit of a substrate for chip packaging;
a plurality of chip groups which are inversely pasted on one side of the circuit of the substrate for chip packaging and are electrically connected with the circuit of the substrate for chip packaging;
the plastic package layer covers the chip group;
and the electric connection structure is positioned on one side of the circuit of the substrate for packaging the chip, which is far away from the chip set, and is used for leading out the chip set electrically.
10. The chip package structure according to claim 9, further comprising a first metal connection layer, wherein the first metal connection layer is filled in a gap between an outer wall of the conductive pillar and a hole wall of the via hole, so as to electrically connect the conductive pillar with the redistribution layer and the second seed layer.
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