CN105762087A - Method And Device Used For Packaging Boss Chip On Trace - Google Patents

Abstract

The present invention provides methods and apparatus for attaching a first substrate to a second substrate. In some embodiments, the first substrate has a protective layer, such as a solder mask, located around the die attach region where the first substrate is attached to the second substrate. A blocking region (for example, a region between the second substrate and the protective layer) is a region located around the second substrate in which the protective layer is not formed or removed. Adjusting the size of the blocking region so that a sufficient gap exists between the second substrate and the protective layer to place the underfill between the first substrate and the second substrate, while reducing or preventing voids, and at the same time allowing Traces in the shadowed area are covered by underfill.

Description

Method and apparatus for bump-on-trace chip packaging

Priority Claims and Cross References

This application is Patent Application No. 13/450,191 filed on April 18, 2012 and titled "Submitted Title: Method and Apparatus for Chip Packaging Integrated Circuit Die. Polymer Compound for Filling Material. Area between ChipPackaging" continuation-in-part of the application, the entire contents of which are hereby incorporated by reference.

technical field

The present invention relates to integrated circuit devices, and more particularly, to methods and apparatus for bump-on-trace chip packaging.

Background technique

An integrated circuit or chip is made up of thousands of active and passive devices such as transistors and capacitors. These devices are initially isolated from each other and then interconnected to form an integrated circuit. Further forming the connector structure for use in an integrated circuit, the connector structure may include bond pads or metal bumps formed on the surface of the circuit. Electrical connections are made through bond pads or metal bumps to connect the chip to a packaging substrate or another die. Typically, chips may be assembled into packages such as pin grid array (PGA) or ball grid array (BGA) using wire bond (WB) or flip chip (FC) packaging techniques.

Flip-chip (FC) packaging technology can use a bump-on-trace (BOT) structure to connect the chip to the package substrate, where the connection is made through metal bumps to connect the chip to the package substrate or the metal of the die. trace. The BOT structure provides a low-cost alternative to the microelectronic packaging industry. However, as the substrate structure becomes thinner, reliability problems arise in the BOT structure.

When the BOT structure is used, the bumps for the chip are soldered on the traces on the package substrate through a reflow process. When the bumps are attached to the substrate and cooled to room temperature by reflow conditions, thermal forces caused by the mismatch in coefficient of thermal expansion (CTE) drive the substrate to shrink and cause relative distortion of each bump. Trace delamination failures occur once the stress level rises above the bond criteria between the substrate and the trace.

Contents of the invention

In order to solve the problems existing in the prior art, the present invention provides a device comprising: a first substrate having traces formed on the first substrate, the first substrate having a die attach region, a shielding region surrounding a periphery of the die attach region, and a peripheral region surrounding a periphery of the shielding region, the first substrate having a protective layer covering the traces in the peripheral region; a second substrate electrically connected to the first substrate in the die attach region; and an underfill interposed between the first substrate and the second substrate, the bottom A filler extends over the traces located in the occluded region; wherein an area of the occluded region is between about 5% and about 18% of an area of the second substrate.

In the above device, wherein the second substrate includes an integrated circuit die.

In the above device, wherein the shielding distance between the edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μm.

In the above device, wherein, the underfill includes a polymer compound with a silicon dioxide filling material.

In the above device, wherein the underfill completely covers the traces located in the shielding area and the die attach area.

In the above device, wherein the second substrate is attached to the first substrate using a bump-on-trace connection.

In the above device, wherein the second substrate includes copper pillars directly connected to the first traces on the first substrate using a solder material.

According to another aspect of the present invention, there is provided a device comprising: a first substrate having a die attach region, a peripheral region, and a shield region between the die attach region and the peripheral region , wherein a protective layer covers the traces in the peripheral region, and wherein the protective layer does not extend into the die attach region and the shielded region; and a second substrate electrically connected to the a first substrate, the second substrate is located above the die attach area of the first substrate; wherein the die attach area corresponds to the first substrate located directly on the A region under the second substrate; wherein the occluded area extends from the boundary of the protective layer to the boundary of the die attach area; wherein the area of the occluded area is between that of the second substrate Between about 5% and about 18% of the area.

In the above device, the device further includes an underfill between the first substrate and the second substrate.

In the above device, wherein, the device further includes an underfill between the first substrate and the second substrate, wherein the underfill completely covers all of the shielding regions. described trace.

In the above device, wherein the device further comprises an underfill between the first substrate and the second substrate, wherein the underfill comprises a high molecular compound.

In the above device, wherein the second substrate includes an integrated circuit die.

In the above device, wherein the shielding distance between the edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μm.

In the above device, wherein the second substrate is attached to the first substrate using a bump-on-trace connection.

According to yet another aspect of the present invention, there is provided a method of forming a semiconductor device, the method comprising: providing a first substrate having traces formed on the first substrate; forming a protective layer over a portion of the first substrate; and attaching a second substrate to the first substrate; wherein a shielding region extends at a boundary of the protective layer and a periphery of the second substrate Between, the area of the shielding region is between about 5% and about 18% of the area of the second substrate.

In the above method, wherein, the method further includes arranging an underfill between the first substrate and the second substrate.

In the above method, wherein, the method further includes arranging an underfill between the first substrate and the second substrate, wherein the underfill completely covers all of the shielding regions. described trace.

In the above method, wherein the method further includes arranging an underfill between the first substrate and the second substrate, wherein the underfill includes a high molecular compound.

In the above method, wherein the second substrate includes an integrated circuit die.

In the above method, wherein the shielding distance between the edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μm.

Description of drawings

Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 shows an embodiment of a chip on a bump-on-trace (BOT) structure to form a flip-chip (FC) package;

Figures 2(a) to 2(c) illustrate methods and apparatus for solder masking trenches used in BOT structures to form embodiments of FC packages; and

3 shows a top view of bumps connected to traces within trench rings of solder mask used in a BOT structure.

4A-6B illustrate various plan and cross-sectional views of intermediate process steps according to some embodiments.

FIG. 7 is a flowchart illustrating a method of fabrication, according to some embodiments.

detailed description

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which the first component and the second component are formed in direct contact. An embodiment in which an additional component may be formed between such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and/or characters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe an element as shown. or the relationship of a component to another (or other) elements or components. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

As will be explained below, methods and apparatus are disclosed for solder masking trenches used in BOT structures to form semiconductor packages. A solder mask layer is formed over the traces and the substrate. Openings in the solder mask layer, called solder mask trenches, are formed to expose traces on the substrate. Connect the chip to the traces exposed in the trenches of the solder mask. Due to the formation of the solder mask trenches, the traces exposed in the trenches may have better grip, which reduces trace delamination failures of the semiconductor package.

1 is a schematic diagram of an illustrative embodiment of a chip 201 on a bump-on-trace (BOT) structure to form a flip-chip (FC) package. Substrate 206 may have multiple sublayers. The two sub-layers of substrate 206 shown in FIG. 1 are for purposes of illustration only, and not limitation. A plurality of balls 207 located under substrate 206 may form a ball grid array (BGA). Chip 201 is connected to substrate 206 by a plurality of interconnects, where each interconnect includes Cu stud bumps or studs 202 and solder bumps 203 . Solder bumps 203 are arranged on traces 204 formed on a substrate 206 . A solder mask 211 covering the traces is formed on the surface of the substrate 206 . An opening in the solder mask, referred to as a solder mask trench, is formed, which exposes the trace 204 . The space between chip 201 and substrate 206 may be filled with a compound, thereby forming encapsulation 205 .

Figure 2(a) shows an embodiment of a single solder mask trench 210 on a substrate 206, which may be any of the trenches in Figure 1, wherein the traces are exposed to the solder mask trench Groove 210 , and solder mask trench 210 constitutes a connection to chip 201 . Traces 204 are formed on the surface of substrate 206 . A solder mask layer 211 may be formed over the traces and on the surface of the substrate 206 covering the traces. Trenches may be opened in solder mask layer 211 to form solder mask trenches 210 , exposing traces 204 . The trenches have openings large enough that interconnects such as solder balls 203 can be positioned directly on traces contained in the openings. For example, the size of the solder mask trench is about the diameter of the solder bump. Trace 204 may connect to chip 201 through an interconnect. The interconnection may include solder bumps 203 and studs 202 such as Cu pillars, wherein solder balls 203 are disposed directly on traces 204 and surrounded by solder mask trenches. The structure shown in Fig. 2(a) is for the purpose of illustration only and is not meant to be limiting. Additional embodiments are contemplated.

FIG. 2( b ) shows a top view where post 202 is located on trace 204 surrounded by solder mask 211 . Chip 201 and substrate 206 are not shown in FIG. 2( b ).

Figure 2(c) shows an exemplary process for fabricating the embodiment shown in Figure 2(a). Details of the process shown in Figure 2(c) are explained below.

The process begins at step 220, where a substrate, such as substrate 206 in Figure 2(a), is provided. Substrate 206 may provide mechanical support for the package and an interface that allows external components to access devices within the package. Substrate 206 may include doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Other substrates may include multilayer substrates, gradient substrates, or hybrid orientation substrates. Substrate 206 may also be a laminate substrate formed as a stack of multiple thin layers of polymeric material such as bismaleimide triazine or the like.

Trace 204 may be located on a surface of substrate 206 . Traces 204 may be used to extend the footprint of the die. The width or diameter of the trace can be about the same as the ball (or bump) diameter, or can be almost 2 to 4 times narrower than the ball (or bump) diameter. For example, traces 204 may have a line width between approximately 10 μm and 40 μm and a trace pitch P between approximately 30 μm and 70 μm. Traces can have narrow, wide or tapered shapes. The shape of the terminals of the trace may be different from the shape of the body of the trace. The trace body may have a substantially constant thickness. The terminals of the trace and the body of the trace are formed as a whole, which is different from placing pads on the trace. The traces may have a length that is substantially longer than the ball (or bump) diameter. On the other hand, the connection pads may have a length or width similar to the ball or bump diameter.

There may be a plurality of traces on the substrate, each trace being electrically insulated from each other, and the spacing between two adjacent traces may be between about 10 μm and 40 μm.

As an example, traces 204 may include conductive materials such as Al, Cu, Au, alloys thereof, other materials, or combinations and/or layers thereof. Alternatively, traces 204 may include other materials. In some embodiments, a dielectric layer may cover portions of traces 204 . Traces 204 may be covered by a metal finish coated over traces 204, such as an organic thin film or a layer of a hybrid material such as Ni/Pd/Au.

Trace 204 and substrate are only connected by interfacial adhesion between them, which may not be sufficient grip force to form a strong connection between trace 204 and substrate 206 .

In step 221 , a solder mask layer, such as solder mask layer 211 shown in FIG. 2( a ), may be formed on the surface of substrate 206 , covering traces 204 as well as the surface of the substrate. The solder mask layer 211 can perform several functions including providing electrical insulation resistance between circuit traces on the substrate, chemical and corrosion resistance or protection, mechanical (scratch, abrasion) protection, boundaries on the solder surface, trace Additional gripping force on the wire, and improved dielectric reliability. The solder mask layer provides additional grip between the traces 204 and the substrate 206 because the solder mask, traces, and substrate form a sandwich structure where the solder mask and substrate "sandwich" the traces .

The solder mask layer 211 can be formed in a single step by screening a wet film on the substrate surface and then curing the wet film by an oven. The thickness of the solder mask layer 211 may be about 30 microns to 40 microns (typically about 35 microns). The solder mask layer may include a polymer material.

In step 223 , as shown in FIG. 2( a ), trenches may be opened in the solder mask layer 211 to form solder mask trenches 210 , thereby exposing the traces 204 . The trenches have openings large enough that interconnects such as solder balls 203 can be bonded directly on traces contained in the openings. The wider opening to accommodate the solder ball increases the strength of the connection between the solder ball and the trace. The size of the opening is thus flexible and can vary with the size of the solder balls used to connect to the traces. The solder mask layer 211 formed of a wet film may be sealed in a pattern to form the solder mask trenches 210 . For example, a solder mask layer with solder mask grooves may first be placed on a roll for printing onto a substrate. Alternatively, a photosensitive material may be used to pattern the solder mask trenches 210 into a cured film. Solder mask trenches 210 may be formed to expose traces 204 to further form appropriate electrical connections to the die to be mounted on the substrate.

Flux (not shown) may be applied to the traces. The flux is mainly used to help the flow of solder so that the solder balls 203 make good contact with the traces on the substrate. The flux may be applied by any of various methods including brushing or spraying. Fluxes typically have an acidic component that removes the oxide barrier from the solder surface, as well as adhesive properties that help prevent chips from moving onto the substrate surface during the assembly process.

In step 227 , as shown in FIG. 2( a ), chip 201 may be connected to trace 204 through the chip's interconnects. As shown in FIG. 2( a ), the interconnection may include solder bumps 203 and studs 202 such as Cu studs. The trenches have openings large enough that solder balls 203 can bond directly on traces contained in the openings.

The solder bumps 203 of the chip 201 may be arranged on the traces 204 exposed by the solder mask trenches. Solder bumps 203 may include a material such as tin, or other suitable material such as silver, lead-free tin, copper, combinations thereof, or the like. In embodiments where the solder bumps 203 are tin solder bumps, the solder bumps 203 may be formed by first forming a certain thickness (e.g., about 15 μm) by methods such as evaporation, electroplating, printing, solder transfer, or balling. ), followed by reflow to shape the material into the desired bump shape. Any suitable method of producing solder bumps 203 may alternatively be utilized.

Chips such as chip 201 shown in FIG. 2( a ) may be connected to traces 204 through solder bumps 203 and posts 202 . The studs 202 may be formed on the chip 201 . The post 202 may be a Cu post or other metal with a melting point higher than 300°C. Chip 201 may be aligned such that studs 202 are disposed on solder bumps 203 . A chip can be a memory chip or any other functional chip.

The studs 202 and the solder bumps 203 together form the chip's interconnects. Posts 202 and solder bumps 203 may be formed in any number of suitable shapes to avoid nearby components, to control connection areas between chip 201 and traces 204 , or for other suitable reasons. The shape of the interconnect can be circular, octagonal, rectangular, elongated hexagon (with two trapezoids at opposite ends of the elongated hexagon), oval, prismatic.

In step 231, a reflow process is performed. After chip 201 is bonded to the traces as shown in FIG. 2( a ), heat may be applied to chip 201 and substrate 206 to reflow solder balls 203 and form electrical connections between chip 201 and substrate 206 . For one embodiment, the heat may reach a temperature of about 220°C.

In step 233 , an underfill material, typically a thermosetting epoxy, may be dispensed into the gap between chip 201 and substrate 206 . A bead of thermosetting epoxy can be applied along one edge of the chip, where the epoxy is attracted under the chip by capillary action until the epoxy completely fills the gap between the chip and the substrate. It is important that the underfill material is evenly distributed in the gap.

A separate bead of epoxy may also be dispensed and bonded around the periphery of the chip 201 . The underfill epoxy and peripheral bonding epoxy are then cured by heating the substrate and chip to an appropriate curing temperature, which forms an encapsulation such as encapsulation 205 shown in FIG. 1 . Encapsulation 205 has filled the gap between chip 201 and substrate 206 . In this way, the process produces a mechanically as well as electrically bonded semiconductor chip assembly when the process ends.

FIG. 3 shows a top view of a substrate of a semiconductor package formed from a BOT structure. Except for region 301, the surface of the substrate may be covered by a solder mask. The solder mask can also cover the surface of the substrate in other shapes. A plurality of solder mask trenches 311 may be formed on the solder mask layer. The solder mask trenches surround the central region of the substrate and form a plurality of solder mask trench rings. The shape of the solder mask trenches conforms to the outline of the traces on the substrate. There may be other shapes than formed solder mask rings. Three such solder mask trench rings are formed in FIG. 3 . Other numbers of solder mask trench rings may be formed. A plurality of studs or interconnects such as 2021 and 2022 may be disposed on the traces exposed within the solder mask trenches. The pitch between two studs or two interconnects may be less than about 140 μm.

In other embodiments, the solder mask is removed from the die attach area (such as the area where a die or other substrate may be attached) and the occluded area (eg, the area immediately surrounding the die attach area). As explained in more detail below, the solder mask material will be removed such that the area directly under and immediately surrounding the die will be removed. The size of the area from which the solder mask material has been removed is greater than the size of the die. The area where the solder mask material was removed is sized such that the lateral area between the edge of the die and the edge of the solder mask allows the underfill material to completely fill the area between the die and the underlying substrate ( leaving no exposed traces) applied.

For example, in some cases where the lateral area between the edge of the die and the edge of the solder mask is too small, the underfill material may not completely fill the area between the die and the underlying substrate, allowing One or more voids are formed between the underlying substrates. In some cases where the lateral area between the edge of the die and the edge of the solder mask is too large, the traces may still be exposed. It has been found that by controlling the width of the distance between the edge of the die and the edge of the solder mask and/or controlling the ratio of the area of the area between the edge of the die and the edge of the solder mask to the area of the die, the bottom The filler may completely fill the area between the die and the underlying substrate and cover the traces, thereby providing protection for the electrical connections between the die and the underlying substrate and the traces on the underlying substrate.

It should be noted that the discussion herein refers to a die attached to a substrate for purposes of illustration to explain components of various embodiments. In other embodiments, the die may be another substrate such as a package, packaging substrate, interposer, die, printed circuit board, or the like. Similarly, for example, the underlying substrate may be a package, packaging substrate, interposer, die, printed circuit board, or the like.

Likewise, Figures 4A-6B show various intermediate stages in the process of forming some embodiments, where "A" is a plan view and "B" is a plan view along the corresponding "A" Cross-sectional view of line B-B. Referring first to FIGS. 4A and 4B , there are shown a plan view of the first substrate 402 and a cross-sectional view taken along line B-B in FIG. 4A . For example, first substrate 402 may be an integrated circuit die, packaging substrate, wafer, printed circuit board, interposer, or the like. In some embodiments, a BOT configuration is used. For example, trace 404 is shown in FIGS. 4A and 4B . In general, traces 404 route electrical signals to desired locations and/or are used to extend the footprint of the die. The width or diameter of the trace 404 may be about the same as the ball (or bump) diameter, or may be almost 2 to 4 times narrower than the ball (or bump) diameter. For example, traces 404 may have a line width between approximately 10 μm and 40 μm and a trace pitch P between approximately 30 μm and 70 μm. Traces can have narrow, wide or tapered shapes. In some embodiments, a terminal end of a trace may have a different shape than the main body of the trace, or the main body of the trace may have a substantially constant thickness. The termination of the trace is formed integrally with the body of the trace, as opposed to placing a pad on the trace. The traces may have a length that is substantially longer than the ball (or bump) diameter. On the other hand, the connection pads may have a length or width similar to the ball or bump diameter.

As an example, in some embodiments, traces 404 may include conductive materials such as Al, Cu, Au, alloys thereof, other materials, or combinations and/or layers thereof. Alternatively, traces 404 may include other materials. Trace 404 may be covered by a metal finish, such as an organic thin film or a layer of a hybrid material such as Ni/Pd/Au, coated on trace 404 . In some embodiments, the pitch between adjacent traces may be between about 10 μm and 40 μm.

4A and 4B also show a protective layer 406 . Generally, the protective layer 406 provides protection from environmental contaminants, electrical insulation resistance between circuit traces on the substrate, chemical and corrosion resistance or protection, mechanical (scratch, abrasion) protection, boundary on the solder surface , additional grip on traces and/or substrates, and improved dielectric reliability. For example, in some embodiments, protective layer 406 is a polymer or other dielectric material. For example, in some embodiments, protective layer 406 is a polymer formed by sealing or spin coating, patterning, and subsequent curing.

The protective layer 406 covers portions of the traces 404 , such as portions of the traces located in the peripheral region of the first substrate 402 . For example, in the embodiment shown in FIG. 4A , protective layer 406 is spaced apart from and formed around die attach area 408 , indicated by the dashed outline in FIG. 4A . As discussed in more detail below, die attach area 408 represents an area on which another substrate is to be disposed. The protective layer 406 will protect the traces 404 from external environmental contaminants and adjust the dimensions of the protective layer 406 to allow the underfill to completely fill the area between the die and the first substrate 402 while also covering the exposed traces 404. The protective layer 406 may have a thickness of about 30 μm to about 40 μm, such as about 35 μm.

Referring now to FIGS. 5A and 5B , the first substrate 402 of FIGS. 4A and 4B is shown after the second substrate 520 has been attached to the first substrate 402 , according to some embodiments. For example, the second substrate 520 may be a die, a substrate, a wafer, a packaging substrate, a printed circuit board, or the like. The second substrate 520 is electrically connected to the first substrate through electrical connections 522 . In some embodiments, electrical connections 522 include conductive posts 522a (eg, copper posts) and solder material 522b connected to conductive posts 522a, although other electrical connections may be used.

In some embodiments, the first substrate 402 is an integrated circuit die and the second substrate 520 is a wafer, and these substrates are bonded in a flip chip chip scale package (FCCSP). The wafer can then be singulated to form individual packages. However, other configurations may be used.

As shown in FIGS. 5A and 5B , a occlusion region (KOR) 524 extends around the second substrate 520 and is located between the second substrate 520 and the protective layer 406 . In some embodiments, the KOR 524 includes a region where the inner edge of the protective layer 406 is spaced an occlusion distance (KOD) D ₁ from the edge of the second substrate 520 . In some embodiments, the area of the KOR 524 is between about 5% and about 18% of the area of the second substrate 520 . For example, the area of the second substrate 520 is width W ₁ times length L ₁ , and the ratio of the area of KOR 524 to the area of second substrate 520 (eg, width W ₁ times length L ₁ ) is about 1:20 Between about 9:50. Additionally, in some embodiments, the blocking distance D ₁ is greater than or equal to about 420 μm.

It has been found that using these guidelines (the ratio of the area of the KOR 524 to the area of the second substrate 520 and the minimum size of the shadowing distance), a sufficient distance is provided between the edge of the protective layer 406 and the edge of the second substrate 520 to allow The underfill material is applied such that the underfill material will be substantially void-free and cover exposed traces in the KOR524. As discussed above, having a smaller distance can result in poor fillability between the first substrate 402 and second substrate 520 , creating voids, while having a larger distance can result in exposed traces in the KOR 524 . Maintaining the shading distance and KOR 524 as discussed above resolves these issues, preventing or reducing the occurrence of voids between the first substrate 402 and the second substrate 520 , and providing better coverage of exposed traces in the KOR 524 .

6A and 6B illustrate the first substrate 402 and the second substrate 520 between the first substrate 402 and the second substrate 520 after an underfill 650 according to some embodiments. In some embodiments, the underfill 650 includes a polymer, a thermosetting epoxy, or the like dispensed into the gap (eg, KOR 524 ) between the second substrate 520 and the protective layer 406 . For example, in some embodiments, the underfill material is a polymer compound with a silicon dioxide fill material. A bead of underfill 650 may be applied along one edge of the chip, wherein the underfill 650 is attracted under the chip by capillary action until the underfill 650 completely fills the gap between the first substrate 402 and the second substrate 520. the gap between.

Figure 7 is a flow diagram illustrating the process of fabrication, according to some embodiments. The process begins at step 702, where a first substrate is provided such that the first substrate includes a die attach region, a shield region, and a peripheral region, wherein a protective layer protects traces in the peripheral region, such as those referenced above 4A and 4B are discussed. In step 704, a second substrate is provided, and in step 706, the second substrate is attached to the first substrate, such as discussed above with reference to FIGS. 5A and 5B. The first substrate is attached to the second substrate in a manner to provide a KOR region and shading distance between the first substrate and the closest edge of the protective layer. In step 708, an underfill is disposed between the first substrate and the second substrate. Maintaining the KOR and shadow distance as discussed above allows the underfill to be placed with little void while providing protection for the traces within the KOR.

In an embodiment, a device is provided. The device includes a first substrate having traces formed thereon. The first substrate has a die attach region, a shading region surrounding a periphery of the die attach region, and a peripheral region surrounding a periphery of the shading region. The first substrate also includes a protective layer over the traces in the peripheral region. The second substrate is electrically connected to the first substrate in the die attach area, and an underfill is interposed between the first substrate and the second substrate, the underfill extending over the traces located in the shielded area , wherein the area of the shielding region is between about 5% and about 18% of the area of the second substrate.

In another embodiment, a device is provided. The device includes a first substrate having a die attach region, a peripheral region, and a shield region between the die attach region and the peripheral region, wherein the protective layer covers traces in the peripheral region, And wherein, the protective layer does not extend into the die attach area and the shadow area. The second substrate is electrically connected to the first substrate such that the second substrate is located over the die attach region of the first substrate. The die attach region corresponds to a region of the first substrate directly beneath the second substrate, and the shadow region extends from a boundary of the protective layer to a boundary of the die attach region. The area of the shadow region is between about 5% and about 18% of the area of the second substrate.

In yet another embodiment, a method of forming a semiconductor device is provided. The method includes providing a first substrate having traces formed thereon, and forming a protective layer over portions of the first substrate. A second substrate is attached to the first substrate. A shading region extends between a boundary of the protective layer and a periphery of the second substrate, wherein an area of the shading region is between about 5% and about 18% of an area of the second substrate.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand aspects of the invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and changes to the present invention without departing from the spirit and scope of the present invention .

Claims (10)

1. a device, including:

First substrate; there is the trace formed on described first substrate; described first substrate has tube core attachment regions, the peripheral blocked area around described tube core attachment regions and the peripheral external zones around described blocked area, and described first substrate has the protective layer covering described trace being arranged in described external zones；

Second substrate, is electrically connected to described first substrate in described tube core attachment regions；And

Bottom filler, between described first substrate and described second substrate, described bottom filler extends in and is arranged in above the described trace of described blocked area；

Wherein, the area of described blocked area between described second substrate area about 5% and about between 18%.

2. device according to claim 1, wherein, described second substrate includes integrated circuit lead.

3. device according to claim 1, wherein, the distance of blocking between edge and the immediate edge of described protective layer of described second substrate equals to or more than about 420 μm.

4. device according to claim 1, wherein, described bottom filler includes the macromolecular compound with silica filler material.

5. device according to claim 1, wherein, described bottom filler is completely covered the described trace being arranged in described blocked area and described tube core attachment regions.

6. device according to claim 1, wherein, described second substrate uses Bump-on-trace connector to be attached to described first substrate.

7. device according to claim 1, wherein, described second substrate includes the copper post of the first trace using solder material to be connected directly on described first substrate.

8. a device, including:

First substrate; having tube core attachment regions, external zones and the blocked area between described tube core attachment regions and described external zones, wherein, protective layer covers the trace in described external zones; and wherein, described protective layer does not extend in described tube core attachment regions and described blocked area；And

Second substrate, is electrically connected to described first substrate, and described second substrate is positioned at above the described tube core attachment regions of described first substrate；

Wherein, described tube core attachment regions corresponding to described first substrate be located immediately at the region below described second substrate；

Wherein, described blocked area extends to the border of described tube core attachment regions from the border of described protective layer；

Wherein, the area of described blocked area between described second substrate area about 5% and about between 18%.

9. device according to claim 8, also includes the bottom filler between described first substrate and described second substrate.

10. the method forming semiconductor device, described method includes:

The first substrate, described first substrate is provided to have the trace formed on described first substrate；

Upper at described first substrate forms protective layer；And

Second substrate is attached to described first substrate；

Wherein, blocked area extends between the border of described protective layer and the periphery of described second substrate, the area of described blocked area between described second substrate area about 5% and about between 18%.