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CN105762087B - Method and apparatus for Bump-on-trace chip package - Google Patents

Method and apparatus for Bump-on-trace chip package Download PDF

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Publication number
CN105762087B
CN105762087B CN201410800491.8A CN201410800491A CN105762087B CN 105762087 B CN105762087 B CN 105762087B CN 201410800491 A CN201410800491 A CN 201410800491A CN 105762087 B CN105762087 B CN 105762087B
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China
Prior art keywords
substrate
trace
semiconductor devices
area
tube core
Prior art date
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Application number
CN201410800491.8A
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Chinese (zh)
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CN105762087A (en
Inventor
林彦良
黄昶嘉
郭庭豪
吴胜郁
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/459,047 external-priority patent/US9165796B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105762087A publication Critical patent/CN105762087A/en
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Publication of CN105762087B publication Critical patent/CN105762087B/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention provides the method and apparatus for the first substrate to be attached to the second substrate.In some embodiments, the first substrate has the protective layer for such as solder mask being located at around tube core attachment regions, and in tube core attachment regions, the first substrate is attached to the second substrate.Blocked area (for example, region between the second substrate and protective layer) is positioned at the region of the second substrate perimeter, wherein does not form or remove protective layer.Adjust the size of blocked area; so that enough gaps are present between the second substrate and protective layer so that bottom filler to be arranged between the first substrate and the second substrate; gap is reduced or prevented simultaneously, and at the same time the trace in occlusion area is covered by bottom filler.The invention further relates to the method and apparatus for Bump-on-trace chip package.

Description

Method and apparatus for Bump-on-trace chip package
Prioity claim and cross reference
The application is entitled " the method and apparatus collection of the entitled chip package of submission submitted on April 18th, 2012 At circuit die.The high-molecular compound of packing material.Patent application 13/th of the area between institute Chip Packaging " 450, No. 191 part continuation applications, entire contents are hereby expressly incorporated by reference.
Technical field
The present invention relates to integrated circuit device, more particularly, to the method and dress for Bump-on-trace chip package It sets.
Background technique
Integrated circuit or chip are made of thousands of active and passive device (such as transistor and capacitor).These Device is initially isolated from each other, and interconnects these devices later to form integrated circuit.Connecting-piece structure is further formed for collecting At circuit, connecting-piece structure may include the landing pad formed on the surface of the circuit or metal coupling.Pass through landing pad Or electrical connector is made so that chip is connected to package substrate or another tube core in metal coupling.Normally, lead can be used to connect It closes (WB) or flip-chip (FC) encapsulation technology and chip is assembled to such as Pin-Grid Array (PGA) or ball grid array (BGA) Packaging part in.
Flip-chip (FC) encapsulation technology can be used Bump-on-trace (BOT) structure and chip be connected to package substrate, Wherein, connector is made so that chip to be connected to the metal trace of package substrate or tube core by metal coupling.BOT structure is micro- Electronic packaging industry provides low cost substitution.However, there is integrity problem in BOT structure as substrat structure is more and more thinner.
When using BOT structure, the trace of the weld tabs of chip on the package substrate will be used for by reflux technique. When convex block is connected to substrate and is cooled to room temperature by counterflow condition, the heating power as caused by thermal expansion coefficient (CTE) mismatch It drives substrate to reduce and leads to the twist relative of each convex block.Once stress level is raised above viscous between substrate and trace Trace removing failure will occur for standardization.
Summary of the invention
In order to solve the problems in the existing technology, the present invention provides a kind of devices, comprising: the first substrate has The trace formed on first substrate, first substrate have tube core attachment regions, around the outer of the tube core attachment regions The external zones of the blocked area and the periphery around the blocked area enclosed, first substrate, which has, to be located in the external zones Cover the protective layer of the trace；Second substrate, first substrate being electrically connected in the tube core attachment regions；And bottom Filler, between first substrate and second substrate, the bottom filler is extended in positioned at the blocked area In the trace above；Wherein, the area of the blocked area between second substrate area about 5% and about 18% it Between.
In the devices set out in the foregoing, wherein second substrate includes integrated circuit die.
In the devices set out in the foregoing, wherein between the edge of second substrate and the immediate edge of the protective layer It blocks distance and is equal to or greater than about 420 μm.
In the devices set out in the foregoing, wherein the bottom filler includes the macromolecule chemical combination with silica filler material Object.
In the devices set out in the foregoing, wherein the bottom filler is completely covered positioned at the blocked area and tube core attachment The trace in area.
In the devices set out in the foregoing, wherein second substrate is attached to first substrate using Bump-on-trace connector.
In the devices set out in the foregoing, wherein second substrate includes that first substrate is connected directly to using solder material On the first trace copper post.
According to another aspect of the present invention, a kind of device is provided, comprising: the first substrate has tube core attachment regions, periphery Area and the blocked area between the tube core attachment regions and the external zones, wherein protective layer covers in the external zones Trace, and wherein, the protective layer does not extend in the tube core attachment regions and the blocked area；And second substrate, It is electrically connected to first substrate, second substrate is located above the tube core attachment regions of first substrate；Wherein, institute State the region below second substrate that tube core attachment regions correspond to first substrate；Wherein, described to block Area extends to the boundary of the tube core attachment regions from the boundary of the protective layer；Wherein, the area of the blocked area is between described Between about the 5% of the area of second substrate and about 18%.
In the devices set out in the foregoing, wherein the device further includes between first substrate and second substrate Bottom filler.
In the devices set out in the foregoing, wherein the device further includes between first substrate and second substrate Bottom filler, wherein the trace in the blocked area is completely covered in the bottom filler.
In the devices set out in the foregoing, wherein the device further includes between first substrate and second substrate Bottom filler, wherein the bottom filler includes the high-molecular compound with silica filler material.
In the devices set out in the foregoing, wherein second substrate includes integrated circuit die.
In the devices set out in the foregoing, wherein between the edge of second substrate and the immediate edge of the protective layer It blocks distance and is equal to or greater than about 420 μm.
In the devices set out in the foregoing, wherein second substrate is attached to first substrate using Bump-on-trace connector.
According to another aspect of the invention, a kind of method for forming semiconductor devices is provided, which comprises provide First substrate, first substrate have the trace formed on first substrate；In the upper of first substrate Form protective layer；And the second substrate is attached to first substrate；Wherein, blocked area extends in the boundary of the protective layer Between the periphery of second substrate, about 5% peace treaty of the area of the blocked area between the area of second substrate Between 18%.
In the above-mentioned methods, wherein the method also includes bottom filler is arranged in first substrate and described Between second substrate.
In the above-mentioned methods, wherein the method also includes bottom filler is arranged in first substrate and described Between second substrate, wherein the trace in the blocked area is completely covered in the bottom filler.
In the above-mentioned methods, wherein the method also includes bottom filler is arranged in first substrate and described Between second substrate, wherein the bottom filler includes the high-molecular compound with silica filler material.
In the above-mentioned methods, wherein second substrate includes integrated circuit die.
In the above-mentioned methods, wherein between the edge of second substrate and the immediate edge of the protective layer It blocks distance and is equal to or greater than about 420 μm.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, from it is described in detail below can best understanding each aspect of the present invention.It should be noted that According to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, the ruler of all parts It is very little to arbitrarily increase or reduce.
Fig. 1 shows the chip in Bump-on-trace (BOT) structure to form the embodiment of flip-chip (FC) packaging part；
Fig. 2 (a) to Fig. 2 (c) shows the method and apparatus of the solder mask trench used in BOT structure to be formed The embodiment of FC packaging part；And
Fig. 3 shows the multiple convex of the trace being connected in multiple solder mask trench rings used in BOT structure The top view of block.
Fig. 4 A to Fig. 6 B shows each plan view and sectional view of intervening process steps in accordance with some embodiments.
Fig. 7 is the flow chart of the method in accordance with some embodiments for showing manufacture.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", " lower part ", " ... On ", the spatially relative terms such as " top " to be to describe an element or component and another (or other) member as shown in the figure The relationship of part or component.Other than orientation shown in figure, spatially relative term is intended to include device in use or operation Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space as used herein Relative descriptors can similarly make corresponding explanation.
As will be described hereinafter, the method and apparatus for solder mask trench used in BOT structure are disclosed To form semiconductor package part.Solder mask layer is formed on trace and substrate.The solder for forming referred to as solder mask trench is covered The opening of mold layer, to expose the trace on substrate.Chip is connected to the trace being exposed in solder mask trench.Due to solder The formation of mask trench, the trace being exposed in groove can have better grasp force, and which reduce semiconductor package parts Trace removes failure.
Fig. 1 is the chip 201 in Bump-on-trace (BOT) structure to form the illustrative reality of flip-chip (FC) packaging part Apply the schematic diagram of example.Substrate 206 can have multiple sublayers.Two sublayers of substrate 206 shown in Fig. 1 are merely to explanation Purpose, and do not lie in limitation.Multiple balls 207 positioned at 206 lower section of substrate can form ball grid array (BGA).Chip 201 is logical It crosses multiple interconnection pieces and is connected to substrate 206, wherein each interconnection piece includes that Cu column convex block or binding post 202 and solder are convex Block 203.Solder projection 203 is arranged on trace 204, and trace 204 is formed on substrate 206.It is formed on the surface of substrate 206 Cover the solder mask 211 of trace.Form the opening of solder mask, referred to as solder mask trench, opening exposure trace 204. The interval between chip 201 and substrate 206 can be filled with compound, to form encapsulated member 205.
Fig. 2 (a) shows the embodiment of the single solder mask trench 210 on substrate 206, and solder mask trench 210 can To be any groove in Fig. 1, wherein trace is exposed to solder mask trench 210, and solder mask trench 210 is constituted extremely The connection of chip 201.Trace 204 is formed on the surface of substrate 206.It can be formed on trace and on the surface of substrate 206 Cover the solder mask layer 211 of trace.Groove can be opened in solder mask layer 211 to form solder mask trench 210, from And expose trace 204.Groove has sufficiently large opening, so that the interconnection piece of such as solder ball 203 can be positioned directly On the trace for including in the opening.For example, the size of solder mask trench is the diameter of about solder projection.Trace 204 can lead to It crosses interconnection piece and is connected to chip 201.Interconnection piece may include the binding post 202 of solder projection 203 and such as Cu column, wherein weldering Pellet 203 is directly arranged on trace 204 and is surrounded by solder mask trench.Structure shown in Fig. 2 (a) is merely to illustrate Purpose, and do not lie in limitation.It is contemplated that additional embodiment.
Fig. 2 (b) shows top view, wherein binding post 202 is located on trace 204, and trace 204 is enclosed by solder mask 211 Around.Chip 201 and substrate 206 are not shown in Fig. 2 (b).
Fig. 2 (c) shows the illustrative processes of embodiment shown in manufacture Fig. 2 (a).It is explained below in Fig. 2 (c) and shows The details of technique out.
Technique starts from step 220, wherein provides the substrate of the substrate 206 in such as Fig. 2 (a).Substrate 206 can be Packaging part provides mechanical support and interface, which allows the device in external module access encapsulation part.Substrate 206 may include The active layer of doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate.Other substrates may include MULTILAYER SUBSTRATE, Gradient substrate or hybrid orientation substrate.Substrate 206, which can also be, is formed as polymer material (such as Bismaleimide Triazine Deng) multiple thin layers stack laminated substrates.
Trace 204 can be located on the surface of substrate 206.Trace 204 can be used for extending the area of coverage of tube core.Trace Width or diameter can be about the same with ball (or convex block) diameter, or can be almost 2 to 4 times narrower than ball (or convex block) diameter.Example Such as, trace 204 can have the line width between about 10 μm and 40 μm and the trace between about 30 μm and 70 μm Pitch P.Trace can have narrow/wide or tapered form.The shape of the terminal of trace can be with the shape of the main body of trace not Together.Trace main body can have substantially constant thickness.The terminal of trace and the main body of trace are formed as an entirety, this is not It is same as pad being arranged on trace.Trace can have the length for being substantially longer than ball (or convex block) diameter.On the other hand, even Connecing pad can have the length or width similar with ball or bump diameter.
May exist a plurality of trace on substrate, every trace is electrically insulated from each other, and between two neighbouring traces Interval can be between about 10 μm and 40 μm.
As example, trace 204 may include such as Al, Cu, Au, the conductive material of their alloy, other materials or Their combination and/or multilayer.Optionally, trace 204 may include other materials.In some embodiments, dielectric layer can be with Cover some parts of trace 204.Trace 204 can be covered by the metal finish being coated on trace 204, such as organic film Or the layer of mixing material (such as Ni/Pd/Au).
Trace 204 and substrate only pass through the connection of the Interface Adhesion between them, and Interface Adhesion may not be to be enough to constitute mark The grasp force of strong ties between line 204 and substrate 206.
In step 221, solder mask layer 211 shown in such as Fig. 2 (a) can be formed on the surface of substrate 206 Solder mask layer, solder mask layer covers the surface of trace 204 and substrate.Solder mask layer 211 can execute several function Can, including providing the electrical isolation resistance between the circuit trace on substrate, anti-chemical and anticorrosive or protection, mechanical (scratch, mill Damage) protection, the boundary on solder surface, the additional grasp force on trace and improved dielectric reliability.Because solder is covered Mould, trace and substrate form sandwich, wherein solder mask and substrate " clamp " trace, so solder mask layer provides mark Additional grasp force between line 204 and substrate 206.
By the way that wet film closing (screening) on the surface of a substrate, is then passed through the wet film of oven for solidifying, Ke Yi Solder mask layer 211 is formed in single step.The thickness of solder mask layer 211 can be about 30 microns to 40 microns (usually About 35 microns).Solder mask layer may include polymer material.
In step 223, as shown in Fig. 2 (a), groove can be opened in solder mask layer 211 to form solder mask Groove 210, thus exposure trace 204.Groove has sufficiently large opening, so that the interconnection piece of such as solder ball 203 can To be directly bonded on the trace in opening included.The wider opening for accommodating solder ball can increase between solder ball and trace Bonding strength.Therefore the size of opening is flexible and can change with the size of the solder ball for being connected to trace Become.The solder mask layer 211 formed by wet film can close into a pattern to form solder mask trench 210.For example, having The solder mask layer of solder mask trench can be initially disposed on roller to be printed on substrate.Optionally, light-sensitive material can be with For by the patterned cured film of solder mask trench 210.Solder mask trench 210 can be formed to expose trace 204, from And it is further formed and is electrically connected with by the appropriate of tube core of installation on substrate.
Scaling powder (not shown) can be applied to trace.Scaling powder serves mainly to facilitate the flowing of solder, so that weldering Pellet 203 and the trace contacts on substrate are good.It can be helped with any method application for including the various methods brushed or sprayed Solder flux.Scaling powder usually has acid ingredient and adhesion, and acid ingredient removes oxide barrier part from solder surface, and attached Property help that chip is prevented to be moved on substrate surface during packaging technology.
In step 227, as shown in Fig. 2 (a), chip 201 can be connected to by trace 204 by the interconnection piece of chip. As shown in Fig. 2 (a), interconnection piece may include the binding post 202 of solder projection 203 and such as Cu column.Groove has sufficiently large Opening, so that solder ball 203 can be directly bonded on the trace in opening included.
The solder projection 203 of chip 201 can be arranged on the trace 204 by solder mask trench exposure.Solder Convex block 203 may include the material or silver, other suitable materials without slicker solder, copper, their combination etc. of tin Material.In the embodiment that solder projection 203 is tin solder convex block, solder projection 203 can be formed by following steps: logical first It crosses such as evaporation, be electroplated, the tin layers of printing, solder transfer or method formation certain thickness (for example, about 15 μm) of plant ball, then Implement reflux with by material forming be desired convex block shape.It can be optionally with any suitable of production solder projection 203 Method.
The chip of chip 201 shown in such as Fig. 2 (a) can be connected to by solder projection 203 and binding post 202 Trace 204.Binding post 202 can be formed on chip 201.Binding post 202 can be Cu column or with higher than 300 fusing point having Other metals.Chip 201 can be aligned, so that binding post 202 is arranged on solder projection 203.Chip, which can be, to be deposited Store up chip or any other functional chip.
Binding post 202 and solder projection 203 are formed together the interconnection piece of chip.Binding post 202 and solder projection 203 can be with Be formed as a variety of suitable shapes to avoid the bonding pad or other conjunctions between neighbouring component, control chip 201 and trace 204 Suitable reason.The shape of interconnection piece can be circle, octagon, rectangle, elongated hexagon (in the opposite end of elongated hexagon Tool is there are two trapezoidal), ellipse, prismatic.
In step 231, implement reflux technique.It, can be with after chip 201 is bonded to the trace as shown in Fig. 2 (a) Apply heat to chip 201 and substrate 206, so that solder ball 203 is flowed back and is formed between chip 201 and substrate 206 and be electrically connected Fitting.For one embodiment, heat can achieve about 220 1 temperature.
In step 233, underfill (usually thermosetting epoxy resin) can be assigned to chip 201 and lining In gap between bottom 206.The globule of thermosetting epoxy resin can be applied along an edge of chip, wherein asphalt mixtures modified by epoxy resin Rouge is attracted to beneath chips through capillary action, until epoxy resin is filled up completely the gap between chip and substrate.Bottom Packing material is evenly distributed in gap and is important.
The individual globule of epoxy resin can also distribute and be bonded on the peripheral of chip 201.Then, pass through by Substrate and chip are heated to solidification temperature appropriate to solidify underfill epoxy and periphery engagement epoxy resin, are formed The encapsulated member of all encapsulated members as shown in Figure 1 205.Between encapsulated member 205 has had been filled between chip 201 and substrate 206 Gap.In this way, at the end of technique, which generates the semiconductor chip assembly for mechanically engaging and electrically engaging.
Fig. 3 shows the top view of the substrate of the semiconductor package part formed by BOT structure.Other than region 301, lining The surface at bottom can be covered by solder mask.Solder mask can also cover the surface of substrate with other shapes.In solder mask It could be formed with multiple solder mask trench 311 on layer.Solder mask trench surrounds the center of substrate and forms multiple welderings Expect mask trench ring.The shape of solder mask trench is consistent with the profile of the trace on substrate.There may be other shapes, without It is the solder mask ring to be formed.Such solder mask trench ring there are three being formed in Fig. 3.It could be formed with other quantity Solder mask trench ring.Such as 2021 and 2022 multiple binding posts or interconnection piece, which can be arranged in, is exposed to solder mask trench On interior trace.Pitch between two binding posts or two interconnection pieces can be less than about 140 μm.
In other embodiments, from tube core attachment regions (region that such as tube core or other substrates can be attached) and blocked area (for example, directly about region of tube core attachment regions) removes solder mask.It explains in greater detail below, removal solder is covered Mold materials so that by region of the removal below tube core and directly about region.Eliminate solder mask material The size in the region of material is greater than the size of tube core.The size for eliminating the region of solder mask material is determined, so that tube core Edge and solder mask edge between transverse area allow underfill to be filled up completely tube core and following lining The mode (not leaving exposed trace) in the region between bottom applies.
For example, under the too small some cases of transverse area between the edge of tube core and the edge of solder mask, bottom Packing material may region between not completely filled tube core and following substrate, thus allow tube core and following substrate it Between form one or more gaps.The too big some cases of transverse area between the edge of tube core and the edge of solder mask Under, trace may still expose.It has been found that passing through the width at the distance between the edge at the edge and solder mask that control tube core And/or control tube core edge and solder mask edge between region area and tube core area ratio, bottom is filled out It fills the region that object can be filled up completely between tube core and following substrate and covers trace, to be tube core and following substrate Between electrical connector and following substrate on trace provide protection.
It should be noted that for illustrative purposes to explain the component of each embodiment, discussion in this is related to being attached to lining The tube core at bottom.In other embodiments, tube core can be such as packaging part, package substrate, intermediary layer, tube core, printed circuit board Deng another substrate.Similarly, for example, following substrate can be packaging part, package substrate, intermediary layer, tube core, printed circuit Plate etc..
Similarly, Fig. 4 A to Fig. 6 B shows each intermediate stage in the technique to form some embodiments, wherein " A " Figure is plan view, and it is sectional view along the line B-B of corresponding " A " figure that " B " figure, which is flat figure,.With reference first to Fig. 4 A and Fig. 4 B, Show the plan view of the first substrate 402 and the sectional view along the line B-B interception in Fig. 4 A.For example, the first substrate 402 can be with It is integrated circuit die, package substrate, wafer, printed circuit board, intermediary layer etc..In some embodiments, it is configured using BOT. For example, Fig. 4 A and Fig. 4 B show trace 404.Normally, electric signal is routed to desired locations and/or is used to expand by trace 404 Open up the area of coverage of tube core.The width or diameter of trace 404 can be about the same with ball (or convex block) diameter, or can almost compare Ball (or convex block) diameter is 2 to 4 times narrow.For example, trace 404 can have line width and Jie between about 10 μm and 40 μm Trace pitch P between about 30 μm and 70 μm.Trace can have narrow/wide or tapered form.In some embodiments, mark The terminal of line, which can have the shape or trace main body different from the main body of trace, can have substantially constant thickness. The terminal of trace and the main body of trace are formed as an entirety, this is different from for pad being arranged on trace.Trace can have It is substantially longer than the length of ball (or convex block) diameter.On the other hand, connection pad can have similar with ball or bump diameter Length or width.
As example, in some embodiments, trace 404 may include such as Al, Cu, Au, they alloy conduction Material, other materials or their combination and/or multilayer.Optionally, trace 404 may include other materials.Trace 404 can be with By the metal finish covering being coated on trace 404, metal finish such as organic film or mixing material (such as Ni/Pd/Au) Layer.In some embodiments, the pitch between neighbouring trace can be between about 10 μm and 40 μm.
Fig. 4 A and Fig. 4 B also show protective layer 406.Normally, protective layer 406 provide prevent the pollution of the environment object protection, Electrical isolation resistance, anti-chemical and anticorrosive or protection, mechanical (scratch, abrasion) protection, weldering between circuit trace on substrate Boundary, trace on material surface and/or additional grasp force and improved dielectric reliability on substrate.For example, some In embodiment, protective layer 406 is polymer or other dielectric materials.For example, in some embodiments, protective layer 406 is to pass through Closing or spin coating, patterning and the subsequent polymer being formed by curing.
Protective layer 406 covers the part of trace 404, the part in the perimeter region of the first substrate 402 of such as trace. For example, in the embodiment as shown in figure 4a, protective layer 406 divides with the tube core attachment regions 408 indicated by the dotted outline in Fig. 4 A It separates and is formed in around tube core attachment regions 408.It discusses in greater detail below, tube core attachment regions 408 indicate on it It will arrange the region of another substrate.Protective layer 406 will protect trace 404 from the influence of ambient environmental contaminants and adjust guarantor The size of sheath 406 is to allow bottom filler to be filled up completely the region between tube core and the first substrate 402, while also covering is sudden and violent The trace 404 of dew.The thickness of protective layer 406 can be about 30 μm to about 40 μm, such as about 35 μm.
Referring now to Fig. 5 A and Fig. 5 B, shows and in accordance with some embodiments have been attached to first in the second substrate 520 The first substrate 402 of Fig. 4 A and Fig. 4 B after substrate 402.For example, the second substrate 520 can be tube core, substrate, wafer, envelope Fitted lining bottom, printed circuit board etc..Second substrate 520 is electrically connected to the first substrate by electrical connector 522.In some embodiments In, electrical connector 522 includes conductive column 522a (for example, copper post) and is connected to the solder material 522b of conductive column 522a, still Other electrical connectors can be used.
In some embodiments, the first substrate 402 is integrated circuit die, and the second substrate 520 is wafer, these substrates It is bonded in flip-chip chip scale package (FCCSP).Wafer can then be divided to form individual packaging part.However, Other configurations can be used.
As fig. 5 a and fig. 5b, blocked area (KOR) 524 is extended in around the second substrate 520 and is located at the second substrate Between 520 and protective layer 406.In some embodiments, KOR 524 includes the inward flange and the second substrate 520 of protective layer 406 Edge, which is spaced apart, blocks distance (KOD) D1Region.In some embodiments, the area of KOR 524 is the face of the second substrate 520 Between long-pending about 5% to about 18%.For example, the area of the second substrate 520 is width W1Multiplied by length L1, the area of KOR 524 with The area of second substrate 520 is (for example, width W1Multiplied by length L1) ratio between about 1:20 between about 9:50.In addition, one In a little embodiments, distance D is blocked1Greater than or equal to about 420 μm.
It has been found that (ratio of the area of the area of KOR 524 and the second substrate 520 and being blocked using these policies The minimum dimension of distance), enough distances are provided between the edge of protective layer 406 and the edge of the second substrate 520 to allow Apply underfill, so that underfill is by substantially tight and covers exposure in KOR 524 Trace.As discussed above, there is lesser distance can lead to the filling energy between the first substrate 402 and the second substrate 520 Power is poor, to generate gap, and there is biggish distance can lead to the exposure of the trace in KOR 524.Keep as discussed above Block distance and KOR 524 solves these problems, to prevent or reduce between the first substrate 402 and the second substrate 520 Gap appearance, and provide the more preferable covering of the exposure trace in KOR 524.
Fig. 6 A and Fig. 6 B show it is in accordance with some embodiments between the first substrate 402 and the second substrate 520 bottom of between The first substrate 402 and the second substrate 520 after portion's filler 650.In some embodiments, bottom filler 650 includes point Polymer, the thermosetting epoxy resin being fitted in the gap (for example, KOR 524) between the second substrate 520 and protective layer 406 Deng.For example, in some embodiments, underfill is the high-molecular compound with silica filler material.It can be with Apply the globule of bottom filler 650 along an edge of chip, wherein bottom filler 650 is inhaled through capillary action Beneath chips are guided to, until bottom filler 650 is filled up completely the gap between the first substrate 402 and the second substrate 520.
Fig. 7 is the flow chart of the technique in accordance with some embodiments for showing manufacture.The technique starts from step 702, wherein The first substrate is provided, so that the first substrate includes tube core attachment regions, blocked area and external zones, wherein protective layer protection is outer The trace in area is enclosed, is such as discussed above by reference to Fig. 4 A and Fig. 4 B.In step 704, the second substrate is provided, and in step In 706, the second substrate is attached to the first substrate, is such as discussed above by reference to Fig. 5 A and Fig. 5 B.In one way by first Substrate is attached to the second substrate, to provide the area KOR between the first substrate and the immediate edge of protective layer and block distance. In step 708, bottom filler is arranged between the first substrate and the second substrate.Keep KOR as discussed above and screening Gear distance allows for bottom filler to be arranged as almost without gap, while providing protection for the trace in KOR.
In embodiment, a kind of device is provided.The device includes the first substrate with the trace being formed thereon.First Substrate has the external zones of tube core attachment regions, the peripheral blocked area around tube core attachment regions and the periphery around blocked area. First substrate further includes the protective layer above the trace in external zones.Second substrate electrical connection into tube core attachment regions One substrate, and bottom filler, between the first substrate and the second substrate, bottom filler extends in blocked area Trace above, wherein the area of blocked area is between about the 5% and about 18% of the area of the second substrate.
In another embodiment, a kind of device is provided.The device includes the first substrate, and the first substrate is attached with tube core Area, external zones and the blocked area between tube core attachment regions and external zones, wherein protective layer covers the mark in external zones Line, and wherein, protective layer does not extend in tube core attachment regions and blocked area.Second substrate electrical connection to the first substrate, thus So that the second substrate is located above the tube core attachment regions of the first substrate.Tube core attachment regions correspond to the first substrate located immediately at the Region below two substrates, and blocked area extends to the boundary of tube core attachment regions from the boundary of protective layer.The area of blocked area Between about the 5% of the area of the second substrate and about 18%.
In another embodiment, a kind of method forming semiconductor devices is provided.This method includes providing the first substrate, the One substrate has the trace being formed on, and forms protective layer in the upper of the first substrate.Second substrate is attached To the first substrate.Blocked area extends between the boundary of protective layer and the periphery of the second substrate, wherein the area of blocked area between Between about the 5% of the area of second substrate and about 18%.
Foregoing has outlined the features of several embodiments, so that the present invention may be better understood in those of ordinary skill in the art Aspect.It will be understood by those skilled in the art that they easily can design or repair using based on the present invention It uses instead in implementing and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Ability Field technique personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from this In the case where the spirit and scope of invention, they can make a variety of variations to the present invention, replace and change.

Claims (20)

1. a kind of semiconductor devices, comprising:
First substrate, has the trace formed on first substrate, and first substrate has tube core attachment regions, surrounds institute Stating the blocked area of the periphery of tube core attachment regions and the external zones of the periphery around the blocked area, first substrate has position The protective layer of the covering trace in the external zones；
Second substrate, first substrate being electrically connected in the tube core attachment regions；And
Bottom filler, between first substrate and second substrate, the bottom filler is extended in positioned at institute It states above the trace in blocked area；
Wherein, the area of the blocked area is between the 5% and 18% of the area of second substrate.
2. semiconductor devices according to claim 1, wherein second substrate includes integrated circuit die.
3. semiconductor devices according to claim 1, wherein the edge of second substrate and most connecing for the protective layer Distance of blocking between close edge is equal to or more than 420 μm.
4. semiconductor devices according to claim 1, wherein the bottom filler includes having silica-filled material The high-molecular compound of material.
5. semiconductor devices according to claim 1, wherein the bottom filler is completely covered positioned at the blocked area With the trace in the tube core attachment regions.
6. semiconductor devices according to claim 1, wherein second substrate is attached using Bump-on-trace connector To first substrate.
7. semiconductor devices according to claim 1, wherein second substrate includes being directly connected to using solder material The copper post of the first trace on to first substrate.
8. a kind of semiconductor devices, comprising:
First substrate has tube core attachment regions, external zones and the screening between the tube core attachment regions and the external zones Keep off area, wherein protective layer covers the trace in the external zones, and wherein, and it is attached that the protective layer does not extend to the tube core It connects in area and the blocked area；And
Second substrate, is electrically connected to first substrate, and second substrate is located at the tube core attachment of first substrate Above area；
Wherein, the tube core attachment regions correspond to the region below second substrate of first substrate；
Wherein, the blocked area extends to the boundary of the tube core attachment regions from the boundary of the protective layer；
Wherein, the area of the blocked area is between the 5% and 18% of the area of second substrate.
9. semiconductor devices according to claim 8 further includes between first substrate and second substrate Bottom filler.
10. semiconductor devices according to claim 9, wherein the bottom filler is completely covered in the blocked area The trace.
11. semiconductor devices according to claim 9, wherein the bottom filler includes with silica-filled The high-molecular compound of material.
12. semiconductor devices according to claim 8, wherein second substrate includes integrated circuit die.
13. semiconductor devices according to claim 8, wherein the edge and the protective layer of second substrate are most Distance of blocking between close edge is equal to or more than 420 μm.
14. semiconductor devices according to claim 8, wherein second substrate is attached using Bump-on-trace connector It is connected to first substrate.
15. a kind of method for forming semiconductor devices, which comprises
The first substrate is provided, first substrate has the trace formed on first substrate；
Protective layer is formed in the upper of first substrate；And
Second substrate is attached to first substrate；
Wherein, blocked area extends between the boundary of the protective layer and the periphery of second substrate, the face of the blocked area Product is between the 5% and 18% of the area of second substrate.
16. the method according to claim 15 for forming semiconductor devices, further include bottom filler is arranged in it is described Between first substrate and second substrate.
17. the method according to claim 16 for forming semiconductor devices, wherein institute is completely covered in the bottom filler State the trace in blocked area.
18. the method according to claim 16 for forming semiconductor devices, wherein the bottom filler includes having two The high-molecular compound of silica-filled material.
19. the method according to claim 15 for forming semiconductor devices, wherein second substrate includes integrated circuit Tube core.
20. the method according to claim 15 for forming semiconductor devices, wherein the edge of second substrate and described Distance of blocking between the immediate edge of protective layer is equal to or more than 420 μm.
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