CN112687549A - Chip packaging structure with shielding function and packaging method thereof - Google Patents
Chip packaging structure with shielding function and packaging method thereof Download PDFInfo
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- CN112687549A CN112687549A CN202011576405.1A CN202011576405A CN112687549A CN 112687549 A CN112687549 A CN 112687549A CN 202011576405 A CN202011576405 A CN 202011576405A CN 112687549 A CN112687549 A CN 112687549A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 90
- 239000002184 metal Substances 0.000 claims abstract description 90
- 239000011521 glass Substances 0.000 claims abstract description 20
- 239000004033 plastic Substances 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 239000000843 powder Substances 0.000 claims description 5
- 238000007731 hot pressing Methods 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging method with a shielding function, which comprises the following steps: providing a second substrate made of glass and a dielectric layer attached to one side of the second substrate, forming a first rewiring layer embedded into the dielectric layer on one side of the dielectric layer, and forming a plurality of grooves on the surface of the first rewiring layer, which is flush with the dielectric layer, so as to obtain a first sub-substrate; providing a third substrate made of glass, manufacturing a metal shielding layer and a plurality of conductive columns embedded into the third substrate and the metal shielding layer on the third substrate, and enabling the conductive columns to be provided with bosses protruding out of the metal shielding layer to manufacture a second sub-base; aligning the boss and embedding the boss into the groove to enable the first sub-substrate and the second sub-substrate to be attached and connected, and obtaining a substrate for packaging the chip; and providing a plurality of chip groups, inversely installing the chip groups on one exposed side of the circuit, carrying out plastic package on the chip groups and electrically leading out the chip groups on the other side of the circuit. The invention can effectively reduce the warpage generated by chip packaging, enhance the electromagnetic shielding function of the chip and improve the yield of the chip packaging structure.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a chip packaging structure with a shielding function and a packaging method thereof.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of new generation electronic products, especially the development of products such as mobile phones, notebooks, intelligent wearable devices, etc., chips are developed in the direction of higher density, faster speed, smaller size, lower cost, etc.
In the packaging process, due to the difference of the thermal expansion coefficients of materials such as plastic, silicon and metal, the volume changes of the materials are asynchronous, so that stress is generated and warping is caused. The difference between the thermal expansion coefficients of the chip and the injection molding material enables the stress generated in the cooling process of the injection molding material to be the most main cause of the warpage generation in the packaging technology.
In addition, in the chip fan-out package process, it is usually necessary to drill a plastic package layer of the covered flip chip and fabricate a conductive post by electroplating, so as to electrically lead out the flip chip. In the process of opening the holes, the depth of the holes is not easy to control, so that the chips are easily damaged or other conductive circuits are broken down, and the yield of the chip packaging structure is influenced.
Disclosure of Invention
The invention aims to provide a chip packaging method with a shielding function and a chip packaging structure with the shielding function, which are manufactured by adopting the method, so that the warping generated by chip packaging can be effectively reduced, a chip can have the electromagnetic shielding function, and the yield of the chip packaging structure is improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a method for packaging a chip with a shielding function is provided, which includes:
providing a second substrate made of glass and a dielectric layer attached to one side of the second substrate, forming a first rewiring layer embedded into the dielectric layer and flush with one surface of the dielectric layer on one side, far away from the second substrate, of the dielectric layer, and forming a plurality of grooves on the surface, flush with the dielectric layer, of the first rewiring layer to obtain a first sub-substrate;
providing a third substrate made of glass, manufacturing a metal shielding layer on the third substrate, manufacturing a plurality of conductive columns embedded into the third substrate and the metal shielding layer, enabling the conductive columns to be provided with bosses protruding out of the metal shielding layer and enabling the bosses to correspond to the grooves in position one to one, and manufacturing a second sub-base;
aligning and embedding the boss into the groove, and enabling the first sub-substrate and the second sub-substrate to be attached and connected to obtain a substrate for chip packaging, wherein at least the conductive column and the first redistribution layer form a circuit of the substrate for chip packaging;
and providing a plurality of chip groups, inversely installing the chip groups on the exposed side of the circuit and electrically connecting the chip groups with the circuit, plastically packaging the chip groups and electrically leading out the chip groups on the other side of the circuit.
According to the invention, the first rewiring layer with the groove structure is directly formed on the second substrate made of the glass material, the conductive post with the boss is manufactured on the third substrate made of the glass material, and the conductive post is inserted into the groove and connected with the first rewiring layer to manufacture the chip packaging substrate for packaging the chip, so that adverse effects caused by manufacturing the conductive post by punching after the chip is pasted and packaged are avoided, meanwhile, the warping phenomenon generated in the chip packaging process is reduced, and the metal shielding layer is positioned in the chip packaging structure and positioned on one side of the chip group, so that the electromagnetic shielding effect of the chip packaging structure can be effectively enhanced.
As a preferable mode of the method for packaging a chip having a shielding function, the first sub-substrate is produced by specifically using the following steps:
s10a, providing a first substrate which is made of glass and provided with a plurality of salient points on the surface, and manufacturing a first seed layer made of copper on the first substrate;
s10b, manufacturing a first photosensitive dry film on the first seed layer, and forming a graphical window at least exposing each bump;
s10c, manufacturing a first rewiring layer in the graphical window;
s10d, removing the residual first photosensitive dry film;
s10e, etching away the first seed layer exposed out of the first redistribution layer;
s10f, pressing a dielectric material on the first redistribution layer to form a dielectric layer;
s10g, providing a second substrate made of glass, and attaching the dielectric layer to the second substrate;
and S10h, removing the first substrate, and forming a groove on the first rewiring layer.
The first seed layer made of the copper material can improve the connection stability between the subsequent conductive pillars and the first redistribution layer.
As a preferable scheme of the chip packaging method with the shielding function, the salient point is of a hemispherical structure or a conical structure, and the groove is of a hemispherical structure or a conical structure matched with the boss.
Specifically, when the bump is of a tapered structure, the area of one end of the bump, which is far away from the first substrate, is slightly smaller than the area of one end of the bump, which is connected with the first substrate, so that the groove formed on the first redistribution layer subsequently is tightly matched with the boss of the conductive pillar.
As a preferable mode of the method for packaging a chip having a shielding function, the second sub-substrate is produced by specifically using the following steps:
s20a, providing a third substrate made of glass, and manufacturing a metal shielding layer on one side of the third substrate;
s20b, forming TGV through holes in the third substrate and the metal shielding layer;
s20c, manufacturing a conductive column in the TGV through hole, enabling one end of the conductive column to be flush with one surface of the third substrate far away from the metal shielding layer, and enabling the other end of the conductive column to protrude out of the metal shielding layer to form the boss.
Alternatively, a metallic shield layer made of copper or silver may be formed on the third substrate by electroplating, a metallic shield layer made of silver or tungsten titanium may be formed on the third substrate by vacuum sputtering, or a metallic shield layer made of various metallic materials such as copper or silver may be formed on the third substrate by electroless plating.
As a preferable scheme of the chip packaging method with the shielding function, the substrate for chip packaging is specifically prepared by the following steps:
s30a, dipping the first sub-substrate and/or the second sub-substrate with nano metal powder, inserting a boss on the second sub-substrate into the groove on the first sub-substrate in an aligning manner, and melting and filling the nano metal powder between the boss and the groove through hot pressing to form a metal connecting layer so as to enable the first sub-substrate and the second sub-substrate to be attached and connected; the nano-metal powder can be nano-copper powder, or can be other metal materials which can be melted by heating, preferably nano-copper powder, and is consistent with the materials of the first redistribution layer and the conductive pillar, so that the electrical connection stability can be improved;
or carrying out plasma cleaning on the first sub-substrate and the second sub-substrate, removing surface impurities, aligning and embedding the boss into the groove, and attaching the first sub-substrate and the second sub-substrate through electrostatic adsorption;
s30b, forming a second seed layer electrically connected to the conductive pillar and a second redistribution layer on the second seed layer on the third substrate, so as to obtain a substrate for chip packaging, where the conductive pillar, the first redistribution layer, the second seed layer, and the second redistribution layer form the circuit.
Wherein, step S30b specifically includes:
manufacturing a second seed layer electrically connected with the conductive posts on the third substrate through vacuum sputtering;
pasting a second photosensitive dry film on the second seed layer, and forming a graphical window through exposure and development;
manufacturing a second rewiring layer in the graphical window through electroplating;
and removing the residual second photosensitive dry film and the second seed layer exposed out of the second rewiring layer.
As a preferable scheme of the chip packaging method with the shielding function, the chip packaging method includes the following specific steps:
s40a, providing a plurality of chipsets, and inversely installing the chipsets on the second rewiring layer;
s40b, carrying out plastic package on the chip set to form a plastic package layer;
s40c, removing the second substrate, and opening the dielectric layer to expose the pad area of the first redistribution layer;
s40d, providing a plurality of metal bumps, and implanting the metal bumps into the pad area to be electrically connected with the first rewiring layer.
In another aspect, a chip package structure manufactured by the chip package method with shielding function includes:
the base for packaging the chip comprises a third substrate, a metal shielding layer and a plurality of conductive columns, wherein the metal shielding layer is positioned on one side of the third substrate, the conductive columns are embedded into the third substrate and the metal shielding layer, one end of each conductive column is flush with one surface of the third substrate, which is far away from the metal shielding layer, and the other end of each conductive column protrudes out of the metal shielding layer to form a boss; the metal shielding layer is arranged on the first substrate, the second substrate is arranged on the second substrate, the dielectric layer is arranged on one side, far away from the third substrate, of the metal shielding layer, the first redistribution layer with a plurality of grooves is embedded into the dielectric layer, the first seed layer made of copper is arranged on one side, far away from the dielectric layer, of the first redistribution layer, the openings of the grooves are arranged on one side, close to the metal shielding layer, of the first redistribution layer, the bosses are connected with the grooves in a one-to-one correspondence mode, and hole sites for exposing the pad area of the first redistribution layer are formed in;
the plurality of chip groups are inversely arranged on one side of the third substrate far away from the metal shielding layer and are electrically connected with the conductive columns;
a plastic package layer on the third substrate and covering the chip set:
and the metal bumps are implanted into the pad area and are electrically connected with the first rewiring layer.
The metal shielding layer is positioned in the chip packaging structure and on one side of the third substrate, so that the warping phenomenon generated in the chip packaging process can be effectively reduced, the electromagnetic shielding effect of the chip packaging structure is enhanced, and the yield of the base structure for chip packaging is improved.
As a preferable scheme of the chip packaging structure with the shielding function, the chip packaging structure further includes a second seed layer located on the third substrate and a second redistribution layer located on the second seed layer, the second redistribution layer is electrically connected to the conductive pillars, a plurality of chips are inversely mounted on the second redistribution layer and electrically connected to the second redistribution layer, and the plastic package layer is located on one side of the third substrate far away from the metal shielding layer and covers the chips.
As a preferable scheme of the chip packaging structure with the shielding function, the substrate for chip packaging further includes a metal connection layer, and the metal connection layer is filled between the conductive pillar and the groove to connect the conductive pillar and the groove.
Furthermore, the metal connecting layer, the conductive column and the first redistribution layer are made of the same material, so that the connection stability is improved.
Furthermore, the metal connecting layer, the conductive column and the first redistribution layer are made of copper materials, so that the connection stability can be further improved, and the electric signal transmission is more stable.
As a preferred scheme of the chip packaging structure with the shielding function, the boss is of a hemispherical structure or a conical structure, and the groove is of a hemispherical structure or a conical structure matched with the boss.
As a preferable scheme of the chip packaging structure with the shielding function, the metal shielding layer is made of any one of copper, silver and tungsten titanium material, so as to improve the electromagnetic shielding effect of the chip packaging structure.
As a preferable aspect of the chip packaging structure having the shielding function, the third substrate is made of glass.
The invention has the beneficial effects that: according to the invention, the first rewiring layer with the groove structure is directly formed on the second substrate made of the glass material, the conductive post with the boss is manufactured on the third substrate made of the glass material, and the conductive post is inserted into the groove and connected with the first rewiring layer to manufacture the chip packaging substrate for packaging the chip, so that adverse effects caused by manufacturing the conductive post by punching after the chip is pasted and packaged are avoided, meanwhile, the warping phenomenon generated in the chip packaging process is reduced, the metal shielding layer is positioned in the chip packaging structure and positioned on one side of the chip group, the electromagnetic shielding effect of the chip packaging structure can be effectively enhanced, and the product yield is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic cross-sectional view illustrating a first photosensitive dry film attached to a first substrate according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of the first photosensitive dry film after exposure and development according to the first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a first redistribution layer formed on a first substrate according to a first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of the first photosensitive dry film removed according to the first embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a dielectric layer attached to a first substrate and covering a first redistribution layer according to a first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of the first substrate after being removed and the dielectric layer being attached to the second substrate according to the first embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a metal shielding layer formed on a third substrate according to a first embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a third substrate and a metal shielding layer after TGV through holes are formed in the third substrate and the metal shielding layer according to a first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a TGV through hole with conductive posts formed therein by electroplating according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a first sub-substrate and a second sub-substrate after being bonded according to the first embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view illustrating the chip set according to the first embodiment of the invention after being flip-chip mounted on the substrate for chip packaging and electrically connected to an end surface of the conductive pillar.
Fig. 12 is a schematic cross-sectional view of the packaged chipset according to the first embodiment of the invention.
Fig. 13 is a schematic cross-sectional view of a metal bump after being implanted according to a first embodiment of the invention.
Fig. 14 is a schematic cross-sectional view of a second redistribution layer formed on a third substrate according to a second embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view illustrating a chipset according to a second embodiment of the present invention being flip-chip mounted on a second redistribution layer.
Fig. 16 is a schematic cross-sectional view of the packaged chipset according to the second embodiment of the invention.
Fig. 17 is a schematic cross-sectional view of a metal bump according to a second embodiment of the present invention after the metal bump is implanted.
In the figure:
11. a first substrate; 12. salient points; 13. a first photosensitive dry film; 14. a first rewiring layer; 15. a dielectric layer; 16. a second substrate; 17. a groove; 21. a third substrate; 22. a metal shielding layer; 23. a TGV through hole; 24. a conductive post; 25. a second rewiring layer; 31. a chipset; 32. a plastic packaging layer; 33. and a metal bump.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example one
The chip packaging method with the shielding function in the embodiment comprises the following steps:
step S10, preparing a first sub-substrate:
s10a, providing a first substrate 11 which is made of glass and provided with a plurality of hemispherical bumps 12 on one surface, and depositing a first seed layer made of copper on the first substrate 11;
s10b, referring to fig. 1, fabricating a first photosensitive dry film 13 on the first seed layer, and opening a patterned window exposing at least each bump 12 through exposure and development, referring to fig. 2;
s10c, manufacturing a first redistribution layer 14 in the patterned window by electroplating, wherein an upper surface of the first redistribution layer 14 is flush with an upper surface of the first photosensitive dry film 13, referring to fig. 3;
s10d, removing the residual first photosensitive dry film 13, referring to fig. 4;
s10e, etching away the first seed layer exposed from the first redistribution layer 14;
s10f, pressing a dielectric material on the first redistribution layer 14 to form a dielectric layer 15, referring to fig. 5;
s10g, providing a second substrate 16 made of glass, and attaching the dielectric layer 15 to the second substrate 16 by using temporary bonding glue;
s10h, removing the first substrate 11, and forming a hemispherical groove 17 on the first redistribution layer 14, referring to fig. 6.
Step S20, preparing a second sub-substrate:
s20a, providing a third substrate 21 made of glass, and forming a metal shielding layer 22 made of copper material on one side of the third substrate 21 by electroplating, referring to fig. 7;
s20b, forming TGV through holes 23 on the third substrate 21 and the metal shielding layer 22, referring to fig. 8;
s20c, forming a conductive pillar 24 in the TGV through hole 23 by electroplating, and making one end of the conductive pillar 24 flush with a surface of the third substrate 21 away from the metallic shielding layer 22, and making the other end protrude from the metallic shielding layer 22 to form a hemispherical boss, referring to fig. 9.
Step S30, preparing a substrate for chip packaging:
the first sub-substrate and the second sub-substrate are respectively stained with nano copper powder, a boss on the second sub-substrate is inserted into a groove 17 on the first sub-substrate in an aligning manner, the nano copper powder is melted and filled between the boss and the groove 17 through hot pressing to form a metal connecting layer, and the first sub-substrate and the second sub-substrate are attached and connected with each other, referring to fig. 10.
Step S40, chip packaging:
s40a, providing a plurality of chip sets 31, and inversely installing the chip sets 31 on the exposed surfaces of the conductive pillars 24, referring to fig. 11;
s40b, performing plastic package on the chipset 31 to form a plastic package layer 32, referring to fig. 12;
s40c, removing the second substrate 16, and opening the dielectric layer 15 to expose the pad region of the first redistribution layer 14;
s40d, providing a plurality of metal bumps 33, and implanting the metal bumps 33 into the pad region to electrically connect with the first redistribution layer 14, referring to fig. 13.
The metal bump 33 is solder, silver solder or gold-tin alloy solder, and the embodiment is preferably a solder ball made of solder.
In other embodiments, the number of chipsets and the number of chips in each chipset are determined according to specific design requirements, and are not limited specifically.
As shown in fig. 13, the chip packaging structure with a shielding function manufactured by the chip packaging method with a shielding function according to the embodiment includes:
the base for chip packaging comprises a third substrate 21, a metal shielding layer 22 made of copper and located on one side of the third substrate 21, and a plurality of conductive columns 24 embedded into the third substrate 21 and the metal shielding layer 22, wherein the conductive columns 24 are made of copper, one end of each conductive column 24 is flush with one surface of the third substrate 21, which is far away from the metal shielding layer 22, and the other end of each conductive column protrudes out of the metal shielding layer 22 to form a boss; the metal shielding layer 22 further comprises a dielectric layer 15 located on one side of the metal shielding layer 22 far away from the third substrate 21, a first redistribution layer 14 embedded in the dielectric layer 15 and provided with a plurality of grooves 17, and a first seed layer made of copper and located on one side of the first redistribution layer 14 far away from the dielectric layer 15, wherein an opening of each groove 17 is located on one side of the first redistribution layer 14 close to the metal shielding layer 22, the bosses are connected with the grooves 17 in a one-to-one correspondence manner, and the dielectric layer 15 is provided with hole sites for exposing a pad area of the first redistribution layer 14;
a plurality of chip sets 31, which are inversely installed on one side of the third substrate 21 far away from the metal shielding layer 22 and electrically connected with the conductive posts 24;
a molding layer 32 located on the third substrate 21 and covering the chip set 31:
and a plurality of solder balls (metal bumps 33) implanted in the pad region and electrically connected to the first redistribution layer 14.
In this embodiment, the metal shielding layer 22 is made of a copper material, is located inside the chip packaging structure, and is located on one side of the third substrate 21, so that a warpage phenomenon generated in a chip packaging process can be effectively reduced, an electromagnetic shielding effect of the chip packaging structure is enhanced, and a yield of the base structure for chip packaging is improved.
Further, the substrate for chip packaging further includes a metal connection layer, and the metal connection layer is filled between the conductive posts 24 and the grooves 17 to enhance the stability of chip signal transmission.
The boss is of a hemispherical structure, and the groove 17 is of a hemispherical structure matched with the boss.
Example two
This embodiment is substantially the same as the first embodiment (refer to some drawings in the first embodiment, and like parts are labeled with like numerals in the first embodiment), except for steps S30 and S40.
Specifically, the step S30 of preparing the substrate for chip packaging includes the steps of:
s30a, respectively dipping a first sub-substrate and a second sub-substrate with nano-copper powder, inserting a boss on the second sub-substrate into the groove 17 on the first sub-substrate in an aligning manner, and melting and filling the nano-copper powder between the boss and the groove 17 through hot pressing to form a metal connecting layer so as to enable the first sub-substrate and the second sub-substrate to be attached and connected;
s30b, forming a second seed layer electrically connected to the conductive pillar 24 on the third substrate 21 by vacuum sputtering;
pasting a second photosensitive dry film on the second seed layer, and forming a graphical window through exposure and development;
fabricating a second rewiring layer 25 within the patterned window by electroplating;
the remaining second photosensitive dry film and the second seed layer exposed from the second redistribution layer 25 are removed, so as to obtain the structure shown in fig. 14.
Specifically, the step S40 chip package includes the following steps:
s40a, providing a plurality of chipsets 31, and flip-mounting the chipsets 31 on the second redistribution layer 25, referring to fig. 15;
s40b, performing plastic package on the chipset 31 to form a plastic package layer 32, referring to fig. 16;
s40c, removing the second substrate 16, and opening the dielectric layer 15 to expose the pad region of the first redistribution layer 14;
s40d, providing a plurality of solder balls (metal bumps 33), and implanting the solder balls into the pad regions to electrically connect the solder balls to the first redistribution layer 14, referring to fig. 17.
The metal shielding layer 22 is a silver metal shielding layer prepared by electroless plating.
In this embodiment, the second seed layer and the second redistribution layer 25 are manufactured on the basis of the first embodiment, so that the mounting range of the chipset 31 is increased, the problem that the area of the exposed end surface of the conductive pillar 24 is too small to affect the smooth assembly of the chipset 31 is avoided, and the yield of the chip packaging structure is further improved.
The chip packaging structure with the shielding function manufactured by the chip packaging method with the shielding function in this embodiment is basically the same as the chip packaging structure manufactured in the first embodiment, except that a second seed layer and a second redistribution layer 25 are further included.
As shown in fig. 17, the chip packaging structure with a shielding function in this embodiment further includes a second seed layer located on the third substrate 21 and a second redistribution layer 25 located on the second seed layer, where the second redistribution layer 25 is electrically connected to the conductive pillars 24 through the second seed layer, a plurality of chip sets 31 are flip-mounted on the second redistribution layer 25 and are electrically connected to the second redistribution layer 25, and the molding compound layer 32 is located on a side of the third substrate 21 away from the metal shielding layer 22 and covers the chip sets 31.
By manufacturing the second seed layer and the second redistribution layer 25 electrically connected to the conductive pillars 24 on the third substrate 21, the limited range of the chip set 31 during flip-chip mounting is reduced, the flip-chip mounting of the chip set 31 is facilitated, and the yield of the chip packaging structure is enhanced.
EXAMPLE III
This embodiment is substantially the same as the second embodiment (refer to the drawings in the first embodiment, and the same components are denoted by the same reference numerals in the first embodiment), except for the difference in S30a in step S30.
Specifically, the step S30a of preparing the substrate for chip packaging includes the steps of:
and carrying out plasma cleaning on the first sub-substrate and the second sub-substrate, aligning and embedding the lug boss into the groove 17 after removing surface impurities, and attaching and connecting the first sub-substrate and the second sub-substrate through electrostatic adsorption.
The chip package structure with the shielding function in this embodiment is substantially the same as the second embodiment, except that a metal connection layer is not included, and details are not repeated.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (10)
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Cited By (1)
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|---|---|---|---|---|
| US12027470B2 (en) | 2021-05-11 | 2024-07-02 | Industrial Technology Research Institute | Package carrier having a stiffener between solder bumps |
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