CN112582268B - Semiconductor device and method for forming the same - Google Patents
Semiconductor device and method for forming the same Download PDFInfo
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- CN112582268B CN112582268B CN201910940543.4A CN201910940543A CN112582268B CN 112582268 B CN112582268 B CN 112582268B CN 201910940543 A CN201910940543 A CN 201910940543A CN 112582268 B CN112582268 B CN 112582268B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
- H10D30/0241—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] doping of vertical sidewalls, e.g. using tilted or multi-angled implants
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- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention provides a semiconductor device and a forming method. In the embodiment of the invention, a first epitaxial layer with lower doping concentration, a second epitaxial layer with higher doping concentration than the first epitaxial layer and a third epitaxial layer are sequentially formed. The concentration of doping ions from the side wall of the channel region to the source region and the drain region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, short channel effects can be suppressed, and the performance of the semiconductor device can be improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the continuous development of semiconductor manufacturing process, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a semiconductor device and a forming method thereof, so as to improve the performance of the semiconductor device.
In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, the method including:
providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, and a region, below the grid structure, of the fin parts is a channel region;
Etching fin parts on two sides of the gate structure by taking the gate structure as a mask to form a concave region on the fin part, and exposing the side wall of the channel region;
And forming a source drain region in the recessed region, wherein the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, and the doping concentration of doping ions of the first epitaxial layer is smaller than that of doping ions of the second epitaxial layer and the third epitaxial layer.
Further, doping concentrations of doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially increased, and the first epitaxial layer covers the side wall of the channel region and the bottom of the recessed region.
Further, the doping concentration of the first epitaxial layer is E18-E19/cubic centimeter, the doping concentration of the second epitaxial layer is E20-E21/cubic centimeter, and the doping concentration of the third epitaxial layer is E21-E22/cubic centimeter.
Further, the semiconductor device is a P-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of boron ions, gallium ions and indium ions.
Further, the semiconductor device is an N-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of phosphorus ions or arsenic ions.
Further, the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon germanium layers, wherein germanium content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is sequentially increased.
Further, the mole fraction of germanium in the first epitaxial layer is 10% -20%, the mole fraction of germanium in the second epitaxial layer is 20% -50%, and the mole fraction of germanium in the third epitaxial layer is 30% -50%.
Further, the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon-carbon layers, wherein the carbon content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is sequentially increased.
Further, the semiconductor device is an N-type transistor, the mole fraction of carbon in the first epitaxial layer is 10% -20%, the mole fraction of carbon in the second epitaxial layer is 20% -50%, and the mole fraction of carbon in the third epitaxial layer is 30% -50%.
Further, the gate structure comprises a dummy gate and an isolation layer covering the side wall of the dummy gate, and the forming of the source drain region specifically comprises:
Thinning the isolation layer;
Forming a first epitaxial layer on the bottom surface of the concave region and the side wall of the channel region by using the dummy gate and the thinned isolation layer as masks through a first epitaxial process;
Forming the second epitaxial layer on the first epitaxial layer;
and forming the third epitaxial layer on the second epitaxial layer.
Further, the forming the second epitaxial layer on the first epitaxial layer is specifically that;
Forming a second epitaxial material layer on the first epitaxial layer by adopting a second epitaxial process;
Performing ion implantation on the second epitaxial material layer by adopting a first ion implantation process;
And annealing the second epitaxial material layer to form a second epitaxial layer.
Further, the forming the third epitaxial layer on the second epitaxial layer is specifically that;
forming a third epitaxial material layer on the second epitaxial layer by adopting a third epitaxial process;
Forming a side wall covering the side wall of the thinned isolation layer;
And taking the dummy gate, the thinned isolation layer and the side wall as masks, and performing ion implantation on the third epitaxial material layer by adopting a second ion implantation process to form a third epitaxial layer.
Further, the first ion implantation process specifically comprises the steps that implantation ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, implantation energy is 0.5K-2K, and doping concentration is 2E14-5E14.
Further, the first ion implantation process specifically includes implanting ions of a type opposite to that of the doped ions of the source/drain regions.
Further, the thickness of the first epitaxial layer is 3-7 nanometers, the thickness of the second epitaxial layer is 5-17 nanometers, and the upper surface of the third epitaxial layer is basically flush with the upper surface of the fin portion.
In a second aspect, an embodiment of the present invention provides a semiconductor device including:
The front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, wherein the area of the fin parts below the grid structure is a channel area, and the fin parts on two sides of the grid structure are provided with concave areas;
The source drain region is located in the concave region and comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, wherein the doping concentration of doping ions of the first epitaxial layer is smaller than that of doping ions of the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the side wall of the channel region and the bottom of the concave region.
Further, the doping concentrations of the doping ions of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer sequentially increase.
Further, the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon germanium layers, wherein germanium content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is sequentially increased.
Further, the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon-carbon layers, wherein the carbon content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is sequentially increased.
Further, the thickness of the first epitaxial layer is 3-7 nanometers, the thickness of the second epitaxial layer is 5-17 nanometers, and the upper surface of the third epitaxial layer is basically flush with the upper surface of the fin portion.
In the embodiment of the invention, a first epitaxial layer with lower doping concentration, a second epitaxial layer with higher doping concentration than the first epitaxial layer and a third epitaxial layer are sequentially formed. The concentration of doping ions from the side wall of the channel region to the source region and the drain region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, short channel effects can be suppressed, and the performance of the semiconductor device can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 4 are schematic views of structures formed at respective steps of a method for forming a semiconductor device of a comparative example;
fig. 5 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention;
Fig. 6 to 12 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic structural view of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise", "comprising", and the like in the context of the present document shall be construed in an inclusive sense rather than an exclusive or exhaustive sense, that is to say, in a sense of "including but not limited to".
In the description of the present document, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present document, it is to be understood that the term "layer" is used in its broadest sense, including films, cover layers or the like, and that a layer may comprise a plurality of sub-layers.
In the description of the present document, it is to be understood that reference throughout the specification is made to conventional etching techniques known in the art of semiconductor fabrication for selectively removing polysilicon, silicon nitride, silicon dioxide, metals, photoresists, polyimides, or similar materials, including, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, shower cleaning, chemical mechanical Polishing (CHEMICAL MECHANICAL Polishing, CMP), and the like. Specific embodiments are described herein with reference to examples of such processes. However, the disclosure and references to specific deposition techniques should not be limited to what is described. In some examples, two such techniques may be interchanged. For example, stripping the photoresist may include immersing the sample in a wet chemical bath or alternatively spraying wet chemicals directly onto the sample.
By "straddling" is meant that, for example, the gate structure straddles the fin portion, it means that the dummy gate structure covers a portion of the top surface and a portion of the sidewall surface of the fin portion, and the dummy gate structure and the fin portion have a crossed positional relationship, and the height of the dummy gate structure is greater than the height of the fin portion.
Semiconductor devices are electronic devices that have electrical conductivity between good electrical conductors and insulators, and that utilize the specific electrical characteristics of semiconductor materials to perform specific functions, and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. The semiconductor devices commonly used in the prior art include Fin field effect transistors (FinField-Effect Transistor, fin-FETs). The finfet includes different types of transistors, including P-type finfet and N-type finfet.
As transistor gate length continues to shrink, oxidation enhanced Diffusion (Oxidation Enhanced Diffusion, OED) becomes a key factor affecting boron and phosphorus ion Diffusion, resulting in transient enhanced Diffusion effects (TRANSIENT ENHANCED Diffusion TED) due to oxidation enhanced Diffusion effects, which not only cause Short channel effects (Short CHANNEL EFFECTS, SCE) of the transistor, but also affect transistor channel mobility, junction capacitance, and junction leakage current. Short channel effects are some of the effects that occur when the conduction channel length of a metal oxide field effect transistor is reduced to the order of tens of nanometers, even a few nanometers. These effects mainly include threshold voltage decrease with decreasing channel length, drain induced barrier decrease, carrier surface scattering, velocity saturation, ionization, and hot electron effects. Therefore, a new method for forming a semiconductor device is urgently needed to suppress the transient enhanced diffusion effect in the manufacturing process of the semiconductor device, thereby effectively suppressing the short channel effect and improving the performance of the semiconductor device.
Referring to fig. 1 to 4, the method of forming the semiconductor device of the comparative example includes the steps of:
step S1, providing a front-end device layer. The front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, and the area, below the grid structure, of the fin parts is a channel area.
And S2, etching the fin parts by taking the gate structure as a mask, and etching the fin parts on two sides of the gate structure to form a concave region on the fin part so as to expose the side wall of the channel region.
And S3, forming source and drain regions on the fin parts at two sides of the channel region.
Fig. 1 is a schematic view of the front-end device layer of the semiconductor device of the comparative example. Fig. 2 is a schematic cross-sectional view of fig. 1 along line AA'. Referring to fig. 1 and 2, in step S1, a front-end device layer 1 is provided. The front-end device layer 1 comprises a plurality of discrete fins 2 and a gate structure 3 crossing the fins 2.
The gate structure 3 includes an isolation layer 3a and a dummy gate 3b. The dummy gate 3b includes a gate dielectric layer, a dummy gate layer, and a cap layer stacked in order.
Shallow trench isolation structures (Shallow Trench Isolation, STI) 4 are provided between adjacent fins 11.
Referring to fig. 3, in step S2, fin portions 11 on both sides of the gate structure are etched with the gate structure 3 as a mask, so as to form a recess region 5 on the fin portions 11.
Referring to fig. 4, in step S3, source and drain regions 6 are formed in the recessed regions 5.
However, the semiconductor device formed by the method for forming the semiconductor device of the comparative example still has transient enhanced diffusion effect and has higher leakage current.
In view of this, in order to improve the performance of the semiconductor device, the embodiment of the invention provides a method for forming the semiconductor device. In the embodiment of the present invention, the fin field effect transistor is taken as an example for forming the fin field effect transistor, and further, the method of the embodiment of the present invention can be used for forming the fin field effect transistor with the process node of 14nm and the fin field effect transistor below the process node of 14nm, for example, for forming the field effect transistor with the thickness of 7nm or 14 nm. Further, the method of forming the fin field effect transistor according to the embodiment of the present invention may also be used to form other semiconductor devices such as complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), NAND Memory (NAND FLASH Memory) and static random access Memory (Static Random Access Memory, SRAM).
Fig. 5 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention. As shown in fig. 5, the method for forming a semiconductor device according to an embodiment of the present invention includes the steps of:
step S100, providing a front-end device layer, where the front-end device layer includes a plurality of discrete fin portions and a gate structure crossing the fin portions, and a region of the fin portions below the gate structure is a channel region.
And step 200, etching fin parts on two sides of the gate structure by taking the gate structure as a mask to form a concave region on the fin part, and exposing the side wall of the channel region.
Step S300, forming a source-drain region in the recessed region, wherein the source-drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially stacked, the doping concentration of doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is sequentially increased, and the first epitaxial layer covers the side wall of the channel region and the bottom of the recessed region.
Fig. 6 to 12 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a perspective view of the front-end device layer. Fig. 7 is a schematic cross-sectional view of the front-end device layer along line AA'. Referring to fig. 6 and 7, in step S100, a front-end device layer 10 is provided, the front-end device layer 10 comprising a plurality of discrete fins 11 and a gate structure 12 crossing the fins 11, the region of the fins 11 below the gate structure being a channel region C.
Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of epitaxial layer structure on silicon, a compound front-end device layer, or an alloy front-end device layer. The compound front-end device layer comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer comprises SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or a combination thereof, the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on an insulating material layer, the semiconductor layer having active and passive devices therein, the insulating material layer protecting the active and passive devices disposed on the semiconductor layer. And a plurality of structures such as an epitaxial interface layer or a strain layer and the like can be formed on the surface of the front-end device layer so as to improve the electrical performance of the semiconductor device.
The plurality of fins 11 are parallel or substantially parallel.
The gate structure 12 includes an isolation layer 12a and a dummy gate 12b. The dummy gate 12b includes a gate dielectric layer, a dummy gate layer, and a cap layer stacked in order.
The material of the isolation layer 12a may be silicon dioxide (SiO 2), silicon oxynitride (SiON), silicon nitride (Si 3N4), or silicon oxycarbide (SiOC). In this embodiment, the material of the isolation layer 12a is silicon nitride.
In an alternative implementation, the front-end device layer 10 further includes shallow trench isolation structures 13 therein. Shallow trench isolation structures 13 fill the bottom in adjacent fins 11. The shallow trench isolation structures 13 are used for electrical isolation between adjacent fins 11. The shallow trench isolation structure 13 may avoid implantation of dopant ions into the front-end device layer 10 during a subsequent ion implantation process. The material of the shallow trench isolation structure 13 may be silicon dioxide (SiO 2), silicon oxynitride (SiON), or silicon oxycarbide (SiOC). The material of the shallow trench may also be a low K dielectric material (dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low K dielectric material (dielectric constant is less than 2.5), and in this embodiment, the material of the shallow trench isolation structure 13 is silicon dioxide.
Referring to fig. 8, in step S200, fin portions 11 on both sides of the gate structure are etched using the gate structure 12 as a mask. To form a recess region 20 on the fin 11, exposing the sidewall of the channel region C.
The etching process can be dry etching or wet etching, etc. In this embodiment, dry etching is used to etch the fin 11, and the dry etching may be performed by selecting an etching gas according to the selected material, and may be performed by selecting as the etching gas, for example, trifluoromethane (CHF 3), sulfur hexafluoride (SF 6), carbon tetrafluoride (CF 4), carbon tetrafluoride (CF 4)/oxygen (O 2), carbon tetrafluoride (CF 4)/hydrogen (H 2), and the like. In embodiments of the present invention, CHF 3 is used as the etching gas, which may be at a pressure of 5-300mTorr.
Optionally, after etching the fin, a cleaning process is used to remove impurity ions from the surface of the fin. And after the wet cleaning process is adopted, drying the intermediate structure formed by the steps.
Referring to fig. 9 to 11, in step S300, a source drain region 30 is formed in the recess region 20, the source drain region 30 includes a first epitaxial layer 30a, a second epitaxial layer 30b, and a third epitaxial layer 30c stacked in sequence, wherein doping concentrations of doping ions of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are sequentially increased, and the first epitaxial layer 30a covers sidewalls of the channel region and a bottom of the recess region.
Specifically, the thickness of the first epitaxial layer 30a is 3 nm-7 nm, the thickness of the second epitaxial layer 30b is 5 nm-17 nm, and the upper surface of the third epitaxial layer 30c is substantially flush with the upper surface of the fin portion.
Specifically, the doping concentration of the first epitaxial layer 30a is E18-E19/cubic centimeter, the doping concentration of the second epitaxial layer 30b is E20-E21/cubic centimeter, and the doping concentration of the third epitaxial layer 30c is E21-E22/cubic centimeter.
Further, the doping ions of the first, second and third epitaxial layers 30a, 30b and 30c include one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions.
In an alternative implementation, the semiconductor device is a P-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are all silicon germanium layers, where the germanium content of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c increases sequentially.
Specifically, the first epitaxial layer 30a has a germanium content of 10% -20%, the second epitaxial layer 30b has a germanium content of 20% -50%, and the third epitaxial layer 30c has a germanium content of 30% -50%.
In another alternative implementation, the semiconductor device is an N-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are all silicon-carbon layers, where the carbon content of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c increases sequentially.
Specifically, the semiconductor device is an N-type transistor, the carbon content in the first epitaxial layer 30a is 10% -20%, the carbon content in the second epitaxial layer 30b is 20% -50%, and the germanium content in the third epitaxial layer 30c is 30% -50%.
In an alternative implementation manner, the gate structure includes a dummy gate and an isolation layer covering sidewalls of the dummy gate, and the forming the source drain region specifically includes:
And step S310, thinning the isolation layer.
And step 320, forming a first epitaxial layer on the bottom surface of the concave region and the side wall of the channel region by using the dummy gate and the thinned isolation layer as masks through a first epitaxial process.
Step S330, forming the second epitaxial layer on the first epitaxial layer.
Step S340, forming the third epitaxial layer on the second epitaxial layer.
Referring to fig. 9, in step S310, the isolation layer is thinned.
Specifically, the spacer layer 12a is thinned to a thickness of 4 nm to 7nm from the spacer layer 12 a. The thickness is the dimension of the spacer layer 12a in the horizontal direction in the cross section shown in fig. 11. By thinning the isolation layer 12a, a source drain region can be formed in the recess region 20 better later, so that a void is avoided from being formed at the position of the sidewall of the channel region due to the excessive thickness of the isolation layer 12 a.
Specifically, the isolation layer 12a may be thinned by an etching process. The etching process may be a dry etching process, and in particular may be an etching process having a high selectivity to the fin 11.
In an alternative implementation, the etching gas used may be one or a combination of fluoromethane (CH 3 F), difluoromethane (CH 2F2) and trifluoromethane (CHF 3), in which oxygen is used as an assist gas in combination. The etching gas flow rate is 20 standard milliliters per minute, and the etching time is 20 seconds to 100 seconds.
Referring to fig. 9, in step S320, the first epitaxial layer 30a is formed on the bottom surface of the recess region and the sidewall of the channel region by using the dummy gate 12b and the thinned isolation layer 12a as masks and using a first epitaxial process.
In an alternative implementation, the thickness of the first epitaxial layer 30a is 5 nanometers.
For an N-type semiconductor device, silicon (Si) may be epitaxially grown in recessed region 20. For P-type semiconductor devices, silicon germanium (SiGe) may be epitaxially grown in recessed region 20. The epitaxial growth may form raised source and drain regions in a subsequent process to facilitate introducing stress into the device. Wherein in-situ doping, such as doping with phosphorus (P) or boron (B), etc., may be performed during epitaxial growth.
The epitaxial layer is formed by adopting an epitaxial growth process, so that the width of the source/drain region formed later is larger than that of the fin part, the series resistance can be reduced, the driving current can be improved, and meanwhile, the position of the source/drain region can be lifted to reduce the parasitic junction capacitance, thereby improving the performance of the semiconductor device.
Specifically, the epitaxial growth process can be selected from Vapor Phase Epitaxy (VPE), liquid Phase Epitaxy (Liquid-Phase Epitaxy), molecular Beam Epitaxy (Molecular Beam Epitaxy, MBE), ion Beam Epitaxy (IBE), etc
In an alternative implementation, the first epitaxial layer 30a is epitaxially grown in an atmosphere with Si, siGe, siC a and other precursors at a pressure of 5TORR-500 TORR. In particular, the precursor may include silicon dichlorosilane SiH 2Cl2 (as a silicon precursor), germane (GeH 4), and methylsilane (CH 3-SiH 3). Meanwhile, in-situ doping can be carried out in the epitaxial growth process, and gases such as boron diborane (B 2H6), phosphine (PH 3), arsine (ASH 3) and the like can be introduced.
In an alternative implementation, the semiconductor device is a P-type transistor, the first epitaxial layer 30a is silicon germanium and the proportion of germanium is 15%. The doping concentration of boron in the first epitaxial layer 30a is 5E 18/cc.
In this step, the first epitaxial layer 30a is made to have a first stress by controlling the proportion of germanium and the concentration of dopant ions in the first epitaxial layer 30 a. The silicon germanium epitaxial layer can introduce compressive stress, so that the molecular arrangement in the channel region is tighter, and the mobility of holes is improved.
Referring to fig. 10, in step S330, the second epitaxial layer 30b is formed on the first epitaxial layer 30 a.
Specifically, forming the second epitaxial layer 30b includes the steps of:
and step S331, forming a second epitaxial material layer on the first epitaxial layer by adopting a second epitaxial process.
Specifically, the second epitaxial process differs from the first epitaxial process in that the proportion of germanium in the reaction gas is increased and the concentration of the dopant ions is increased.
And S332, performing ion implantation on the second epitaxial layer by adopting a first ion implantation process.
Specifically, the implantation ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E14.
Further, ions of the opposite ion type as in-situ doped ions are implanted in the second epitaxial layer 30 b. Specifically, in the P-type transistor, phosphorus ions are implanted in the second epitaxial layer 30b, and in the N-type transistor, boron ions are implanted in the second epitaxial layer 30 b.
From the simulation calculation, it can be determined that the smaller the ion implantation dose is, the less damage is caused to the epitaxial layer. Thus, a lower dose of ion implantation is performed in the second epitaxial material layer to fill the gaps in the second epitaxial material layer, which may hinder the diffusion of ions. Controlling the rate of ion diffusion. The opposite type of implanted ions can further block the diffusion of ions in the epitaxial layer. The low energy can avoid damage to the second epitaxial material layer during ion implantation.
Step S333, annealing the second epitaxial material layer to form a second epitaxial layer.
In particular, the anneal may be a rapid thermal anneal (RAPID THERMAL ANNEAL, RTA), which may include in particular a laser thermal anneal (LASER ANNEAL, LSA), a spike rapid thermal anneal (SPIKE ANNEAL, SA), or a flash lamp anneal (FLASH LAMP ANNEAL, FLA).
The temperature of the anneal may range from 800 ℃ to 1200 ℃.
Annealing may relax the second epitaxial layer 30b, reducing the defect density and junction leakage current of the second epitaxial layer 30 b.
In an alternative implementation, the second epitaxial layer 30b is silicon germanium with a proportion of 30% germanium. The doping concentration of boron in the first epitaxial layer 30a is 5E 120/cc.
In this step, the second epitaxial layer has a larger proportion of germanium and a larger doping concentration of dopant ions than the first epitaxial layer. The concentration of the doping ions in the region from the channel region to the second epitaxial layer is gradually increased, and transient enhanced diffusion caused by overlarge concentration difference between the doping ions in the epitaxial layer and the doping ions in the channel region can be avoided. Meanwhile, the proportion of germanium in the first epitaxial layer and the second epitaxial layer is increased in a gradient mode, and curling or breakage of the epitaxial layers caused by excessive stress is avoided.
Referring to fig. 11, in step S340, the third epitaxial layer 30c is formed on the second epitaxial layer 30 b.
Specifically, forming the third epitaxial layer 30c includes the steps of:
step S341, forming a third epitaxial material layer on the second epitaxial layer 30b by using a third epitaxial process.
Specifically, the third epitaxial process is different from the second epitaxial process in that the proportion of germanium in the reaction gas is increased and the concentration of the dopant ions is increased.
And S342, forming a side wall covering the side wall of the thinned isolation layer.
The sidewall 40 is used as a mask in the subsequent ion implantation process to avoid ion implantation into the channel region and the dummy gate. The thickness of the sidewall 40 may be 5 nm to 20 nm.
The material of the side wall 40 may be a low K dielectric material (dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low K dielectric material (dielectric constant is less than 2.5), and in this embodiment, the material of the side wall 20 is silicon dioxide.
Specifically, the sidewall 40 may be formed by chemical Vapor Deposition (Chemical Vapor Deposition, CVD), such as low temperature chemical Vapor Deposition (Low Temperature Chemical Vapor Deposition, LTCVD), plasma chemical Vapor Deposition (PLASMACHEMICAL VAPOR DEPOSITION, PCVD), low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical Vapor Deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), and fluid chemical Vapor Deposition (Fluid Chemical Vapor Deposition, FCVD).
And S343, performing ion implantation on the third epitaxial material layer by using the dummy gate, the thinned isolation layer and the side wall as masks and adopting a second ion implantation process to form a third epitaxial layer.
Specifically, the ion implantation process is to implant one or more of phosphorus ion, arsenic ion, boron ion, indium ion, gallium ion and antimony ion, the ion implantation angle is 0-5 degrees, the implantation dosage is E14atom/cm 2-5E15atom/cm2, and the implantation energy is 6Kev-50Kev.
With the dummy gate 12b, the thinned isolation layer 12a, and the sidewall 40 as masks, ion implantation into the channel region C and the dummy gate 12b can be avoided. At the same time, the region where ions are implanted can be spaced from the channel region C to prevent the ions in the source/drain region 40 from diffusing into the channel region.
In this step, a first epitaxial layer having a lower doping concentration and a second epitaxial layer and a third epitaxial layer having a higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of doping ions from the side wall of the channel region to the source region and the drain region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
Meanwhile, since the first epitaxial layer is not subjected to ion implantation, the energy of ion implantation of the second epitaxial layer is small, and thus, the number of defects formed in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer due to ion implantation gradually increases. That is, the first epitaxial layer near the channel region has few defects, and the rate of ion diffusion can be further controlled.
The proportion of the components in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer also gradually changes, for example, in a P-type transistor, the materials of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon germanium, the proportion of germanium in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer gradually increases, and curling or breakage of the epitaxial layers caused by overlarge stress can be avoided.
Referring to fig. 12, in a subsequent process, annealing the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer is further included. And forming an etching stop layer 60 covering the fin 11, the source drain region 30 and the side wall of the side wall 40. A dielectric layer 70 is formed on the etch stop layer 60. The dummy gate is replaced with a metal gate. And forming a conductive through hole electrically connected with the source/drain region and the metal gate. An interconnect structure electrically connected to the conductive via. And encapsulating the formed semiconductor structure. To form a completed semiconductor device.
In the embodiment of the invention, a first epitaxial layer with lower doping concentration, a second epitaxial layer with higher doping concentration than the first epitaxial layer and a third epitaxial layer are sequentially formed. The concentration of doping ions from the side wall of the channel region to the source region and the drain region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, short channel effects can be suppressed, and the performance of the semiconductor device can be improved.
On the other hand, the embodiment of the invention also provides a semiconductor device, which comprises a front-end device layer and a source-drain region.
The front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, wherein the area of the fin parts below the grid structure is a channel area, and the fin parts on two sides of the grid structure are provided with concave areas.
The source drain region is located in the concave region and comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially stacked, wherein the doping concentration of doping ions of the first epitaxial layer is smaller than that of doping ions of the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the side wall of the channel region and the bottom of the concave region.
Fig. 13 is a schematic structural view of a semiconductor device according to an embodiment of the present invention. Referring to fig. 13, the semiconductor device according to the embodiment of the present invention includes a front-end device layer 10 'and a source drain region 30'.
The front-end device layer 10' includes a plurality of discrete fins 11', a gate structure 12' crossing the fins 11', a channel region C ' located below the gate structure 12' in the fin 11', and recessed regions on the fins 11' on both sides of the gate structure 12 '.
The plurality of fins 11' are parallel or substantially parallel.
In an alternative implementation, the front-end device layer 10 'also includes shallow trench isolation structures 13'. The shallow trench isolation structures 13 'fill the bottom in the adjacent fin 11'. The shallow trench isolation structures 13 'are used for electrical isolation between adjacent fins 11'.
The gate structure 12' includes an isolation layer 12a ' and a dummy gate 12b '. The dummy gate 12b' includes a gate dielectric layer, a dummy gate layer, and a cap layer stacked in order.
In an alternative implementation, the sidewalls of the gate structure 12 'are covered with sidewalls 40'.
The source drain region 30 'is located in the recess region 20', the source drain region 30 'includes a first epitaxial layer 30a', a first epitaxial layer 30b ', and a third epitaxial layer 30c' stacked in sequence, wherein a doping concentration of a doping ion of the first epitaxial layer 30a 'is smaller than a doping concentration of a doping ion of the first epitaxial layer 30b' and the third epitaxial layer 30c ', and the first epitaxial layer 30a' covers a sidewall of the channel region and a bottom of the recess region.
Specifically, the doping concentrations of the doping ions of the first epitaxial layer 30a ', the first epitaxial layer 30b ', and the third epitaxial layer 30c ' sequentially increase.
Specifically, the doping concentration of the first epitaxial layer 30a ' is E18-E19/cc, the doping concentration of the first epitaxial layer 30b ' is E20-E21/cc, and the doping concentration of the third epitaxial layer 30c ' is E21-E22/cc.
Specifically, the doping ions of the first epitaxial layer 30a ', the first epitaxial layer 30b ', and the third epitaxial layer 30c ' include one or more of carbon ions, phosphorus ions, boron ions, gallium ions, and arsenic ions.
Specifically, the semiconductor device is a P-type transistor, and the first epitaxial layer 30a ', the first epitaxial layer 30b', and the third epitaxial layer 30c 'are silicon germanium layers, wherein the germanium content of the first epitaxial layer 30a', the first epitaxial layer 30b ', and the third epitaxial layer 30c' increases in sequence.
Specifically, the first epitaxial layer 30a ' has a germanium content of 10% -20%, the first epitaxial layer 30b ' has a germanium content of 20% -50%, and the third epitaxial layer 30c ' has a germanium content of 30% -50%.
Specifically, the semiconductor device is an N-type transistor, and the first epitaxial layer 30a ', the first epitaxial layer 30b', and the third epitaxial layer 30c 'are all silicon-carbon layers, wherein the carbon content of the first epitaxial layer 30a', the first epitaxial layer 30b ', and the third epitaxial layer 30c' increases in sequence.
Specifically, the carbon content in the first epitaxial layer 30a ' is 10% -20%, the carbon content in the first epitaxial layer 30b ' is 20% -50%, and the germanium content in the third epitaxial layer 30c ' is 30% -50%.
Specifically, the thickness of the first epitaxial layer 30a 'is 3 nm-7 nm, the thickness of the first epitaxial layer 30b' is 5 nm-17 nm, and the upper surface of the third epitaxial layer 30c 'is substantially flush with the upper surface of the fin 11'.
In the embodiment of the invention, the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer and the third epitaxial layer with doping concentration higher than that of the first epitaxial layer. The concentration of doping ions from the side wall of the channel region to the source region and the drain region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, short channel effects can be suppressed, and the performance of the semiconductor device can be improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (18)
1. A method of forming a semiconductor device, the method comprising:
providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, and a region, below the grid structure, of the fin parts is a channel region;
Etching fin parts on two sides of the gate structure by taking the gate structure as a mask to form a concave region on the fin part to expose the side wall of the channel region, and
Forming a source drain region in the recessed region, wherein the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, the doping concentration of doping ions of the first epitaxial layer is smaller than that of the second epitaxial layer and the third epitaxial layer,
The forming the source drain region in the recessed region comprises:
Forming the second epitaxial layer on the first epitaxial layer, and
Forming the third epitaxial layer on the second epitaxial layer;
The forming the second epitaxial layer on the first epitaxial layer includes:
Forming a second epitaxial material layer on the first epitaxial layer by a second epitaxial process, and
Performing ion implantation on the second epitaxial material layer by adopting a first ion implantation process;
The forming the third epitaxial layer on the second epitaxial layer includes:
forming a third epitaxial material layer on the second epitaxial layer by a third epitaxial process, and
Performing ion implantation on the third epitaxial material layer by adopting a second ion implantation process;
The implantation energy of the first ion implantation process is smaller than that of the second ion implantation process, the doping concentrations of doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially increased, and the first epitaxial layer covers the side wall of the channel region and the bottom of the concave region.
2. The method of claim 1, wherein the first epitaxial layer has a doping concentration of E18-E19/cc, the second epitaxial layer has a doping concentration of E20-E21/cc, and the third epitaxial layer has a doping concentration of E21-E22/cc.
3. The method of claim 1, wherein the semiconductor device is a P-type transistor, and the dopant ions of the first, second, and third epitaxial layers include at least one of boron ions, gallium ions, and indium ions.
4. The method of claim 1, wherein the semiconductor device is an N-type transistor and the dopant ions of the first, second, and third epitaxial layers comprise at least one of phosphorus ions or arsenic ions.
5. The method of forming a semiconductor device according to claim 1, wherein the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are silicon germanium layers, wherein germanium content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases sequentially.
6. The method of forming a semiconductor device according to claim 5, wherein a mole fraction of germanium in the first epitaxial layer is 10% to 20%, a mole fraction of germanium in the second epitaxial layer is 20% to 50%, and a mole fraction of germanium in the third epitaxial layer is 30% to 50%.
7. The method of forming a semiconductor device according to claim 1, wherein the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are all silicon-carbon layers, wherein the carbon content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases in order.
8. The method of forming a semiconductor device according to claim 7, wherein the semiconductor device is an N-type transistor, a mole fraction of carbon in the first epitaxial layer is 10% to 20%, a mole fraction of carbon in the second epitaxial layer is 20% to 50%, and a mole fraction of carbon in the third epitaxial layer is 30% to 50%.
9. The method of forming a semiconductor device of claim 1, wherein the gate structure comprises a dummy gate and an isolation layer covering sidewalls of the dummy gate, the forming the source drain region further comprising, prior to forming the second epitaxial layer on the first epitaxial layer:
Thinning the isolation layer;
And forming a first epitaxial layer on the bottom surface of the concave region and the side wall of the channel region by using the dummy gate and the thinned isolation layer as masks through a first epitaxial process.
10. The method of forming a semiconductor device of claim 9, wherein forming the second epitaxial layer on the first epitaxial layer after ion implantation of the second epitaxial material layer using a first ion implantation process further comprises;
And annealing the second epitaxial material layer to form a second epitaxial layer.
11. The method of claim 9, wherein forming the third epitaxial layer on the second epitaxial layer prior to the ion implanting the third epitaxial material layer using the second ion implantation process further comprises;
Forming a side wall covering the side wall of the thinned isolation layer;
the implanting ions into the third epitaxial material layer by adopting the second ion implantation process comprises the following steps:
And taking the dummy gate, the thinned isolation layer and the side wall as masks, and performing ion implantation on the third epitaxial material layer by adopting a second ion implantation process to form a third epitaxial layer.
12. The method of claim 1, wherein the first ion implantation process is performed with one or more of carbon ion, phosphorus ion, boron ion, gallium ion and arsenic ion, implantation energy of 0.5K-2K, and doping concentration of 2E14-5E14.
13. The method of claim 1, wherein the first ion implantation process comprises implanting ions of a type opposite to that of the source/drain regions.
14. The method of claim 1, wherein the first epitaxial layer has a thickness of 3 nm to 7 nm, the second epitaxial layer has a thickness of 5 nm to 17 nm, and the third epitaxial layer has an upper surface substantially flush with the upper surface of the fin.
15. A semiconductor device, the semiconductor device comprising:
The front-end device layer comprises a plurality of discrete fin parts and a grid structure crossing the fin parts, wherein the area of the fin parts below the grid structure is a channel area, and the fin parts on two sides of the grid structure are provided with concave areas;
The source drain region is located in the concave region, the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially stacked from bottom to top, the doping concentration of doping ions of the first epitaxial layer is smaller than that of doping ions of the second epitaxial layer and the third epitaxial layer, the doping concentrations of doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially increased, the first epitaxial layer covers the side wall of the channel region and the bottom of the concave region, and the implantation energy of ion implantation when the second epitaxial layer is formed is smaller than that of ion implantation when the third epitaxial layer is formed, so that the defect number in the second epitaxial layer is smaller than that in the third epitaxial layer.
16. The semiconductor device of claim 15, wherein the semiconductor device is a P-type transistor and the first, second and third epitaxial layers are silicon germanium layers, wherein the germanium content of the first, second and third epitaxial layers increases sequentially.
17. The semiconductor device of claim 15, wherein the semiconductor device is an N-type transistor and the first, second, and third epitaxial layers are all silicon-carbon layers, wherein the carbon content of the first, second, and third epitaxial layers increases in sequence.
18. The semiconductor device of claim 15, wherein the first epitaxial layer has a thickness of 3 nm-7 nm, the second epitaxial layer has a thickness of 5 nm-17 nm, and an upper surface of the third epitaxial layer is substantially flush with an upper surface of the fin.
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| CN109309009A (en) * | 2018-11-21 | 2019-02-05 | 长江存储科技有限责任公司 | A kind of semiconductor device and its manufacturing method |
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| CN109755297A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
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