CN112582471B - Semiconductor device and forming method - Google Patents

Abstract

The embodiment of the invention provides a semiconductor device and a forming method. In the embodiment of the invention, before forming the source-drain region, a diffusion region is formed in the bottom region of the side wall of the channel region. The diffusion region can reduce leakage current of the semiconductor device and can suppress short channel effects. Or the diffusion region can improve the mobility of carriers in the channel region, reduce the potential barrier of the drain end of the semiconductor device and increase the linear current of the semiconductor device. By forming the diffusion region, the performance of the semiconductor device can be improved.

Description

Semiconductor device and method for forming the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a forming method thereof.

Background Art

With the continuous development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the characteristic size of semiconductor devices is gradually shrinking. However, the performance of semiconductor devices still needs to be improved.

Summary of the invention

In view of this, an embodiment of the present invention provides a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, the method comprising:

Providing a front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins located below the gate structure is a channel region;

Using the gate structure as a mask, etching the fins on both sides of the gate structure to form a recessed area on the fins and expose the sidewalls of the channel area;

forming a diffusion region, the diffusion region extending inward from a bottom region of a sidewall of the channel region;

Source and drain regions are formed on the fins at both sides of the channel region.

Furthermore, the forming of the diffusion region specifically includes:

Using the gate structure as a mask, ion implantation is performed at the bottom of the recessed region and the bottom of the sidewall of the channel region to form an ion implantation layer including a diffusion region;

The bottom of the recessed area is etched downward to a predetermined depth using the gate structure as a mask to remove a portion of the ion implantation layer located at the bottom of the recessed area.

Furthermore, the energy of the ion implantation is 3Kev-10Kev.

Furthermore, the implanted ions of the ion implantation include ions of a type opposite to that of the doping ions of the source and drain regions, so as to reduce leakage current.

Furthermore, the implanted ions of the ion implantation include ions of the same type as the doping ions of the source and drain regions, so as to improve the carrier mobility of the channel region.

Further, the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of carbon ions, boron ions and gallium ions; or

The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions.

Further, the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions; or

The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions.

Furthermore, the depth of the diffusion region ranges from 3 nanometers to 10 nanometers.

Furthermore, the gate structure includes a dummy gate and an isolation layer covering the sidewalls of the dummy gate, and the forming of source and drain regions on the fins on both sides of the channel region specifically includes:

Thinning the isolation layer;

Using the dummy gate and the thinned isolation layer as masks, an epitaxial layer is formed on the bottom surface of the recessed area and the sidewall of the channel area by an epitaxial growth process;

forming a sidewall covering the sidewall of the thinned isolation layer;

Ions are implanted into the epitaxial layer using the dummy gate, the thinned isolation layer and the sidewall as masks.

In a second aspect, an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device comprises:

A front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, the region of the fins located below the gate structure being a channel region, and the fins on both sides of the gate structure having recessed regions;

a diffusion region extending inwardly from a bottom region of a sidewall of the channel region;

A source/drain region is located in the recessed region.

Furthermore, the diffusion region is formed by performing ion implantation at the bottom of the channel region.

Furthermore, the depth of the diffusion region ranges from 3 nanometers to 10 nanometers.

Furthermore, the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions, so as to reduce leakage current.

Furthermore, the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions, so as to improve the carrier mobility in the channel region.

In an embodiment of the present invention, before forming the source and drain regions, a diffusion region is formed in the bottom region of the sidewall of the channel region. The diffusion region can effectively block the ions between the source and drain regions formed in the recessed region from laterally diffusing into the channel region, and can improve the control capability of the gate structure over the channel region. By forming the diffusion region, the threshold voltage of the gate structure formed later can also be adjusted. Thus, the reliability of the semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

1 to 4 are schematic diagrams of structures formed in various steps of a method for forming a semiconductor device of a comparative example;

5 is a flow chart of a method for forming a semiconductor device according to a first embodiment of the present invention;

6 to 15 are schematic diagrams of structures formed in various steps of a method for forming a semiconductor device according to an embodiment of the present invention;

16 is a flow chart of a method for forming a semiconductor device according to a second embodiment of the present invention;

FIG. 17 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, words such as “include”, “including” and the like in the specification should be interpreted as including rather than being exclusive or exhaustive; that is, as including but not limited to “including”.

In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

In the description of the present invention, it needs to be understood that the term "layer" is used in its broadest sense to include a film, a cover layer or the like, and one layer may include a plurality of sub-layers.

In the description of the present invention, it is to be understood that conventional etching techniques known in the field of semiconductor manufacturing for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials are mentioned throughout the specification, including, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP) and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping the photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly on the sample.

“Spanning” means that, for example, the gate structure spans the fin, indicating that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a crossing positional relationship, and the height of the dummy gate structure is greater than the height of the fin.

Semiconductor devices are electronic devices with conductivity between good conductors and insulators. They use the special electrical properties of semiconductor materials to complete specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Existing commonly used semiconductor devices include Fin Field-Effect Transistors (Fin-FET). Fin Field-Effect Transistors include different types of transistors, such as P-type Fin Field-Effect Transistors and N-type Fin Field-Effect Transistors.

As the gate length of transistors continues to shrink, oxidation enhanced diffusion (OED) becomes a key factor affecting the diffusion of boron and phosphorus ions. Due to the oxidation enhanced diffusion effect, transient enhanced diffusion effect (TED) is caused, and transient enhanced diffusion effect not only causes short channel effects (SCE) of transistors, but also affects transistor channel mobility, junction capacitance and junction leakage current. Short channel effect is some effects that appear in transistors when the conductive channel length of metal oxide field effect transistors is reduced to more than ten nanometers or even a few nanometers. These effects mainly include the decrease of threshold voltage as the channel length decreases, the decrease of drain-induced potential barrier, carrier surface scattering, velocity saturation, ionization and hot electron effect. Therefore, a new method for forming semiconductor devices is urgently needed to suppress the transient enhanced diffusion effect of semiconductor devices, thereby effectively suppressing the short channel effect and improving the performance of semiconductor devices.

1 to 4 , the method for forming a semiconductor device of the comparative example includes the following steps:

Step S1, providing a front-end device layer. The front-end device layer includes a plurality of discrete fins and a gate structure spanning the fins, and the region of the fins located below the gate structure is a channel region.

Step S2, etching the fins using the gate structure as a mask, and etching the fins on both sides of the gate structure to form recessed areas on the fins to expose the sidewalls of the channel area.

Step S3, forming source and drain regions on the fins at both sides of the channel region.

Fig. 1 is a schematic diagram of a front-end device layer of a semiconductor device of a comparative example. Fig. 2 is a cross-sectional schematic diagram along line AA' of Fig. 1. Referring to Fig. 1 and Fig. 2, in step S1, a front-end device layer 1 is provided. The front-end device layer 1 includes a plurality of discrete fins 2 and a gate structure 3 spanning the fins 2.

The gate structure 3 includes: an isolation layer 3a and a dummy gate 3b, wherein the dummy gate 3b includes a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

A shallow trench isolation (STI) structure 4 is provided between adjacent fins 11 .

3 , in step S2 , the fins 11 on both sides of the gate structure are etched using the gate structure 3 as a mask to form recessed regions 5 on the fins 11 .

4 , in step S3 , source and drain regions 6 are formed in the recessed region 5 .

However, the semiconductor device formed by the semiconductor device forming method of the comparative example still has a short channel effect and a high leakage current.

In view of this, in order to improve the performance of semiconductor devices. An embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, the formation of a fin field effect transistor is taken as an example for explanation. Furthermore, the method of the embodiment of the present invention can be used to form a fin field effect transistor below a 10nm process node, for example, to form a 5nm or 7nm field effect transistor. Furthermore, the method of forming a fin field effect transistor by the method of the embodiment of the present invention can also be used to form other semiconductor devices such as complementary metal oxide semiconductors (CMOS), NAND flash memories (NAND flash memories) and static random access memories (SRAM).

FIG5 is a flow chart of a method for forming a semiconductor device according to a first embodiment of the present invention. As shown in FIG5 , the method for forming a semiconductor device according to a first embodiment of the present invention includes the following steps:

Step S100: providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins below the gate structure is a channel region.

Step S200: using the gate structure as a mask to etch the fins on both sides of the gate structure to form a recessed area on the fins and expose the sidewalls of the channel area.

Step S300: forming a diffusion region, wherein the diffusion region extends inward from a bottom region of a sidewall of the channel region.

Step S400: forming source and drain regions on the fins at both sides of the channel region.

6 to 15 are schematic diagrams of structures formed in various steps of the method for forming a semiconductor device according to an embodiment of the present invention.

Fig. 6 is a three-dimensional structural diagram of the front-end device layer. Fig. 7 is a cross-sectional schematic diagram of the front-end device layer along line AA'. Referring to Fig. 6 and Fig. 7, in step S100, a front-end device layer 10 is provided, wherein the front-end device layer 10 includes a plurality of discrete fins 11 and a gate structure 12 spanning the fins 11, and the region of the fins 11 below the gate structure is a channel region C.

Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI), a stacked silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof, the SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon germanium layer, a carbon silicon layer or a germanium layer) disposed on an insulating material layer, the semiconductor layer has active devices and passive devices, and the insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. Several structures such as epitaxial interface layers or strained layers can also be formed on the surface of the front-end device layer to improve the electrical performance of the semiconductor device.

The plurality of fins 11 are parallel or substantially parallel.

The gate structure 12 includes an isolation layer 12a and a dummy gate 12b, wherein the dummy gate 12b includes a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

The material of the isolation layer 12a may be silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxycarbide (SiOC). In the present embodiment, the material of the isolation layer 12a is silicon nitride.

In an optional implementation, the front-end device layer 10 also includes a shallow trench isolation structure 13. The shallow trench isolation structure 13 fills the bottom of adjacent fins 11. The shallow trench isolation structure 13 is used for electrical isolation between adjacent fins 11. The shallow trench isolation structure 13 can avoid doping ions from being implanted into the front-end device layer 10 in a subsequent ion implantation process. The material of the shallow trench isolation structure 13 can be silicon dioxide ( _SiO2 ), silicon oxynitride (SiON) or silicon oxycarbide (SiOC). The material of the shallow trench can also be a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the shallow trench isolation structure 13 is silicon dioxide.

8 , in step S200 , the fins 11 on both sides of the gate structure are etched using the gate structure 12 as a mask to form a recessed region 20 on the fins 11 and expose the sidewalls of the channel region C.

The etching process may be dry etching or wet etching. In the present embodiment, dry etching is used to etch the fin 11. The etching gas may be selected according to the selected material. Trifluoromethane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), carbon tetrafluoride (CF ₄ )/oxygen (O ₂ ) and carbon tetrafluoride (CF ₄ )/hydrogen (H ₂ ) may be selected as the etching gas. In the embodiment of the present invention, CHF ₃ is used as the etching gas, and the etching pressure may be 5-300 mTorr.

Optionally, after etching the fins, a cleaning process is used to remove impurity ions on the surface of the fins. After the wet cleaning process is used, the intermediate structure formed in the above steps is dried.

9 and 10 , in step S300 , a diffusion region 30 is formed, wherein the diffusion region 30 extends inward from a bottom region of a sidewall of the channel region C. As shown in FIG.

Specifically, forming the diffusion region includes:

Step S301 , performing ion implantation at the bottom of the recessed region and the bottom of the sidewall of the channel region using the gate structure as a mask to form an ion implantation layer including a diffusion region.

Step S302 , using the gate structure as a mask to etch the bottom of the recessed area downward to a predetermined depth, so as to remove a portion of the ion implantation layer located at the bottom of the recessed area.

9 , in step S301 , ion implantation is performed at the bottom of the recessed region 20 and the bottom of the sidewall of the channel region C using the gate structure 12 as a mask to form an ion implantation layer 30 a including a diffusion region 30 .

Specifically, the energy of the ion implantation is 3Kev-10Kev. The implantation angle of the ion implantation is 0°-15°. The implanted ions of the ion implantation are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions. The depth range of the ion implantation layer 30a is 3 nanometers-10 nanometers. The depth range can be the size of the ion implantation layer in the horizontal direction of the channel region in the cross section as shown in Figure 9, or it can be the size of the ion implantation layer in the vertical direction in the cross section as shown in Figure 9 in the bottom area of the groove.

In an optional implementation, the implanted ions of the ion implantation include ions of a type opposite to that of the doping ions of the source and drain regions, so as to reduce leakage current.

Specifically, the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of carbon ions, boron ions and gallium ions. The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions.

Specifically, the semiconductor device is a P-type field effect transistor, and the implanted ions of the ion implantation process are carbon ions, boron ions and gallium ions. The energy of the ion implantation is 7Kev, and the implantation angle is 10°. The depth of the ion implantation layer 30a is 8 nanometers. The semiconductor device is an N-type field effect transistor, and the implanted ions of the ion implantation process are phosphorus ions and gallium ions. The energy of the ion implantation is 5Kev, and the implantation angle is 13°. The depth of the ion implantation layer 30a is 6 nanometers.

By forming a diffusion region including ions of opposite doping type to the source and drain regions, ions or atoms between the source and drain regions subsequently formed in the recessed region can be effectively blocked from laterally diffusing into the channel region, thereby improving the control capability of the gate structure over the channel region.

10 , in step S302 , the bottom of the recessed region 20 is etched downward to a predetermined depth using the gate structure 12 as a mask to remove a portion of the ion implantation layer 30 a located at the bottom of the recessed region 20 .

That is to say, in this step, the ion implantation layer 30a outside the diffusion region 30 is removed. Dry etching or wet etching can be used. In this embodiment, a dry etching process is used to etch part of the ion implantation layer 30a at the bottom of the recessed region 20. The etching gas can be selected according to the selected material. Trifluoromethane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), carbon tetrafluoride (CF ₄ )/oxygen (O ₂ ) and carbon tetrafluoride (CF ₄ )/hydrogen (H ₂ ) can be selected as the etching gas. In the embodiment of the present invention, trifluoromethane is used as the etching gas, and the etching pressure can be 5-300 mTorr.

The diffusion region finally formed is shown in FIG. 11 , and the depth of the diffusion region ranges from 3 nanometers to 10 nanometers.

In other optional implementations, a mask layer may be formed in a predetermined area of the groove by a photolithography process, and then ions may be implanted into the bottom of the groove and the bottom of the sidewall of the channel region that are not covered by the mask layer.

The diffusion region is formed on the sidewall of the channel without covering the bottom of the recessed region, so that the doped ions in the bottom of the recessed region can be prevented from affecting the subsequent formation of the source and drain regions and preventing defects from being formed in the source and drain regions.

In this step, an ion implantation layer 30a including a diffusion region 30 is formed by adopting an ion implantation process, and then the ion implantation layer 30a outside the diffusion region 30 is removed to form the diffusion region 30. The diffusion region 30 is implanted with ions of the opposite type to the doping ions in the source and drain regions, so that the implanted ions fill the vacancies of the materials in the sidewall region of the channel region, making the material structure of the predetermined region of the channel region more compact. Therefore, according to the relevant theories of diffusion, the compact diffusion region can effectively block the ions or atoms between the source and drain regions formed in the recessed region from diffusing laterally into the channel region, which can reduce the leakage current, suppress the transient enhanced diffusion effect, and further suppress the short channel effect.

10 , in step S400 , source and drain regions are formed on the fins at both sides of the channel region.

Specifically, the gate structure includes a gate and an isolation layer covering the sidewalls of the gate, and the forming of source and drain regions on the fins on both sides of the channel region includes:

Step S401, thinning the isolation layer.

Step S402 : using the dummy gate and the thinned isolation layer as masks, an epitaxial layer is formed on the bottom surface of the recessed region and the sidewalls of the channel region by an epitaxial growth process.

Step S403 , forming a sidewall covering the sidewall of the thinned isolation layer.

Step S404: performing ion implantation on the epitaxial layer using the dummy gate, the thinned isolation layer and the sidewall as masks.

Referring to FIG. 11 , in step S401 , the isolation layer 12 a is thinned.

Specifically, the isolation layer 12a is thinned to a thickness of 4 nanometers to 7 nanometers. The thickness is the dimension of the isolation layer 12a in the horizontal direction in the cross section shown in FIG. 11. By thinning the isolation layer 12a, the source and drain regions can be better formed in the recessed region 20 later, and the formation of gaps at the sidewalls of the channel region due to the isolation layer 12a being too thick can be avoided.

Specifically, the isolation layer 12 a may be thinned by an etching process. The etching process may be dry etching, and specifically may be an etching process with a high selectivity to the fin 11 .

In an optional implementation, the etching gas used may be one or a combination of fluoromethane (CH ₃ F), difluoromethane (CH ₂ F ₂ ) and trifluoromethane (CHF ₃ ), and oxygen is mixed in the etching gas as an auxiliary gas. The flow rate of the etching gas is 20 standard milliliters per minute, and the etching time ranges from 20 seconds to 100 seconds.

12 , in step S402 , an epitaxial layer 40 a is formed on the bottom surface of the recessed region 20 and the sidewalls of the channel region C by an epitaxial growth process using the dummy gate 12 b and the thinned isolation layer 12 as masks.

For an N-type semiconductor device, silicon (Si) may be epitaxially grown in the recessed region 20. For a P-type semiconductor device, silicon germanium (SiGe) may be epitaxially grown in the recessed region 20. Epitaxial growth may form elevated source and drain regions in subsequent processes to facilitate the introduction of stress into the device. In-situ doping may be performed during epitaxial growth, such as doping with phosphorus (P) or boron (B).

The epitaxial layer is formed by an epitaxial growth process so that the width of the subsequently formed source and drain regions is greater than the width of the fins, which can reduce the series resistance and increase the drive current; at the same time, the position of the source and drain regions can be raised to reduce the parasitic junction capacitance, thereby improving the performance of the semiconductor device.

Specifically, the epitaxial growth process can be selected from vapor phase epitaxy (VPE), liquid phase epitaxy (Liquid-Phase Epitaxy), molecular beam epitaxy (MBE) and ion beam epitaxy (IBE).

13 , in step S403 , a sidewall spacer 50 is formed to cover the sidewall of the thinned isolation layer 12 a .

The sidewall spacer 50 is used as a mask in the subsequent ion implantation process to prevent ions from being implanted into the channel region and the dummy gate. The thickness of the sidewall spacer 50 may be 5 nanometers to 20 nanometers.

The material of the sidewall spacer 50 may be a low-K dielectric material (with a dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (with a dielectric constant less than 2.5). In this embodiment, the material of the sidewall spacer 20 is silicon dioxide.

Specifically, a chemical vapor deposition method (Chemical Vapor Deposition, CVD) can be used, such as low temperature chemical vapor deposition (Low Temperature Chemical Vapor Deposition, LTCVD), plasma chemical vapor deposition process (Plasma Chemical Vapor Deposition, PCVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and fluid chemical vapor deposition process (Fluid Chemical Vapor Deposition, FCVD).

Referring to FIG. 14 , in step S404 , ion implantation is performed on the epitaxial layer 40 a using the dummy gate 12 b , the thinned isolation layer 12 a and the spacer 50 as masks to form source and drain regions 40 .

Specifically, the implanted ions in the ion implantation process are one or more of phosphorus ions, arsenic ions, boron ions, indium (In) ions, gallium ions and antimony ions, the implantation angle of the ion implantation is 0-5 degrees, the implantation dose is 5E13atom/ ^cm2-5E15atom / ^cm2 , and the implantation energy is 6Kev-50Kev.

The dummy gate 12b, the thinned isolation layer 12a and the sidewall 50 are used as masks to prevent ions from being implanted into the channel region C and the dummy gate 12b. At the same time, the region where ions are implanted can be kept at a certain distance from the channel region C to prevent ions in the source and drain region 40 from diffusing into the channel region.

Referring to FIG. 15 , in the subsequent process, it also includes: forming an etching stop layer 60 covering the sidewalls of the fin 11, the source and drain regions 40 and the sidewalls 50. Forming a dielectric layer 70 on the etching stop layer 60. Replacing the dummy gate with a metal gate. Forming a conductive via electrically connected to the source and drain regions and the metal gate. An interconnection structure electrically connected to the conductive via. And packaging the formed semiconductor structure. To form a complete semiconductor device.

FIG16 is a flow chart of a method for forming a semiconductor device according to a second embodiment of the present invention. Referring to FIG16 , the method for forming a semiconductor device according to the second embodiment of the present invention includes the following steps:

Step S100: providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins below the gate structure is a channel region.

Step S200: using the gate structure as a mask to etch the fins on both sides of the gate structure to form a recessed area on the fins and expose the sidewalls of the channel area.

Step S300': forming a diffusion region, wherein the diffusion region extends inward from a bottom region of the sidewall of the channel region.

Step S400: forming source and drain regions on the fins at both sides of the channel region.

Among them, step S100, step S200 and step S400 may refer to the first embodiment of the present invention, and will not be described in detail here.

In step S300', a diffusion region is formed, wherein the diffusion region extends inward from a bottom region of a sidewall of the channel region.

Specifically, the difference between the first embodiment and the second embodiment of the present invention lies in the different types of ion implantation during the process of forming the diffusion region.

In a second embodiment of the present invention, the implanted ions of the ion implantation include ions of the same type as the doping ions of the source and drain regions, so as to improve the carrier mobility of the channel region.

Specifically, the semiconductor device is an N-type field effect transistor, and the implanted ions of the ion implantation process are carbon ions, boron ions and gallium ions. The energy of the ion implantation is 7Kev, and the implantation angle is 10°. The depth of the ion implantation layer 30a is 8 nanometers. The semiconductor device is a P-type field effect transistor, and the implanted ions of the ion implantation process are phosphorus ions and gallium ions. The energy of the ion implantation is 5Kev, and the implantation angle is 13°. The depth of the ion implantation layer 30a is 6 nanometers.

By injecting ions of the same type as those of the source and drain regions into the diffusion region, the linear current can be increased and the potential barrier at the drain end of the semiconductor device can be lowered.

Specifically, the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions. The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions.

Injecting ions of the same type as those doped in the source and drain regions into the diffusion region can reduce the resistance of the channel region and increase the mobility of carriers in the channel region. It can also adjust the threshold voltage of the gate structure formed subsequently. It can increase the linear current and reduce the potential barrier at the drain end of the semiconductor device. This can improve the reliability of the semiconductor device.

In an embodiment of the present invention, before forming the source and drain regions, a diffusion region is formed in the bottom region of the sidewall of the channel region. The diffusion region can reduce the leakage current of the semiconductor device and suppress the short channel effect. Alternatively, the diffusion region can increase the mobility of carriers in the channel region, reduce the potential barrier at the drain end of the semiconductor device, and increase the linear current of the semiconductor device. By forming the diffusion region, the performance of the semiconductor device can be improved.

On the other hand, an embodiment of the present invention further provides a semiconductor device, which includes: a front-end device layer, a diffusion region, and a source and drain region.

The front-end device layer includes a plurality of discrete fins and a gate structure spanning the fins. The area of the fins located below the gate structure is a channel area. The fins on both sides of the gate structure have recessed areas.

The diffusion region extends inward from a bottom region of a sidewall of the channel region.

The source and drain regions are located in the recessed region.

Fig. 17 is a cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention. Referring to Fig. 17, the semiconductor device according to the embodiment of the present invention comprises: a front-end device layer 10', a diffusion region 30' and a source-drain region 40'.

The front-end device layer 10' includes a plurality of discrete fins 11' and a gate structure 12' spanning the fins 11', the area where the fins 11' are located below the gate structure 12' is a channel region C', and the fins 11' on both sides of the gate structure 12' have recessed regions.

In an optional implementation, the front-end device layer 10' further includes a shallow trench isolation structure 13'. The shallow trench isolation structure 13' fills the bottom of the adjacent fins 11'. The shallow trench isolation structure 13' is used for electrical isolation between adjacent fins 11'. The multiple fins 11' are parallel or substantially parallel.

The gate structure 12' comprises: an isolation layer 12a' and a dummy gate 12b'. The dummy gate 12b' comprises a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

In an optional implementation, the sidewalls of the gate structure 12' are covered with sidewall spacers 50'.

The diffusion region 30' extends inward from the bottom area of the sidewall of the channel region C'.

The source and drain regions 40' are located in the recessed regions.

The diffusion region 30' is formed by ion implantation at the bottom of the channel region C'.

The depth of the diffusion region 30' is in the range of 3 nm to 10 nm.

Specifically, the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions, so as to reduce leakage current.

In the embodiment of the present invention, a diffusion region is formed in the bottom area of the sidewall of the channel region. The diffusion region can reduce the leakage current of the semiconductor device and suppress the short channel effect.

A fourth embodiment of the present invention provides a semiconductor device. The fourth embodiment differs from the third embodiment in that the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions, so as to improve the carrier mobility in the channel region.

In the embodiment of the present invention, the diffusion region can improve the mobility of carriers in the channel region, reduce the potential barrier of the drain end of the semiconductor device, and increase the linear current of the semiconductor device. By setting the diffusion region, the performance of the semiconductor device can be improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (13)

1. A method for forming a semiconductor device, characterized in that the method comprises: Providing a front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, the gate structure comprising a dummy gate and an isolation layer covering the sidewalls of the dummy gate, and the region of the fins located below the gate structure is a channel region; Using the gate structure as a mask, etching the fins on both sides of the gate structure to form a recessed area on the fins and expose the sidewalls of the channel area; forming a diffusion region, the diffusion region extending inward from a bottom region of a sidewall of the channel region; forming source and drain regions on the fins at both sides of the channel region; Wherein, forming source and drain regions on the fins on both sides of the channel region specifically includes: Thinning the isolation layer; Using the dummy gate and the thinned isolation layer as masks, an epitaxial layer is formed on the bottom surface of the recessed area and the sidewall of the channel area by an epitaxial growth process; forming a sidewall covering the sidewall of the thinned isolation layer, wherein the bottom of the sidewall covers a portion of the epitaxial layer; Using the dummy gate, the thinned isolation layer and the sidewall as masks, ion implantation is performed on the epitaxial layer to form source and drain regions. 2. The method for forming a semiconductor device according to claim 1, wherein forming the diffusion region specifically comprises: Using the gate structure as a mask, ion implantation is performed at the bottom of the recessed region and the bottom of the sidewall of the channel region to form an ion implantation layer including a diffusion region; The bottom of the recessed area is etched downward to a predetermined depth using the gate structure as a mask to remove a portion of the ion implantation layer located at the bottom of the recessed area. 3 . The method for forming a semiconductor device according to claim 2 , wherein the energy of the ion implantation is 3 KeV-10 KeV. 4 . The method for forming a semiconductor device according to claim 2 , wherein the implanted ions of the ion implantation include ions of a type opposite to that of the doped ions of the source and drain regions, so as to reduce leakage current. 5 . The method for forming a semiconductor device according to claim 2 , wherein the implanted ions of the ion implantation include ions of the same type as the doping ions of the source and drain regions, so as to improve the carrier mobility of the channel region. 6. The method for forming a semiconductor device according to claim 4, wherein the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of carbon ions, boron ions and gallium ions; or The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions. 7. The method for forming a semiconductor device according to claim 5, wherein the semiconductor device is an N-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions; or The semiconductor device is a P-type field effect transistor, and the implanted ions in the ion implantation process are one or more of phosphorus ions and gallium ions. 8 . The method for forming a semiconductor device according to claim 1 , wherein a depth of the diffusion region ranges from 3 nanometers to 10 nanometers. 9. A semiconductor device, characterized in that the semiconductor device comprises: A front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, the region of the fins located below the gate structure being a channel region, the fins on both sides of the gate structure having recessed regions, the gate structure comprising a dummy gate and an isolation layer covering the sidewalls of the dummy gate, the sidewalls of the isolation layer having sidewalls; a diffusion region extending inwardly from a bottom region of a sidewall of the channel region; A source/drain region is located in the recessed region, and the bottom of the sidewall covers a portion of the source/drain region. 10 . The semiconductor device according to claim 9 , wherein the diffusion region is formed by ion implantation at the bottom of the channel region. 11 . The semiconductor device according to claim 9 , wherein the depth of the diffusion region ranges from 3 nanometers to 10 nanometers. 12 . The semiconductor device according to claim 9 , wherein the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions to reduce leakage current. 13 . The semiconductor device according to claim 9 , wherein the type of doping ions in the diffusion region is opposite to the type of doping ions in the source and drain regions, so as to improve carrier mobility in the channel region.