CN110047753B

CN110047753B - Semiconductor device and forming method thereof

Info

Publication number: CN110047753B
Application number: CN201810038409.0A
Authority: CN
Inventors: 刘震宇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-01-16
Filing date: 2018-01-16
Publication date: 2022-03-29
Anticipated expiration: 2038-01-16
Also published as: CN110047753A

Abstract

The invention discloses a method for forming a semiconductor device and a semiconductor device. The technical solution of the embodiment of the present invention controls the boron doping concentration of the cap layer covering the germanium-silicon layer during the formation of the semiconductor device, so that the boron doping concentration of the region of the capping layer close to the top of the germanium-silicon layer is greater than that far from the top of the germanium-silicon layer. Boron doping concentration in the region. As a result, the boron concentration at the bottom of the capping layer is higher, the resistance is lower, and the DC performance of the PMOS device is improved. At the same time, the overall boron doping concentration of the capping layer remains low, so that it can have smaller parasitic capacitance and improve the AC performance of the PMOS device.

Description

Semiconductor device and forming method thereof

Technical Field

The invention relates to a semiconductor manufacturing technology, in particular to a semiconductor device and a forming method thereof.

Background

Stress Engineering (Stress Engineering) is widely used to improve carrier mobility in the channel region of semiconductor devices as the critical dimension of semiconductor fabrication processes reaches below 90 nm. In the prior art, a groove is formed in a source/drain region of a PMOS (P-channel Metal Oxide Semiconductor) device and an embedded silicon germanium (SiGe) layer is filled to introduce compressive stress (compressive stress) into a channel, so as to improve mobility of holes in the PMOS device.

In the process of forming the source/drain region using the sige layer, a cap layer (cap layer) needs to be formed on the sige layer. The cap layer is used for protecting the silicon germanium layer and is subsequently converted into a metal silicide layer serving as contact metal of a source/drain electrode. Introducing boron doping in the cap layer may further increase the carrier concentration of the source/drain regions, thereby eliminating the need for ion implantation and annealing during fabrication. However, the boron doping concentration has a large impact on the performance of PMOS devices. If the boron doping concentration is too low, a large extension resistance results. This can degrade the dc performance of the device. If the boron doping concentration is too high, a large parasitic capacitance results. This can degrade the ac performance of the device. Therefore, how to optimize the boron doping concentration of the cap layer is a key issue to improve the performance of the PMOS device.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a semiconductor device forming method and a semiconductor device, so as to optimize the boron doping concentration of a cap layer and improve the dc and ac performance of a PMOS device.

According to a first aspect of embodiments of the present invention, there is provided a method of forming a semiconductor device, wherein the method includes:

providing a semiconductor substrate comprising a PMOS region, wherein a gate structure is formed in the PMOS region on the semiconductor substrate;

forming grooves in the substrate on two sides of the grid structure;

forming a germanium-silicon layer in the groove; and

forming a cap layer which covers the top of the germanium-silicon layer and is doped with boron;

and in the cap layer, the boron doping concentration of a region close to the top of the germanium-silicon layer is greater than that of a region far away from the top of the germanium-silicon layer.

Further, the step of forming the cap layer includes:

forming a first sub-cap layer on the top of the germanium-silicon layer; and

forming a second sub-cap layer on the first sub-cap layer;

and the boron doping concentration of the first sub-cap layer is greater than that of the second sub-cap layer.

Further, the temperature for forming the first sub-cap layer is lower than the temperature for forming the second sub-cap layer.

Further, the temperature for forming the first sub-cap layer is the same as the temperature for forming the germanium-silicon layer.

Further, the thickness of the first sub-cap layer is smaller than that of the second sub-cap layer, so that the boron doping concentration of the second sub-cap layer can determine the boron doping concentration of the whole cap layer.

Further, the first sub-cap layer and the second sub-cap layer are formed through epitaxial growth.

Further, the first sub-cap layer is an in-situ boron-doped silicon layer, and the second sub-cap layer is an in-situ boron-doped germanium-silicon layer.

Further, the step of forming the first sub-cap layer is as follows:

epitaxially growing an in-situ boron-doped silicon layer of 3 nm to 5 nm at 600 ℃ to 700 ℃, wherein the boron doping concentration is 1E20atom/cm³To 1E21atom/cm³；

The step of forming the second sub-cap layer is as follows:

epitaxially growing an in-situ boron-doped germanium-silicon layer of 10 to 20 nanometers at 700 to 800 ℃, wherein the boron doping concentration is 1E18atom/cm³To 1E19atom/cm³。

According to a second aspect of embodiments of the present invention, there is provided a semiconductor device including:

a semiconductor substrate having a PMOS region;

a gate structure formed in the PMOS region;

the germanium-silicon layers are positioned in the semiconductor substrate on two sides of the grid structure; and

a cap layer which covers the top of the germanium-silicon layer and is doped with boron;

Further, the cap layer comprises:

a first sub-cap layer; and

a second sub-cap layer formed on the first sub-cap layer;

Further, the thickness of the first sub-cap layer is 3 to 5 nanometers, and the boron doping concentration is 1E20atom/cm³To 1E21atom/cm³；

The thickness of the second sub-cap layer is 10 to 20 nanometers, and the boron doping concentration is 1E18atom/cm³To 1E19atom/cm³。

Furthermore, the first sub-cap layer is a boron-doped silicon layer, and the second sub-cap layer is a boron-doped germanium-silicon layer.

Compared with the prior art, the technical scheme of the embodiment of the invention controls the boron doping concentration of the capping layer covering the germanium-silicon layer in the forming process of the semiconductor device, so that the boron doping concentration of the region close to the top of the germanium-silicon layer in the capping layer is greater than that of the region far away from the top of the silicon layer. Therefore, the boron concentration at the bottom of the cap layer is higher, the resistance is lower, and the direct current performance of the PMOS device is improved. Meanwhile, the total boron doping concentration of the cap layer is still kept low, so that the parasitic capacitance is small, and the alternating current performance of the PMOS device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;

FIG. 2 is a flow chart of forming a cap layer according to an embodiment of the present invention;

fig. 3-7 are schematic cross-sectional views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention;

FIG. 8 is a partial cross-sectional view of a prior art PMOS device;

fig. 9 is a schematic cross-sectional view of a semiconductor device of an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, "a plurality" means two or more unless otherwise specified.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.

Spatial relationship terms such as "below …", "below", "lower", "above …", "above", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.

Fig. 1 is a flow chart of a method of forming a semiconductor device according to an embodiment of the present invention. As shown in fig. 1, the semiconductor device forming method of the present embodiment includes the steps of:

step S100, providing a semiconductor substrate including a PMOS region. Wherein a gate structure is formed in a PMOS region on a semiconductor substrate.

And S200, forming grooves in the substrate on two sides of the grid structure.

And step S300, forming a germanium-silicon layer in the groove.

And step S400, forming a cap layer which covers the top of the germanium-silicon layer and is doped with boron. And in the cap layer, the boron doping concentration of a region close to the top of the germanium-silicon layer is greater than that of a region far away from the top of the germanium-silicon layer.

As shown in fig. 2, step S400 may include the steps of:

and step S410, forming a first sub-cap layer with higher boron doping concentration on the top of the embedded germanium-silicon layer.

And step S420, forming a second sub-cap layer with lower boron doping concentration on the first sub-cap layer.

Further, the boron doping concentration of the first sub-cap layer is set such that the contact resistance of the first sub-cap layer can be significantly reduced. The boron doping concentration of the second sub-cap layer is set to reduce the boron doping concentration of the whole cap layer to a desired limit, so that parameters such as parasitic capacitance and the like meet the requirement.

Thus, the boron-containing cap layer with the boron doping concentration at the bottom part larger than that of the upper region can be formed through the two-step forming manner of the step S410 and the step S420. The extension region at the bottom of the cap layer has low resistance and good direct current performance, and the boron doping concentration of the whole cap layer is kept low, so that the parasitic capacitance is low, and the alternating current performance of the PMOS device is improved.

Fig. 3-7 are schematic cross-sectional views of structures formed at various steps of a semiconductor device forming method according to an embodiment of the present invention. First, referring to fig. 3, a semiconductor substrate 10 is provided. A PMOS region, that is, a region for forming a PMOS transistor, is provided on the semiconductor substrate 10. The semiconductor substrate 10 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the semiconductor substrate so as to improve the electrical performance of the semiconductor device. An isolation structure is formed in the semiconductor substrate 10. As an example, the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The isolation structure may divide the semiconductor substrate 10 into an NMOS region and a PMOS region, only the PMOS region being shown in the figure for simplicity. It is to be understood that the semiconductor substrate 10 may also have only PMOS regions.

A gate structure 11 is formed on a semiconductor substrate 10. As an example, the gate structure includes a gate dielectric layer 11a, a gate material layer 11b, and a gate hard mask layer 11c, which are sequentially stacked. The gate dielectric layer 11a includes an oxide layer. The oxide layer may be silicon dioxide (SiO)₂) And (3) a layer. The gate material layer 11b includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer. The metal layer may be made of tungsten (W), nickel (Ni), or titanium (Ti). The conductive metal nitride layer may be a titanium nitride (TiN) layer. The conductive metal oxide layer may be iridium oxide (IrO)₂) And (3) a layer. The metal silicide layer may be a titanium silicide (TiSi) layer. The gate hard mask layer 11c includes one or more of an oxide layer, a nitride layer, an oxynitride layer, and amorphous carbon. The oxide layer may be made of Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicon Glass (PSG), tetraethyl orthosilicate (TEOS), or silicon nitrideDoped silicon glass (USG), spin-on glass (SOG), High Density Plasma (HDP), or spin-on dielectric (SOD). The nitride layer may be silicon nitride (Si)₃N₄) And (3) a layer. The oxynitride layer may be a silicon oxynitride (SiON) layer. The gate dielectric layer 11a, the gate material layer 11b and the gate hard mask layer 11c may be formed by any conventional method known to those skilled in the art, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc.

As an example, sidewall structures 12 are also formed on the semiconductor substrate 10, which are located at both sides of the gate structure 11 and abut against the gate structure. Wherein the sidewall structures 12 are comprised of oxide, nitride, or a combination thereof. The sidewall structure 12 is used to form a protection for the gate structure 11.

Referring to fig. 4, in step S200, grooves 13 are formed in the substrate at both sides of the gate structure. In order to effectively shorten the length of the device channel and meet the requirement of device size scaling, the cross-sectional shape of the groove 13 is generally sigma-shaped. As an example, the process step of forming the sigma-shaped recess may include: firstly, forming a U-shaped groove by adopting anisotropic dry etching, wherein the etching gas comprises HBr and Cl₂He and O₂And does not contain fluorine-based gas. Before the dry etching is performed, a mask layer for shielding only the NMOS region needs to be formed. As an example, the mask layer may be a buffer layer and a stress material layer stacked from bottom to top, wherein the buffer layer may be an oxide layer or a silicon oxynitride layer, and the stress material layer may be a silicon nitride layer having a tensile stress. Then, the U-shaped groove is etched again to form the sigma-shaped groove 13. The etching may be performed by a wet etching process, and the U-shaped groove may be expansion-etched to form the Σ -shaped groove 13, utilizing the characteristic that an etchant of the wet etching has different etching rates in different crystal orientations of the constituent material of the semiconductor substrate 10. As an example, the etching solution of the wet etching is a tetramethylammonium hydroxide (TMAH) solution, the temperature is 30-60 ℃, and the duration is determined according to the expected size of the sigma-shaped groove 13。

Referring to fig. 5, in step S300, an embedded sige layer 14 is formed in the recess 13. Wherein the embedded sige layer may be formed by a selective epitaxial growth process (selective epitaxy) to completely fill the recess 13. The selective epitaxial growth process may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE). Preferably, the embedded sige layer 14 is formed doped with boron. Preferably, a seed layer (not shown) may be formed on the sidewalls and bottom of the groove 13 before the selective epitaxial growth process is performed.

Referring to fig. 6, a first sub-cap layer 15 is formed on top of the embedded ge-si layer 14 at step S410.

Referring to fig. 7, in step S420, a second sub-cap layer 16 is formed on the first sub-cap layer 15. Wherein, the first sub-cap layer 15 and the second sub-cap layer 16 are both doped with boron. And the doping concentration of boron in the first sub-cap layer 15 is higher than that in the second sub-cap layer 16.

Further, the thickness of the first sub-cap 15 is small, and the thickness of the second sub-cap 16 is large, which makes it possible for the second sub-cap 16 to play a decisive role in the boron doping concentration of the entire cap. The high boron doping concentration of the first sub-cap layer 15 is favorable for improving the characteristics of the bottom region of the cap layer, and reducing the contact resistance at the bottom, thereby improving the direct current performance.

Wherein the first sub-cap layer 15 may be formed at a lower temperature and a higher boron doping concentration by using an in-situ epitaxial growth process. The first sub-cap layer 15 is an in-situ boron doped silicon layer.

The steps of forming the first sub-cap layer 15 are specifically as follows: and epitaxially growing an in-situ boron-doped silicon layer of 3-5 nm at 600-700 ℃. Wherein the boron doping concentration is 1E20atom/cm³To 1E21atom/cm³。

The lower temperature can prevent germanium (Ge) in the sige layer 14 from diffusing away from the already formed sige layer during the temperature rise process, thereby ensuring the stability of the sige layer 14. After the first sub-cap 15 is formed, it can block the diffusion of germanium at high temperature, thereby reducing the loss of germanium in the sige layer 14 in the subsequent high temperature processing steps.

Preferably, the temperature for epitaxially growing the first sub-cap layer 15 is set to be the same as the temperature for epitaxially growing the sige layer 14, so as to minimize loss of ge in the sige layer 14. Meanwhile, the formation of the germanium-silicon layer and the in-situ boron-doped silicon layer can be carried out in the same equipment, so that the time for waiting for temperature change is not needed to be spent even if the same temperature is adopted, and the efficiency of the technological process is improved.

Meanwhile, the higher boron doping concentration in the first sub-cap layer 15 can effectively improve the dc performance. It has been found that the reason for the higher extension resistance of PMOS devices when the cap layer is formed using si-containing materials is: due to the constraints of the technical conditions, the cap layer cannot be fully silicided in the subsequent process steps for forming the metal silicide, i.e., the cap layer cannot be fully converted into the metal silicide. The bottom region of the cap layer, due to the deeper locations, typically still retains its original composition. This forms a silicon "gap" 19 between the silicon germanium layer 14 and the metal silicide layer 18 as shown in fig. 8. The presence of the silicon "gap" prevents the metal silicide from contacting the silicon germanium layer, resulting in an increase in contact resistance, which in turn results in an increase in the overall extension resistance.

In this embodiment, the boron doping concentration of the first cap layer 15 is higher, which makes the boron doping concentration of the bottom region of the entire cap layer higher, and has lower contact resistance. When the capping layer is subsequently converted into the metal silicide layer, even if the capping layer cannot be completely converted into the metal silicide, the negative influence of the gap on the direct current performance of the PMOS device is greatly reduced because the contact resistance of the bottom region is low. The dc performance of the PMOS device can be improved.

The steps for forming the second sub-cap layer 16 are specifically: epitaxially growing an in-situ boron-doped SiGe layer with a boron doping concentration of 1E18atom ^ 10-20 nm at 700-800 deg.Ccm³To 1E19atom/cm³. It can be seen that the thickness of the second sub-cap layer 16 is much greater than that of the first sub-cap layer 15, and meanwhile, the boron doping concentration of the second sub-cap layer 16 is several orders of magnitude less than that of the first sub-cap layer 15. This allows the second sub-cap 16 to be formed with an effective pull down of the average boron doping concentration of the entire cap. Since the parasitic capacitance between the cap layer and the silicon germanium layer 14 is inversely proportional to the width of the depletion layer therebetween. The smaller the boron concentration, the wider the depletion layer formed and the smaller the parasitic capacitance. The smaller the parasitic capacitance, the less it will block the ac signal, which will result in a better ac performance for the PMOS device. Therefore, by setting the second sub-cap layer 16 to be thicker and have a lower boron doping concentration, the boron doping concentration of the entire cap layer can be effectively reduced, and the parasitic capacitance is reduced, so that the ac performance of the PMOS device is optimized.

Meanwhile, the lower integral boron doping concentration in the cap layer can also inhibit dislocation (dislocation) and stacking fault (stacking fault) of the cap layer in the growth process, and the crystallization quality is improved.

In this way, the overall impedance of the device can also be reduced due to the lower extension resistance and parasitic capacitance.

After forming the cap layer, a metal layer may be further formed on the cap layer to cover the cap layer, the sidewall structures 12 and the tops of the gate structures 11. The metal layer may contain a proportion of platinum or nickel. A protective layer can be further formed on the metal layer. The metal layer is prevented from being exposed to a non-inert environment and being oxidized. And then, enabling the metal to diffuse into the cap layer through an annealing process to form metal silicide with the silicon in the cap layer. As an example, the metal silicide may be NiPtSiGe. Finally, annealing the metal silicide by adopting high-temperature rapid thermal annealing. The metal silicide formed may serve as the source/drain contact metal for the PMOS device.

Fig. 9 is a schematic cross-sectional view of a semiconductor device of an embodiment of the present invention. The semiconductor device shown in fig. 9 includes a semiconductor substrate 10, a gate structure 11, an embedded sige layer 14, and a cap layer. The semiconductor substrate 10 has a PMOS region. A gate structure 11 is formed in the PMOS region to act as a gate for the PMOS device. The semiconductor device may further include a sidewall structure 12 located at both sides of the gate structure 11. The embedding is that silicon germanium layers 14 are formed in the semiconductor substrate on both sides of the gate structure 11. The silicon germanium layer 14 may be doped with boron.

In the cap layer, the boron doping concentration is greater in the region near the top of the embedded sige layer 14 than in the region remote from the top of the embedded sige layer 14. Specifically, the cap layer may include a first sub-cap layer 15 and a second sub-cap layer 16 formed by sequential epitaxial growth. The boron doping concentration of the first sub-cap layer 15 is greater than that of the second sub-cap layer 16. Meanwhile, the thickness of the first sub-cap layer 15 is smaller than that of the second sub-cap layer 16.

More specifically, the thickness of the first sub-cap layer 15 is 3 nm to 5 nm, and the boron doping concentration is 1E20atom/cm³To 1E21atom/cm³(ii) a The thickness of the second sub-cap layer 16 is 10 nm to 20 nm, and the boron doping concentration is 1E18atom/cm³To 1E19atom/cm³。

The boron concentration at the bottom of the cap layer is higher, so that the resistance is lower, and the direct current performance of the PMOS device is improved. Meanwhile, the total boron doping concentration of the cap layer is still kept low, so that the parasitic capacitance is small, and the alternating current performance of the PMOS device is improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, wherein the method comprises:

providing a semiconductor substrate including a PMOS region, a gate structure formed in the PMOS region on the semiconductor substrate;

forming grooves in the substrate on both sides of the gate structure;

forming a silicon germanium layer in the recess; and

forming a capping layer doped with boron overlying the top of the silicon germanium layer;

Wherein, in the capping layer, the boron doping concentration of the region close to the top of the germanium-silicon layer is greater than the boron doping concentration of the region far from the top of the germanium-silicon layer; the step of forming the capping layer includes:

forming a first sub-cap layer on top of the silicon germanium layer; and

forming a second sub-cap layer on the first sub-cap layer;

Wherein, the boron doping concentration of the first sub-cap layer is greater than the boron doping concentration of the second sub-cap layer;

The first sub-cap layer is an in-situ boron-doped silicon layer, and the second sub-cap layer is an in-situ boron-doped silicon germanium layer.

2 . The method of claim 1 , wherein the temperature at which the first sub-cap layer is formed is lower than the temperature at which the second sub-cap layer is formed. 3 .

3. The method according to claim 1 or 2, wherein the temperature at which the first sub-cap layer is formed is the same as the temperature at which the silicon germanium layer is formed.

4 . The method of claim 1 , wherein the thickness of the first sub-cap layer is smaller than the thickness of the second sub-cap layer so that the boron doping concentration of the second sub-cap layer can determine the entire cap. 5 . boron doping concentration of the layer.

5 . The method of claim 1 , wherein the first sub-cap layer and the second sub-cap layer are both formed by epitaxial growth. 6 .

6. The method according to claim 1, wherein the step of forming the first sub-cap layer is:

epitaxially growing an in-situ boron-doped silicon layer of 3 nanometers to 5 nanometers at 600 degrees Celsius to 700 degrees Celsius, wherein the boron doping concentration is 1E20 atom/cm ³ to 1E21 atom/cm ³ ;

The steps of forming the second sub-cap layer are:

An in-situ boron-doped silicon-germanium layer of 10 nm to 20 nm is epitaxially grown at 700 to 800 degrees Celsius, wherein the boron doping concentration is 1E18 atom/cm ³ to 1E19 atom/cm ³ .

7. A semiconductor device comprising:

a semiconductor substrate with a PMOS region;

a gate structure formed in the PMOS region;

a silicon germanium layer in the semiconductor substrate on both sides of the gate structure; and

a capping layer doped with boron covering the top of the silicon germanium layer;

Wherein, in the cap layer, the boron doping concentration of the region close to the top of the germanium-silicon layer is greater than the boron doping concentration of the region far from the top of the germanium-silicon layer;

The capping layer includes:

a first sub-cap layer; and

a second sub-cap layer formed on the first sub-cap layer;

The first sub-cap layer is a boron-doped silicon layer, and the second sub-cap layer is a boron-doped silicon germanium layer.

8 . The semiconductor device according to claim 7 , wherein the thickness of the first sub-cap layer is smaller than the thickness of the second sub-cap layer so that the boron doping concentration of the second sub-cap layer can determine the entire Boron doping concentration of the capping layer.

9 . The semiconductor device according to claim 7 , wherein the thickness of the first sub-cap layer is 3 nanometers to 5 nanometers, and the boron doping concentration is 1E20 atom/cm ³ to 1E21 atom/cm ³ ;

The thickness of the second sub-cap layer is 10 to 20 nanometers, and the boron doping concentration is 1E18 atom/cm ³ to 1E19 atom/cm ³ .