CN112366178B - Preparation method of array substrate and array substrate - Google Patents

Abstract

The invention provides a preparation method of an array substrate and the array substrate. Preparation method of array substrateComprises disposing a metal barrier layer below the copper electrode layer with a thickness of

The metal barrier layer is

Or the thickness of the copper electrode layer is

The metal barrier layer is

According to the preparation method of the array substrate, the thickness of the metal barrier layer is reduced, the wet etching compatibility of the thin copper product and the thick copper product in the mass production process of the array substrate can be effectively realized, the newly increased manufacturing cost when the mass production of the thin copper product is switched to the thick copper product is reduced, and the metal residue after etching is reduced.

Description

Preparation method of array substrate and array substrate

technical field

The present application relates to the field of liquid crystal display technology, in particular to a method for preparing an array substrate and the array substrate.

Background technique

With the advancement of information technology, display screens have gradually developed in the direction of high quality and high functionality. The more functions of the display screen, the higher the picture quality, the more complicated the thin film transistor array (Thin Film Transistor, TFT) circuit, and the longer the metal wire, which causes signal delay. Currently, the copper process has replaced the aluminum process in the panel process because copper has better electrical conductivity and lower impedance. Usually, a thin layer of metal barrier material is added between the copper metal wire and the glass substrate to increase the adhesion between the copper electrode and the glass substrate.

)已经被运用至高端显示面板制造工艺中，如8K显示技术、铟镓锌氧化物(Indium Gallium ZincOxide，IGZO)显示技术、有机发光半导体(Organic Light-Emitting Diode，OLED)显示技术。但是，厚铜产品的湿刻蚀特性与薄铜产品存在较大差异。量产化的湿刻蚀工艺中，在保证相同的CD loss(金属线上方光阻宽度与湿蚀刻后金属线宽的差值)条件下，厚铜产品因拥有更厚的金属铜厚，蚀刻后更容易出现刻蚀不尽的问题，导致金属残留的存在，从而影响面板生产工艺的整体良率。In order to further reduce the signal delay on TFT complex circuits, thick copper technology (copper thicker than

) has been applied to high-end display panel manufacturing processes, such as 8K display technology, Indium Gallium Zinc Oxide (IGZO) display technology, Organic Light-Emitting Diode (OLED) display technology. However, the wet etching characteristics of thick copper products are quite different from those of thin copper products. In the mass-production wet etching process, under the condition of ensuring the same CD loss (the difference between the width of the photoresist above the metal line and the width of the metal line after wet etching), the thicker copper product has a thicker metal copper thickness and is easier to etch. In the end, it is more likely to have the problem of insufficient etching, resulting in the existence of metal residues, which affects the overall yield of the panel production process.

Contents of the invention

In order to improve the defects of the prior art, the present application provides a method for preparing an array substrate and the array substrate. By reducing the thickness of the metal barrier layer in the thick copper product, the preparation method of the array substrate can greatly improve the wet etching compatibility between the thin copper product and the thick copper product during mass production, and reduce the thickness of the mass production thin copper product to the thick copper product. Added manufacturing overhead when switching, and reduces post-etch metal residue.

This application provides the following technical solutions:

In a first aspect, the present application provides a method for preparing an array substrate, including the following steps:

S1. Provide a substrate;

S2. disposing a first barrier metal layer on the substrate;

S3. disposing a first copper electrode layer on the surface of the first metal barrier layer; and

S4. Etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;

所述第一金属阻挡层为/>

或者所述第一铜电极层厚度为

所述第一金属阻挡层为/>

Wherein, the gate conductor layer includes a gate, a gate line and a gate pad, and the thickness of the first copper electrode layer is

The first metal barrier layer is />

Or the thickness of the first copper electrode layer is

The first metal barrier layer is />

所述第一金属阻挡层为/>

并且，所述步骤S4包括：In the preparation method of the present application, the thickness of the first copper electrode layer is

The first metal barrier layer is />

And, the step S4 includes:

S4a coating photoresist and developing on the first copper electrode layer; and

S4b wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.

所述第一金属阻挡层为/>

并且，所述步骤S4包括：In the preparation method of the present application, the thickness of the first copper electrode layer is

The first metal barrier layer is />

And, the step S4 includes:

S4c coating photoresist, developing, and baking on the first copper electrode layer; and

S4d wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.

In the preparation method of the present application, the preparation method further includes the following steps after the step S4:

S5 disposing a gate insulating layer on the gate conductor layer to cover the gate conductor layer;

S6 sequentially disposing an active layer and an ohmic contact layer on the gate insulating layer; and

S7 disposing a data line, a data pad, a source electrode and a drain electrode on the ohmic contact layer;

Wherein, at least one of the data line, the data pad, the source electrode and the drain electrode includes a second metal barrier layer and a second copper electrode layer stacked from bottom to top.

In the preparation method of the present application, a third metal barrier layer is further disposed on the second copper electrode layer.

In the preparation method of the present application, the material of the first metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

In the preparation method of the present application, the material of the second metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

In the preparation method of the present application, the material of the third metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

In the preparation method of the present application, the material of the active layer is amorphous silicon or oxide semiconductor. The array substrate prepared by the preparation method.

In the second aspect, the present application also provides the array substrate prepared by the array preparation method described in the first aspect.

所述金属阻挡层为/>

或者所述铜电极层厚度为/>

所述金属阻挡层为/>

本申请提供的阵列基板的制备方法通过减少金属阻挡层的厚度，可有效实现阵列基板量产过程中薄铜产品和厚铜产品的湿刻蚀兼容性，降低量产薄铜产品向厚铜产品切换时的新增制造费用，并减少蚀刻后金属残留。Beneficial effects: the present application provides a method for preparing an array substrate, including setting a metal barrier layer under the copper electrode layer, and the thickness of the copper electrode layer is

The metal barrier layer is />

Or the thickness of the copper electrode layer is />

The metal barrier layer is />

The preparation method of the array substrate provided by this application can effectively realize the wet etching compatibility of thin copper products and thick copper products in the mass production process of the array substrate by reducing the thickness of the metal barrier layer, and reduce the thickness of thin copper products to thick copper products in mass production. Added manufacturing overhead when switching, and reduces post-etch metal residue.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that need to be used in the description of the embodiments.

FIG. 1 is a flow chart of the first method for preparing an array substrate provided by the present application;

FIG. 2 is a schematic structural diagram of the first array substrate provided by the present application;

Fig. 3 is a flow chart of the second array substrate preparation method provided by the present application;

FIG. 4 is a schematic structural diagram of the second array substrate provided by the present application;

FIG. 5 is a flow chart of the third method for preparing an array substrate provided by the present application;

FIG. 6 is a schematic structural diagram of a third array substrate provided by the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

In the description of this application, it is to be understood that the terms "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

This application proposes a method for preparing an array substrate, including

S1. Provide a substrate;

S2. disposing a first barrier metal layer on the substrate;

S3. disposing a first copper electrode layer on the surface of the first metal barrier layer; and

S4. Etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;

所述第一金属阻挡层为/>

或者所述第一铜电极层厚度为

所述第一金属阻挡层为/>

Wherein, the gate conductor layer includes a gate, a gate line and a gate pad, and the thickness of the first copper electrode layer is

The first metal barrier layer is />

Or the thickness of the first copper electrode layer is

The first metal barrier layer is />

所述第一金属阻挡层为/>

时，所述步骤S4包括：When the thickness of the first copper electrode layer is

The first metal barrier layer is />

, the step S4 includes:

4a coating photoresist and developing on the first copper electrode layer;

4b Wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.

In some embodiments, the preparation method further includes the following steps after the step S4:

S5 disposing a gate insulating layer on the gate conductor layer to cover the gate conductor layer;

S6 sequentially disposing an active layer and an ohmic contact layer on the gate insulating layer; and

S7 disposing a data line, a data pad, a source electrode and a drain electrode on the ohmic contact layer;

Wherein, at least one of the data line, the data pad, the source electrode and the drain electrode includes a second metal barrier layer and a second copper electrode layer stacked from bottom to top.

)和薄铜产品(铜电极层厚度为/>

)在湿法蚀刻工艺中的兼容性，可以有效降低厚铜产品和薄铜产品之间工艺转换的成本，并且厚铜产品在涂布光阻、显影后省略烘烤过程，进一步减少蚀刻后的金属残留风险。The present application reduces the thickness of the metal barrier layer below the thick copper electrode layer to improve thick copper products (thickness of the copper electrode layer is

) and thin copper products (copper electrode layer thickness is />

) in the wet etching process can effectively reduce the cost of process conversion between thick copper products and thin copper products, and thick copper products omit the baking process after coating photoresist and development, further reducing the etching process Risk of metal residues.

The technical solution of the present application will now be described in conjunction with specific embodiments.

Example 1

As shown in Figures 1 and 2, this embodiment provides a method for preparing an array substrate, the array substrate is a TFT substrate 110, and the preparation method includes the following steps:

S1. Provide a substrate 110;

The substrate 110 is a transparent substrate made of other materials such as a glass substrate or resin.

S2. disposing a first barrier metal layer 121 on the substrate 110;

First, the first metal barrier layer 121 can be formed on the substrate 110 by sputtering, electroplating, thermal evaporation or other metal film-forming methods, and the metal material of the first metal barrier layer 121 is selected from molybdenum (Mo), One or more of binary alloys of molybdenum or ternary alloys of molybdenum. Wherein, the binary alloy of molybdenum is an alloy of molybdenum and titanium, the ternary alloy of molybdenum includes molybdenum and titanium, and the third metal element is at least one selected from aluminum, chromium and nickel. In some embodiments, in the binary alloy of molybdenum, the mass percentage of titanium is 0.5-0.85%; in other embodiments, in the ternary alloy of molybdenum, the mass percentage of titanium is 0.5-0.85%. 0.85%, the mass percentage of aluminum or chromium or nickel is 0.5-0.85%, and the rest is molybdenum.

S3. disposing a first copper electrode layer 122 on the surface of the first barrier metal layer 121;

The first copper electrode layer 122 is disposed on the surface of the first metal barrier layer 121 by sputtering, thermal evaporation, electroplating or other metal film forming methods.

S4. Etching the first copper electrode layer 122 and the first metal barrier layer 121 to form a gate conductor layer;

This step includes etching the first copper electrode layer 122 and the first barrier metal layer 121 according to the pattern of the gate conductor layer using a wet etching process to form a double-layer gate conductor layer.

时，所述第一金属阻挡层121为/>

或者所述第一铜电极层122厚度为/>

时，所述第一金属阻挡层121为/>

In the preparation method, the gate conductor layer includes a gate 123, a gate line and a gate pad 124, and the thickness of the first copper electrode layer 122 is

When, the first barrier metal layer 121 is />

Or the thickness of the first copper electrode layer 122 is />

When, the first barrier metal layer 121 is />

时，所述第一金属阻挡层121为/>

此时所述步骤S4包括：In some embodiments, when the thickness of the first copper electrode layer 122 is

When, the first barrier metal layer 121 is />

Now described step S4 comprises:

S4a coating photoresist and developing on the first copper electrode layer 122; and

S4b wet etching the first copper electrode layer 122 and the first metal barrier layer 121 to form a gate conductor layer.

This step specifically includes forming a photoresist (photoresist) on the surface of the first copper electrode layer 122, exposing and developing the photoresist using a patterned mask to form a photoresist mask, and then The mask pattern etches the first copper electrode layer 122 and the first metal barrier layer 121 to form patterns of the gate 123 , gate lines (not shown in the figure) and gate pads 124 . It should be noted that in this step, after the photoresist mask is formed by exposure and development, it can be directly etched without baking. Since the thickness of the copper electrode layer is large, the photolithography without baking The hardness of the glue can ensure good etching of the first copper electrode layer 122 and the first metal barrier layer 121 , reduce metal residues, and improve the yield of the array substrate. In addition, those skilled in the art can understand that this step may also include a step of removing or stripping the photoresist mask after the etching is completed.

时，所述第一金属阻挡层121为/>

此时所述步骤S4包括：In some embodiments, when the thickness of the first copper electrode layer 122 is

When, the first barrier metal layer 121 is />

Now described step S4 comprises:

S4c coating photoresist, developing and baking on the first copper electrode layer 122; and

S4d wet etching the first copper electrode layer 122 and the first barrier metal layer 121 to form a gate conductor layer.

This step specifically includes forming a photoresist (photoresist) on the surface of the first copper electrode layer 122, exposing and developing the photoresist using a patterned mask to form a photoresist mask, and then The mask pattern is used to etch the first copper electrode layer 122 and the first metal barrier layer 121 to form patterns of the gate 123 , gate lines and gate pads 124 . It should be noted that in this step, the formation of the photoresist mask is baked, including baking before development and baking after development, and etching after baking. Since the thickness of the copper electrode layer is small , the hardness of the baked photoresist is higher, which can ensure a good etching effect of thin copper products and achieve good compatibility when the production line switches between thick copper products and thin copper products. In addition, those skilled in the art can understand that this step may also include a step of removing or stripping the photoresist mask after the etching is completed.

时，所述第一金属阻挡层121为/>

或者所述第一铜电极层122厚度为/>

时，所述第一金属阻挡层121为/>

This embodiment also provides an array substrate obtained by the above method. As shown in FIG. Conductor layer, the gate conductor layer includes a gate 123, a gate line (not shown in the figure) and a gate pad 124; wherein, the thickness of the first copper electrode layer 122 is

When, the first barrier metal layer 121 is />

Or the thickness of the first copper electrode layer 122 is />

When, the first barrier metal layer 121 is />

Example 2

This embodiment provides a method for preparing an array substrate, as shown in FIG. 3 and FIG. 4 , which differs from the method for preparing an array substrate in Embodiment 1 only in that the following steps are further included after step S4:

S5 disposing a gate insulating layer 125 on the gate conductor layer to cover the gate conductor layer;

其中，栅极绝缘层125可以选用氮化物(例如SiNx)或者氧化物(例如SiOx)等材料。A method such as chemical vapor deposition (PCVD) can be used to deposit a gate 123 insulating layer on the gate conductor layer. Specifically, a plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit the gate 123 insulating layer. layer. The deposition thickness of the gate insulating layer 125 can be

Wherein, the gate insulating layer 125 may be made of materials such as nitride (eg SiNx) or oxide (eg SiOx).

S6 sequentially disposing an active layer 206 and an ohmic contact layer 205 on the gate insulating layer 125;

的活性材料层和欧姆接触层205。然后，在活性材料层上形成光刻胶，再用刻画有图形的掩膜版对光刻胶进行曝光和显影，形成光刻胶掩膜，再根据光刻胶掩膜图案对所述活性材料层进行刻蚀，形成活性层206图案。其中，所述活性层206为非晶硅或氧化物半导体层，所述氧化物半导体层可以选自氧化铟镓锌、氧化铟锡锌、氧化铪铟锌或氧化铟锌中的至少一种。所述欧姆接触层205可以是本领域已知的掺杂半导体材料，例如N型掺杂硅。First, after completing the gate insulating layer 125 deposition process, continue to form an active layer 206, which can be formed by PECVD or other methods with a thickness of

active material layer and ohmic contact layer 205 . Then, a photoresist is formed on the active material layer, and then the photoresist is exposed and developed with a patterned mask to form a photoresist mask, and then the active material is processed according to the photoresist mask pattern. The layer is etched to form a pattern of the active layer 206 . Wherein, the active layer 206 is amorphous silicon or an oxide semiconductor layer, and the oxide semiconductor layer may be selected from at least one of indium gallium zinc oxide, indium tin zinc oxide, hafnium indium zinc oxide or indium zinc oxide. The ohmic contact layer 205 can be a doped semiconductor material known in the art, such as N-type doped silicon.

S7 disposing a data line 212, a data pad 213, a source electrode 210, and a drain electrode 211 on the ohmic contact layer 205;

Wherein, at least one of the data line 212, the data pad 213, the source electrode 210 and the drain electrode 211 includes a second metal barrier layer 201 and a second copper electrode layer 202 stacked from bottom to top;

First, a second metal barrier layer 201 can be formed on the substrate 110 by sputtering, electroplating, thermal evaporation or other metal film-forming methods, and the metal material of the second metal barrier layer 201 is selected from molybdenum (Mo), One or more of binary alloys of molybdenum or ternary alloys of molybdenum. Wherein, the binary alloy of molybdenum is an alloy of molybdenum and titanium, the ternary alloy of molybdenum includes molybdenum and titanium, and the third metal element is at least one selected from aluminum, chromium and nickel. In some embodiments, in the binary alloy of molybdenum, the mass percentage of titanium is 0.5-0.85%; in other embodiments, in the ternary alloy of molybdenum, the mass percentage of titanium is 0.5-0.85%. 0.85%, the mass percentage of aluminum or chromium or nickel is 0.5-0.85%, and the rest is molybdenum.

The second copper electrode layer 202 is disposed on the surface of the second metal barrier layer 201 by sputtering, thermal evaporation, electroplating or other metal film forming methods.

This step includes etching the second copper electrode layer 202 and the second metal barrier layer 201 according to a pattern by using a wet etching process to form a data line 212, a data pad 213, a source electrode 210 and a drain electrode in a double-layer metal layer structure. Pole 211.

时，所述第二金属阻挡层201为/>

或者所述第二铜电极层202厚度为/>

时，所述第二金属阻挡层201为/>

In the preparation method, the thickness of the second copper electrode layer 202 is

When, the second barrier metal layer 201 is />

Or the thickness of the second copper electrode layer 202 is />

When, the second barrier metal layer 201 is />

时，所述第二金属阻挡层201为/>

此时所述步骤S4包括：In some embodiments, when the thickness of the second copper electrode layer 202 is

When, the second barrier metal layer 201 is />

Now described step S4 comprises:

S4a coating photoresist and developing on the second copper electrode layer 202; and

S4b wet etching the second copper electrode layer 202 and the second barrier metal layer 201 to form a data line 212 , a data pad 213 , a source electrode 210 and a drain electrode 211 .

This step specifically includes forming a photoresist (photoresist) on the surface of the second copper electrode layer 202, exposing and developing the photoresist using a patterned mask to form a photoresist mask, and then The mask pattern etches the second copper electrode layer 202 and the second metal barrier layer 201 to form patterns of data lines 212 , data pads 213 , source electrodes 210 and drain electrodes 211 . It should be noted that in this step, after the photoresist mask is formed by exposure and development, it can be directly etched without baking. Since the thickness of the copper electrode layer is large, the photolithography without baking The hardness of the glue can ensure good etching of the second copper electrode layer 202 and the second metal barrier layer 201 , reduce metal residues, and improve the yield of the array substrate. In addition, those skilled in the art can understand that this step may also include a step of removing or stripping the photoresist mask after the etching is completed.

时，所述第二金属阻挡层201为/>

此时所述步骤S4包括：In some embodiments, when the thickness of the second copper electrode layer 202 is

When, the second barrier metal layer 201 is />

Now described step S4 comprises:

S4c coating photoresist, developing and baking on the second copper electrode layer 202; and

S4d wet etching the second copper electrode layer 202 and the second barrier metal layer 201 to form data lines 212 , data pads 213 , source electrodes 210 and drain electrodes 211 .

This step specifically includes forming a photoresist (photoresist) on the surface of the second copper electrode layer 202, exposing and developing the photoresist using a patterned mask to form a photoresist mask, and then The mask pattern etches the second copper electrode layer 202 and the second metal barrier layer 201 to form patterns of data lines 212 , data pads 213 , source electrodes 210 and drain electrodes 211 . It should be noted that in this step, the formation of the photoresist mask is baked, including baking before development and baking after development, and etching after baking. Since the thickness of the copper electrode layer is small , the hardness of the baked photoresist is higher, which can ensure a good etching effect of thin copper products and achieve good compatibility when the production line switches between thick copper products and thin copper products. In addition, those skilled in the art can understand that this step may also include a step of removing or stripping the photoresist mask after the etching is completed.

In some embodiments, the thickness and/or material of the first barrier metal layer 121 is the same as that of the second barrier metal layer 201; of course, the thickness and material of the two may also be different, or only the thickness or material One of them is the same.

This embodiment also provides an array substrate prepared by the above preparation method, as shown in FIG. 4 , including a substrate 110, and a gate conductor layer, a gate insulating layer 125, an active layer 206, an ohmic Contact layer 205, data line 212, data pad 213, source electrode 210 and drain electrode 211, wherein the gate conductor layer includes the gate 123 formed by the first metal barrier layer 121, the first copper electrode layer 122, the gate line and The gate pad 124 , the data line 212 , the data pad 213 , the source 210 and the drain 211 include the second barrier metal layer 201 and the second copper electrode layer 202 .

Example 3

时，所述第二金属阻挡层201为/>

或者所述第二铜电极层202厚度为/>

时，所述第二金属阻挡层201为/>

The embodiment of the present invention also provides a preparation method of an array substrate, as shown in FIG. 5 and FIG. A third barrier metal layer 203 is provided. The step of disposing the third barrier metal layer 203 is the same as that of the second barrier metal layer 201 . In some embodiments, the thickness and/or material of the third barrier metal layer 203 is the same as that of the second barrier metal layer 201; of course, the thickness and material of the two may also be different, or only the thickness or material One of them is the same. Wherein, the thickness of the second copper electrode layer 202 is

When, the second barrier metal layer 201 is />

Or the thickness of the second copper electrode layer 202 is />

When, the second barrier metal layer 201 is />

In some embodiments, when the array substrate contains the third barrier metal layer 203 , the second barrier metal layer 201 , the second copper electrode layer 202 and the third barrier metal layer 203 are disposed first, and then etched.

This embodiment also provides an array substrate prepared by the above preparation method, as shown in FIG. 6 , including a substrate 110, and a gate conductor layer, a gate insulating layer 125, an active layer 206, an ohmic Contact layer 205, data line 212, data pad 213, source electrode 210 and drain electrode 211, wherein the gate conductor layer includes the gate 123 formed by the first metal barrier layer 121, the first copper electrode layer 122, the gate line and The gate pad 124 , the data line 212 , the data pad 213 , the source electrode 210 and the drain electrode 211 include a second barrier metal layer 201 , a second copper electrode layer 202 and a third barrier metal layer 203 .

The method for preparing the array substrate provided in the present application may further include the step of providing structures such as pixel electrodes and passivation layers.

The preparation method of an array substrate provided by the embodiment of the present application and the array substrate have been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present application. The description of the above embodiment is only for helping Understand the method of this application and its core idea; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not understood as a limitation on the application.

Claims (8)

1. The preparation method of the array substrate is characterized by comprising the following steps:

s1, providing a substrate;

s2, arranging a first metal barrier layer on the substrate;

s3, arranging a first copper electrode layer on the surface of the first metal barrier layer; and

s4, etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;

wherein the gate conductor layer comprises a gate electrode, a gate line, and a gate pad, the first copper electrode layer has a thickness of 5000-10000A, the first metal barrier layer is 50-200A, or the first copper electrode layer has a thickness of 2000-5000A, the first metal barrier layer is 200-500A;

the first copper electrode layer has a thickness of 5000-10000A, the first metal barrier layer is 50-200A, and step S4 comprises:

s4a, coating a photoresist on the first copper electrode layer and developing; and

s4b, etching the first copper electrode layer and the first metal barrier layer by a wet method to form a gate conductor layer;

the first copper electrode layer has a thickness of 2000-5000A, the first metal barrier layer is 200-500A, and step S4 comprises:

s4c, coating a photoresist on the first copper electrode layer, developing and baking; and

and S4d, etching the first copper electrode layer and the first metal barrier layer by a wet method to form a gate conductor layer.

2. The method for manufacturing an array substrate according to claim 1, further comprising the following steps after the step S4:

s5, arranging a grid electrode insulating layer on the grid conductor layer to cover the grid conductor layer;

s6, sequentially arranging an active layer and an ohmic contact layer on the grid electrode insulating layer; and

s7, arranging a data line, a data bonding pad, a source electrode and a drain electrode on the ohmic contact layer;

and at least one of the data line, the data bonding pad, the source electrode and the drain electrode comprises a second metal barrier layer and a second copper electrode layer which are stacked from bottom to top.

3. The method for preparing the array substrate of claim 2, wherein a third metal barrier layer is further disposed on the second copper electrode layer.

4. The method for manufacturing the array substrate according to claim 1, wherein the material of the first metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

5. The method for manufacturing the array substrate according to claim 2, wherein the material of the second metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

6. The method for manufacturing the array substrate according to claim 3, wherein the material of the third metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.

7. The method of claim 2, wherein the active layer is made of amorphous silicon or an oxide semiconductor.

8. An array substrate prepared by the method of any one of claims 1 to 7.

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