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CN112366178A - Preparation method of array substrate and array substrate - Google Patents

Preparation method of array substrate and array substrate Download PDF

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Publication number
CN112366178A
CN112366178A CN202011239652.2A CN202011239652A CN112366178A CN 112366178 A CN112366178 A CN 112366178A CN 202011239652 A CN202011239652 A CN 202011239652A CN 112366178 A CN112366178 A CN 112366178A
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layer
metal barrier
barrier layer
array substrate
copper electrode
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CN112366178B (en
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刘净
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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Abstract

本发明提供一种阵列基板的制备方法及阵列基板。所述阵列基板的制备方法包括在铜电极层下方设置金属阻挡层，且铜电极层厚度为

Figure DDA0002768002090000011
所述金属阻挡层为
Figure DDA0002768002090000013
或者所述铜电极层厚度为
Figure DDA0002768002090000012
所述金属阻挡层为
Figure DDA0002768002090000014
本申请提供的阵列基板的制备方法通过减少金属阻挡层的厚度，可有效实现阵列基板量产过程中薄铜产品和厚铜产品的湿刻蚀兼容性，降低量产薄铜产品向厚铜产品切换时的新增制造费用，并减少蚀刻后金属残留。

Figure 202011239652

The invention provides a preparation method of an array substrate and an array substrate. The preparation method of the array substrate includes arranging a metal barrier layer under the copper electrode layer, and the thickness of the copper electrode layer is

Figure DDA0002768002090000011
The metal barrier is
Figure DDA0002768002090000013
Or the thickness of the copper electrode layer is
Figure DDA0002768002090000012
The metal barrier is
Figure DDA0002768002090000014
The preparation method of the array substrate provided by the present application can effectively realize the wet etching compatibility of thin copper products and thick copper products in the mass production process of the array substrate by reducing the thickness of the metal barrier layer, and reduce the mass production of thin copper products to thick copper products. Added manufacturing overhead when switching, and reduced metal residue after etching.

Figure 202011239652

Description

Preparation method of array substrate and array substrate
Technical Field
The application relates to the technical field of liquid crystal display, in particular to a preparation method of an array substrate and the array substrate.
Background
With the progress of information technology, the display screen has gradually advanced toward high quality and high functionality. The more functions of the display panel, the higher the image quality, the more complicated a Thin Film Transistor array (TFT) circuit is, and the longer the metal line is, thereby causing a delay in signal. Currently, copper processes have replaced aluminum processes in panel processes because copper has better conductivity and lower resistance. Typically, a thin layer of metal barrier material is added between the copper metal line and the glass substrate to increase the adhesion between the copper electrode and the glass substrate.
To further reduce signal delay on TFT complex circuits, thick copper technology (copper thickness greater than
Figure BDA0002768002070000011
) Have been applied to high-end display panel manufacturing processes, such as 8K display technology, Indium Gallium Zinc Oxide (IGZO) display technology, and Organic Light-Emitting Diode (OLED) display technology. However, the wet etching characteristics of thick copper products are significantly different from those of thin copper products. In the mass production wet etching process, under the condition of ensuring the same CD loss (difference between the photoresist width above the metal line and the metal line width after wet etching), the problem of incomplete etching after etching is more likely to occur due to the thicker metal copper thickness of the thick copper product, so that the metal residue exists, and the overall yield of the panel production process is affected.
Disclosure of Invention
In order to overcome the defects in the prior art, the present application provides a method for manufacturing an array substrate and an array substrate. According to the preparation method of the array substrate, the thickness of the metal barrier layer in the thick copper product is reduced, so that the wet etching compatibility of the thin copper product and the thick copper product during mass production can be greatly improved, the newly increased manufacturing cost during switching from the mass production of the thin copper product to the thick copper product is reduced, and the metal residue after etching is reduced.
The application provides the following technical scheme:
in a first aspect, the present application provides a method for manufacturing an array substrate, including the following steps:
s1, providing a substrate;
s2, arranging a first metal barrier layer on the substrate;
s3, arranging a first copper electrode layer on the surface of the first metal barrier layer; and
s4, etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;
the gate conductor layer comprises a gate, a gate line and a gate pad, and the first copper electrode layer has a thickness of
Figure BDA0002768002070000021
The first metal barrier layer is
Figure BDA0002768002070000022
Or the first copper electrode layer has a thickness of
Figure BDA0002768002070000023
The first metal barrier layer is
Figure BDA0002768002070000024
In the preparation method, the thickness of the first copper electrode layer is
Figure BDA0002768002070000025
The first metal barrier layer is
Figure BDA0002768002070000026
Further, the step S4 includes:
s4a coating photoresist on the first copper electrode layer and developing; and
and S4b, wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.
In the preparation method, the thickness of the first copper electrode layer is
Figure BDA0002768002070000027
The first metal barrier layer is
Figure BDA0002768002070000028
Further, the step S4 includes:
s4c coating photoresist on the first copper electrode layer, developing and baking; and
and S4d, wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.
In the preparation method of the present application, the preparation method further includes, after the step S4, the steps of:
s5 disposing a gate insulating layer on the gate conductor layer to cover the gate conductor layer;
s6, sequentially arranging an active layer and an ohmic contact layer on the gate insulating layer; and
s7, arranging a data line, a data pad, a source electrode and a drain electrode on the ohmic contact layer;
and at least one of the data line, the data bonding pad, the source electrode and the drain electrode comprises a second metal barrier layer and a second copper electrode layer which are stacked from bottom to top.
In the preparation method, a third metal barrier layer is further arranged on the second copper electrode layer.
In the preparation method, the material of the first metal barrier layer is selected from one or more of molybdenum, binary alloy of molybdenum or ternary alloy of molybdenum.
In the preparation method, the material of the second metal barrier layer is selected from one or more of molybdenum, binary alloy of molybdenum or ternary alloy of molybdenum.
In the preparation method, the material of the third metal barrier layer is selected from one or more of molybdenum, binary alloy of molybdenum or ternary alloy of molybdenum.
In the preparation method of the present application, the material of the active layer is amorphous silicon or an oxide semiconductor. The array substrate prepared by the preparation method.
In a second aspect, the present application further provides an array substrate prepared by the method for preparing an array according to the first aspect.
Has the advantages that: the application provides a preparation method of an array substrate, which comprises the step of arranging a metal barrier layer below a copper electrode layer, wherein the thickness of the copper electrode layer is
Figure BDA0002768002070000031
The metal barrier layer is
Figure BDA0002768002070000032
Or the thickness of the copper electrode layer is
Figure BDA0002768002070000033
The metal barrier layer is
Figure BDA0002768002070000034
According to the preparation method of the array substrate, the thickness of the metal barrier layer is reduced, the wet etching compatibility of the thin copper product and the thick copper product in the mass production process of the array substrate can be effectively realized, the newly increased manufacturing cost when the mass production of the thin copper product is switched to the thick copper product is reduced, and the metal residue after etching is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below.
Fig. 1 is a flowchart of a first method for manufacturing an array substrate according to the present disclosure;
fig. 2 is a schematic structural diagram of a first array substrate provided in the present application;
fig. 3 is a flowchart of a second method for manufacturing an array substrate according to the present application;
fig. 4 is a schematic structural diagram of a second array substrate provided in the present application;
fig. 5 is a flowchart of a method for manufacturing a third array substrate according to the present application;
fig. 6 is a schematic structural diagram of a third array substrate provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
The application provides a preparation method of an array substrate, which comprises the following steps
S1, providing a substrate;
s2, arranging a first metal barrier layer on the substrate;
s3, arranging a first copper electrode layer on the surface of the first metal barrier layer; and
s4, etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;
the gate conductor layer comprises a gate, a gate line and a gate pad, and the first copper electrode layer has a thickness of
Figure BDA0002768002070000041
The first metal barrier layer is
Figure BDA0002768002070000042
Or the first copper electrode layer has a thickness of
Figure BDA0002768002070000043
The first metal barrier layer is
Figure BDA0002768002070000044
When the thickness of the first copper electrode layer is
Figure BDA0002768002070000045
The first metal barrier layer is
Figure BDA0002768002070000046
Then, the step S4 includes:
4a, coating a photoresist on the first copper electrode layer and developing;
4b, wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.
In some embodiments, the preparation method further comprises the following step after the step S4:
s5 disposing a gate insulating layer on the gate conductor layer to cover the gate conductor layer;
s6, sequentially arranging an active layer and an ohmic contact layer on the gate insulating layer; and
s7, arranging a data line, a data pad, a source electrode and a drain electrode on the ohmic contact layer;
and at least one of the data line, the data bonding pad, the source electrode and the drain electrode comprises a second metal barrier layer and a second copper electrode layer which are stacked from bottom to top.
According to the method, the thickness of the metal barrier layer below the thick copper electrode layer is reduced, so that the thick copper product during the production of the array substrate is improved (the thickness of the copper electrode layer is
Figure BDA0002768002070000047
) And thin copper products (copper electrode layer thickness of
Figure BDA0002768002070000048
) The compatibility in the wet etching process can effectively reduce the process conversion cost between thick copper products and thin copper products, and the thick copper products areThe product omits the baking process after coating and developing the photoresist, thereby further reducing the risk of metal residue after etching.
The technical solution of the present application will now be described with reference to specific embodiments.
Example 1
As shown in fig. 1 and fig. 2, the present embodiment provides a method for manufacturing an array substrate, where the array substrate is a TFT substrate 110, and the method includes the following steps:
s1, providing a substrate 110;
the substrate 110 is a glass substrate or a transparent substrate made of other materials such as resin.
S2, arranging a first metal barrier layer 121 on the substrate 110;
first, a first metal barrier layer 121 may be formed on the substrate 110 by sputtering, electroplating, thermal evaporation, or other metal film forming methods, and a metal material of the first metal barrier layer 121 may be selected from one or more of molybdenum (Mo), a binary alloy of molybdenum, or a ternary alloy of molybdenum. The binary alloy of molybdenum is an alloy of molybdenum and titanium, the ternary alloy of molybdenum comprises molybdenum and titanium, and the third metal element is at least one selected from aluminum, chromium and nickel. In some embodiments, the binary alloy of molybdenum has a titanium content of 0.5-0.85% by weight; in other embodiments, the ternary alloy of molybdenum comprises, by weight, 0.5 to 0.85% titanium, 0.5 to 0.85% aluminum, chromium, or nickel, and the balance molybdenum.
S3, arranging a first copper electrode layer 122 on the surface of the first metal barrier layer 121;
a first copper electrode layer 122 is disposed on the surface of the first metal barrier layer 121 by sputtering, thermal evaporation, electroplating or other metal film forming methods.
S4, etching the first copper electrode layer 122 and the first metal barrier layer 121 to form a gate conductor layer;
the step includes etching the first copper electrode layer 122 and the first metal barrier layer 121 according to a gate conductor layer pattern by using a wet etching process to form a gate conductor layer having a double-layer structure.
In the preparation method, the gate conductor layer includes a gate electrode 123, a gate line and a gate pad 124, and the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000051
When the first metal barrier layer 121 is
Figure BDA0002768002070000052
Or the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000053
When the first metal barrier layer 121 is
Figure BDA0002768002070000054
In some embodiments, when the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000055
When the first metal barrier layer 121 is
Figure BDA0002768002070000056
At this time, the step S4 includes:
s4a coating photoresist on the first copper electrode layer 122 and developing; and
s4b wet etching the first copper electrode layer 122 and the first metal barrier layer 121 to form a gate conductor layer.
The step specifically includes forming a photoresist (photoresist) on the surface of the first copper electrode layer 122, exposing and developing the photoresist by using a mask plate with a pattern, forming a photoresist mask, and etching the first copper electrode layer 122 and the first metal barrier layer 121 according to the photoresist mask pattern, so as to form patterns of a gate electrode 123, a gate line (not shown in the figure) and a gate pad 124. It should be noted that, in this step, after the photoresist mask is formed through exposure and development, etching may be directly performed without baking, and due to the fact that the thickness of the copper electrode layer is large, the hardness of the photoresist without baking may ensure good etching of the first copper electrode layer 122 and the first metal barrier layer 121, so that metal residues are reduced, and the yield of the array substrate is improved. In addition, as will be understood by those skilled in the art, the present step may further include a step of removing or stripping the photoresist mask after the etching is completed.
In some embodiments, when the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000061
When the first metal barrier layer 121 is
Figure BDA0002768002070000062
At this time, the step S4 includes:
s4c coating photoresist on the first copper electrode layer 122, developing and baking; and
s4d wet etching the first copper electrode layer 122 and the first metal barrier layer 121 to form a gate conductor layer.
The method specifically comprises the steps of forming a photoresist (photoresist) on the surface of the first copper electrode layer 122, exposing and developing the photoresist by using a mask with patterns carved thereon to form a photoresist mask, and etching the first copper electrode layer 122 and the first metal barrier layer 121 according to the photoresist mask pattern to form the patterns of a grid electrode 123, a grid line and a grid pad 124. It should be noted that, in this step, the formation of the photoresist mask is baked, including baking before development and baking after development, and then etching is performed after baking, and since the thickness of the copper electrode layer is smaller, the baked photoresist has higher hardness, a good etching effect of the thin copper product can be ensured, and good compatibility of the production line when switching between the thick copper product and the thin copper product is achieved. In addition, as will be understood by those skilled in the art, the present step may further include a step of removing or stripping the photoresist mask after the etching is completed.
The present embodiment further provides an array substrate obtained by the above method, as shown in fig. 2, the array substrate includes a substrate 110, and a gate conductor layer composed of a first metal barrier layer 121 and a first copper electrode layer 122 sequentially disposed on the substrate 110, where the gate conductor layer includes a first metal layer and a second copper layer, and the first metal layer 121 and the second copper layer 122 are disposed on the first metal layer and the second copper layer, respectivelyA gate electrode 123, a gate line (not shown), and a gate pad 124; wherein the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000063
When the first metal barrier layer 121 is
Figure BDA0002768002070000064
Or the first copper electrode layer 122 has a thickness of
Figure BDA0002768002070000065
When the first metal barrier layer 121 is
Figure BDA0002768002070000066
Example 2
This embodiment provides a method for manufacturing an array substrate, as shown in fig. 3 and 4, which is different from the method for manufacturing an array substrate of embodiment 1 only in that the method further includes the following steps after step S4:
s5 disposing a gate insulating layer 125 on the gate conductor layer to cover the gate conductor layer;
a gate electrode 123 insulating layer may be deposited on the gate conductor layer using chemical vapor deposition (PCVD), and in particular, the gate electrode 123 insulating layer may be deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The gate insulating layer 125 may be deposited to a thickness of
Figure BDA0002768002070000071
The gate insulating layer 125 may be made of nitride (e.g., SiNx) or oxide (e.g., SiOx).
S6 disposing an active layer 206 and an ohmic contact layer 205 on the gate insulating layer 125 in sequence;
first, after the gate insulating layer 125 deposition process is completed, an active layer 206 is formed, which may be formed to a thickness of PECVD or the like
Figure BDA0002768002070000072
And an ohmic contact layer 205. Then, photoresist is formed on the active material layer, the photoresist is exposed and developed by using a mask plate with a pattern engraved on the photoresist to form a photoresist mask, and the active material layer is etched according to the photoresist mask pattern to form an active layer 206 pattern. The active layer 206 is amorphous silicon or an oxide semiconductor layer, and the oxide semiconductor layer may be at least one selected from indium gallium zinc oxide, indium tin zinc oxide, hafnium indium zinc oxide, or indium zinc oxide. The ohmic contact layer 205 may be a doped semiconductor material known in the art, such as N-type doped silicon.
S7 disposing a data line 212, a data pad 213, a source electrode 210 and a drain electrode 211 on the ohmic contact layer 205;
at least one of the data line 212, the data pad 213, the source electrode 210 and the drain electrode 211 comprises a second metal barrier layer 201 and a second copper electrode layer 202 which are stacked from bottom to top;
first, a second metal barrier layer 201 may be formed on the substrate 110 by sputtering, electroplating, thermal evaporation, or other metal film forming methods, and a metal material of the second metal barrier layer 201 is selected from one or more of molybdenum (Mo), a binary alloy of molybdenum, or a ternary alloy of molybdenum. The binary alloy of molybdenum is an alloy of molybdenum and titanium, the ternary alloy of molybdenum comprises molybdenum and titanium, and the third metal element is at least one selected from aluminum, chromium and nickel. In some embodiments, the binary alloy of molybdenum has a titanium content of 0.5-0.85% by weight; in other embodiments, the ternary alloy of molybdenum comprises, by weight, 0.5 to 0.85% titanium, 0.5 to 0.85% aluminum, chromium, or nickel, and the balance molybdenum.
And a second copper electrode layer 202 is arranged on the surface of the second metal barrier layer 201 by adopting sputtering, thermal evaporation, electroplating or other metal film forming methods.
The step includes etching the second copper electrode layer 202 and the second metal barrier layer 201 according to a pattern by using a wet etching process to form a data line 212, a data pad 213, a source electrode 210, and a drain electrode 211 of a double-layer metal layer structure.
In the preparation method, the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000081
When the second metal barrier layer 201 is
Figure BDA0002768002070000082
Or the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000083
When the second metal barrier layer 201 is
Figure BDA0002768002070000084
In some embodiments, when the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000085
When the second metal barrier layer 201 is
Figure BDA0002768002070000086
At this time, the step S4 includes:
s4a coating photoresist on the second copper electrode layer 202 and developing; and
s4b wet etching the second copper electrode layer 202 and the second metal barrier layer 201 to form a data line 212, a data pad 213, a source electrode 210, and a drain electrode 211.
The method specifically comprises the steps of forming a photoresist (photoresist) on the surface of the second copper electrode layer 202, exposing and developing the photoresist by using a mask plate with a pattern carved thereon to form a photoresist mask, and etching the second copper electrode layer 202 and the second metal barrier layer 201 according to the photoresist mask pattern to form patterns of the data line 212, the data pad 213, the source electrode 210 and the drain electrode 211. It should be noted that, in this step, after the photoresist mask is formed through exposure and development, etching may be directly performed without baking, and due to the fact that the thickness of the copper electrode layer is large, the hardness of the photoresist without baking may ensure good etching of the second copper electrode layer 202 and the second metal barrier layer 201, reduce metal residues, and improve the yield of the array substrate. In addition, as will be understood by those skilled in the art, the present step may further include a step of removing or stripping the photoresist mask after the etching is completed.
In some embodiments, when the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000087
When the second metal barrier layer 201 is
Figure BDA0002768002070000088
At this time, the step S4 includes:
s4c coating photoresist on the second copper electrode layer 202, developing and baking; and
s4d wet etching the second copper electrode layer 202 and the second metal barrier layer 201 to form a data line 212, a data pad 213, a source electrode 210, and a drain electrode 211.
The method specifically comprises the steps of forming a photoresist (photoresist) on the surface of the second copper electrode layer 202, exposing and developing the photoresist by using a mask plate with a pattern carved thereon to form a photoresist mask, and etching the second copper electrode layer 202 and the second metal barrier layer 201 according to the photoresist mask pattern to form patterns of the data line 212, the data pad 213, the source electrode 210 and the drain electrode 211. It should be noted that, in this step, the formation of the photoresist mask is baked, including baking before development and baking after development, and then etching is performed after baking, and since the thickness of the copper electrode layer is smaller, the baked photoresist has higher hardness, a good etching effect of the thin copper product can be ensured, and good compatibility of the production line when switching between the thick copper product and the thin copper product is achieved. In addition, as will be understood by those skilled in the art, the present step may further include a step of removing or stripping the photoresist mask after the etching is completed.
In some embodiments, the thickness and/or material of the first metal barrier layer 121 is the same as the second metal barrier layer 201; of course, the thickness and material of both may be different, or only one of the thickness or material may be the same.
The embodiment also provides the array substrate prepared by the preparation method, as shown in fig. 4, which includes a substrate 110, and a gate conductor layer, a gate insulating layer 125, an active layer 206, an ohmic contact layer 205, a data line 212, a data pad 213, a source 210, and a drain 211 sequentially disposed on the substrate 110 from bottom to top, wherein the gate conductor layer includes a first metal barrier layer 121, a gate 123 formed by a first copper electrode layer 122, a gate line, and a gate pad 124, and the data line 212, the data pad 213, the source 210, and the drain 211 include a second metal barrier layer 201 and a second copper electrode layer 202.
Example 3
An embodiment of the present invention further provides a method for manufacturing an array substrate, as shown in fig. 5 and 6, which is different from the method for manufacturing an array substrate provided in embodiment 2 only in that: a third metal barrier layer 203 is disposed on the second copper electrode layer 202. The third metal barrier layer 203 is provided in the same step as the second metal barrier layer 201. In some embodiments, the thickness and/or material of the third metallic barrier layer 203 is the same as the second metallic barrier layer 201; of course, the thickness and material of both may be different, or only one of the thickness or material may be the same. Wherein the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000091
When the second metal barrier layer 201 is
Figure BDA0002768002070000092
Or the second copper electrode layer 202 has a thickness of
Figure BDA0002768002070000093
When the second metal barrier layer 201 is
Figure BDA0002768002070000094
In some embodiments, when the array substrate includes the third metal barrier layer 203, the second metal barrier layer 201, the second copper electrode layer 202 and the third metal barrier layer 203 are disposed, and then etching is performed.
The embodiment also provides the array substrate prepared by the preparation method, as shown in fig. 6, which includes a substrate 110, and a gate conductor layer, a gate insulating layer 125, an active layer 206, an ohmic contact layer 205, a data line 212, a data pad 213, a source 210, and a drain 211 sequentially disposed on the substrate 110 from bottom to top, wherein the gate conductor layer includes a first metal barrier layer 121, a gate 123 formed by a first copper electrode layer 122, a gate line, and a gate pad 124, and the data line 212, the data pad 213, the source 210, and the drain 211 include a second metal barrier layer 201, a second copper electrode layer 202, and a third metal barrier layer 203.
The preparation method of the array substrate provided by the application can further comprise the step of arranging structures such as the pixel electrode and the passivation layer.
The above detailed description is provided for the preparation method of the array substrate and the array substrate provided in the embodiments of the present application, and the principles and embodiments of the present application are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. The preparation method of the array substrate is characterized by comprising the following steps:
s1, providing a substrate;
s2, arranging a first metal barrier layer on the substrate;
s3, arranging a first copper electrode layer on the surface of the first metal barrier layer; and
s4, etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer;
the gate conductor layer comprises a gate, a gate line and a gate pad, and the first copper electrode layer has a thickness of
Figure FDA0002768002060000011
The first metal barrier layer is
Figure FDA0002768002060000012
Or the first copper electrode layer has a thickness of
Figure FDA0002768002060000013
The first metal barrier layer is
Figure FDA0002768002060000014
2. The method for manufacturing an array substrate of claim 1, wherein the first copper electrode layer has a thickness of
Figure FDA0002768002060000015
The first metal barrier layer is
Figure FDA0002768002060000016
Further, the step S4 includes:
s4a coating photoresist on the first copper electrode layer and developing; and
and S4b, wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.
3. The method for manufacturing an array substrate of claim 1, wherein the first copper electrode layer has a thickness of
Figure FDA0002768002060000017
The first metal barrier layer is
Figure FDA0002768002060000018
Further, the step S4 includes:
s4c coating photoresist on the first copper electrode layer, developing and baking; and
and S4d, wet etching the first copper electrode layer and the first metal barrier layer to form a gate conductor layer.
4. The method for preparing an array substrate of claim 1, wherein the method further comprises the following steps after the step S4:
s5 disposing a gate insulating layer on the gate conductor layer to cover the gate conductor layer;
s6, sequentially arranging an active layer and an ohmic contact layer on the gate insulating layer; and
s7, arranging a data line, a data pad, a source electrode and a drain electrode on the ohmic contact layer;
and at least one of the data line, the data bonding pad, the source electrode and the drain electrode comprises a second metal barrier layer and a second copper electrode layer which are stacked from bottom to top.
5. The method for preparing the array substrate according to claim 4, wherein a third metal barrier layer is further disposed on the second copper electrode layer.
6. The method for manufacturing the array substrate according to claim 1, wherein the material of the first metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.
7. The method for manufacturing the array substrate according to claim 4, wherein the material of the second metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.
8. The method for manufacturing the array substrate according to claim 5, wherein the material of the third metal barrier layer is selected from one or more of molybdenum, a binary alloy of molybdenum, or a ternary alloy of molybdenum.
9. The method of claim 4, wherein the active layer is made of amorphous silicon or an oxide semiconductor.
10. An array substrate produced by the production method according to any one of claims 1 to 9.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020119403A1 (en) * 2000-12-26 2002-08-29 Yoo Ji-Yong Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same
US20080062344A1 (en) * 2006-09-07 2008-03-13 Yoshikazu Yoshimoto Method for manufacturing liquid crystal display panel and liquid crystal display panel
CN103295970A (en) * 2013-06-05 2013-09-11 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device
CN104952932A (en) * 2015-05-29 2015-09-30 合肥鑫晟光电科技有限公司 Thin-film transistor, array substrate, manufacturing method of thin-film transistor, manufacturing method of array substrate, and display device
US20180097075A1 (en) * 2016-01-20 2018-04-05 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacturing method of array substrate and lcd panel
CN109524357A (en) * 2018-09-11 2019-03-26 惠科股份有限公司 Manufacturing method of array substrate and display panel
CN111326082A (en) * 2020-04-14 2020-06-23 Tcl华星光电技术有限公司 Backboard unit, manufacturing method thereof and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020119403A1 (en) * 2000-12-26 2002-08-29 Yoo Ji-Yong Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same
US20080062344A1 (en) * 2006-09-07 2008-03-13 Yoshikazu Yoshimoto Method for manufacturing liquid crystal display panel and liquid crystal display panel
CN103295970A (en) * 2013-06-05 2013-09-11 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device
CN104952932A (en) * 2015-05-29 2015-09-30 合肥鑫晟光电科技有限公司 Thin-film transistor, array substrate, manufacturing method of thin-film transistor, manufacturing method of array substrate, and display device
US20180097075A1 (en) * 2016-01-20 2018-04-05 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacturing method of array substrate and lcd panel
CN109524357A (en) * 2018-09-11 2019-03-26 惠科股份有限公司 Manufacturing method of array substrate and display panel
CN111326082A (en) * 2020-04-14 2020-06-23 Tcl华星光电技术有限公司 Backboard unit, manufacturing method thereof and display device

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