CN103700670B - Array base palte and preparation method thereof, display device - Google Patents

Abstract

The invention provides a kind of array base palte and preparation method thereof, display device, belong to Display Technique field.The manufacture method of this array base palte includes: before making conductive pattern, utilizes the mask plate making conductive pattern to be patterned the insulating barrier under described conductive pattern；Deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned forming described conductive pattern to described conductive layer.Pass through technical scheme, it is possible to ensure the periphery noresidue of conductive pattern after etching, reduce the etching residue impact on the performance of display device.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

During the production process of LCD (Liquid Crystal Display, Liquid Crystal Display) array substrate and OLED (Organic Light-Emitting Diode, Organic Light-Emitting Diode) array substrate, uneven etching of conductive patterns will affect the display performance of the array substrate, for example Array substrates often use indium tin oxide (ITO) to make pixel electrodes, but when depositing ITO, it is easy to form ITO crystals due to the temperature rise caused by long-term sputtering, and this phenomenon becomes more obvious as the thickness of the ITO film increases. The etching of crystalline ITO is relatively difficult, so when the ITO thin film is subsequently etched to form the pattern of the pixel electrode, ITO residues are likely to occur.

As shown in Figure 1, it is a relatively common array substrate structure. After the film layers 3 of the array substrate including the gate electrode, gate insulating layer, active layer, source and drain electrode layers, etc. are fabricated on the base substrate 4, passivation is performed. Fabrication of layer 2 and ITO layer 1. After ITO goes through the patterning process, the ideal situation is shown in Figure 2. The ITO film layer in the area 5 where the ITO film is removed between the adjacent area 7 where the ITO film is retained (that is, the adjacent ITO pattern area) should be completely covered. removed, exposing the underlying passivation layer. However, when etching the ITO layer to form the pixel electrode pattern, because the etching of crystalline ITO is relatively difficult, as shown in Figure 3, the etching is often incomplete, and the ITO film will remain in the region 7 to form the electrode. Area 5 will remove the ITO film to expose the passivation layer below, but because the etching difficulty of crystalline ITO is greater than that of normal ITO, there will still be ITO grains left in the peripheral area 6 of area 7. If there are too many ITO crystal grains left in the peripheral area 6 of area 7, the pixel electrodes of adjacent pixels will be electrically connected, which will seriously affect the electrical performance of the array substrate and increase the uncontrollability of the overall performance of the array substrate, which will eventually affect The display effect of the display device.

Contents of the invention

The technical problem to be solved by the present invention is to provide an array substrate and its manufacturing method, and a display device, which can ensure that there is no residue around the conductive pattern after etching, and reduce the impact of the etching residue on the performance of the display device.

In order to solve the above technical problems, embodiments of the present invention provide technical solutions as follows:

In one aspect, a method for manufacturing an array substrate is provided, including:

Before making the conductive pattern, the insulating layer under the conductive pattern is patterned by using a mask plate for making the conductive pattern;

A conductive layer is deposited, and the conductive layer is patterned to form the conductive pattern by using a mask plate for making a conductive pattern.

Further, patterning the insulating layer under the conductive pattern by using a mask plate for making a conductive pattern includes:

forming a first pattern of an insulating layer;

Coat photoresist on the base plate that is formed with the first pattern of described insulating layer, utilize the mask board that makes conductive pattern to expose to described photoresist, make photoresist form photoresist unreserved area and light Resist reserved area, wherein, the photoresist reserved area corresponds to the area where the conductive pattern is located, and the photoresist unreserved area corresponds to the area other than the described conductive pattern. Developing treatment is carried out, and the photolithography of the photoresist unreserved area The glue is completely removed, and the thickness of the photoresist in the photoresist-retained area remains unchanged;

Part of the insulating layer in the region where the photoresist is not retained is etched away by an etching process, and the remaining photoresist is peeled off to form a second pattern of the insulating layer corresponding to the conductive pattern, and the edge of the second pattern is There are slopes.

Further, the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions.

Further, the patterning of the conductive layer by using a mask for making conductive patterns to form the conductive patterns includes:

depositing a conductive layer on the insulating layer;

Coating a photoresist on the conductive layer, using a mask plate for making a conductive pattern to expose the photoresist, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, wherein the photoresist The resist reserved area corresponds to the area where the conductive pattern is located, and the photoresist unreserved area corresponds to the area outside the conductive pattern. After developing treatment, the photoresist in the photoresist unreserved area is completely removed, and the photoresist is completely removed. The photoresist thickness in the reserved area remains constant;

The conductive layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form the conductive pattern.

Further, the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a gate line or a pixel electrode.

An embodiment of the present invention also provides an array substrate manufactured by the above method, the insulating layer under at least one conductive pattern includes an insulating layer pattern corresponding to the conductive pattern, and the conductive pattern is connected to the insulating layer pattern edge alignment.

Further, the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions

Further, there is a slope at the edge of the insulating layer pattern corresponding to the conductive pattern.

Further, the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a gate line or a pixel electrode.

An embodiment of the present invention also provides a display device, including the above-mentioned array substrate.

Embodiments of the present invention have the following beneficial effects:

In the above solution, before making the conductive pattern, the insulating layer under the conductive pattern is patterned by using a mask plate for making the conductive pattern, so that the insulating layer under the conductive pattern has an insulating layer pattern corresponding to the conductive pattern. When depositing the conductive film layer on the insulating layer afterwards, because there is a slope at the edge of the insulating layer pattern, the conductive film layer at the slope is very thin, which makes the process of etching the conductive pattern easier, even if the conductive film layer below the slope has The residue will also be blocked by the non-residual slope, which has a good isolation effect. A non-residual isolation zone is formed around the conductive pattern, which separates the conductive pattern from the part of the etching residue, so that the etching effect is reflected. The influence of etching residue on the performance of the display device is reduced.

Description of drawings

FIG. 1 is a schematic cross-sectional view of an existing array substrate;

Figure 2 is a schematic top view of ITO etching without residue;

Fig. 3 is a schematic top view when ITO etching remains;

4 is a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;

5 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention after depositing a transparent conductive layer;

Fig. 6 is a schematic top view of an edge portion of an ITO according to an embodiment of the present invention.

reference sign

1 transparent conductive layer 2 passivation layer

3 Each film layer including gate electrode, gate insulating layer, active layer, source-drain electrode layer, etc.

4 Substrate substrate 5 Area where ITO thin film is removed

6 Peripheral area of area 7 7 Area where ITO thin film remains

8 Isolation zone 9 Etching residual part 10 Pixel electrode

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

Embodiments of the present invention aim at the problem in the prior art that the etching residue around the conductive pattern will affect the performance of the display device, and provide an array substrate, a manufacturing method thereof, and a display device, which can ensure the integrity of the conductive pattern after etching. There is no residue at the periphery, which reduces the impact of etching residue on the performance of the display device.

An embodiment of the present invention provides a method for manufacturing an array substrate, as shown in FIG. 4 , this embodiment includes:

Step 101: Before making the conductive pattern, use the mask plate for making the conductive pattern to pattern the insulating layer under the conductive pattern;

Step 102: depositing a conductive layer, and patterning the conductive layer using a mask plate for forming a conductive pattern to form the conductive pattern.

In the manufacturing method of the array substrate of the present invention, before making the conductive pattern, the insulating layer under the conductive pattern is patterned by using the mask plate for making the conductive pattern, so that the insulating layer under the conductive pattern has an insulating layer corresponding to the conductive pattern graphics. When depositing the conductive film layer on the insulating layer afterwards, because there is a slope at the edge of the insulating layer pattern, the conductive film layer at the slope is very thin, which makes the process of etching the conductive pattern easier, even if the conductive film layer below the slope has The residue will also be blocked by the non-residual slope, which has a good isolation effect. A non-residual isolation zone is formed around the conductive pattern, which separates the conductive pattern from the part of the etching residue, so that the etching effect is reflected. The influence of etching residue on the performance of the display device is reduced.

Further, patterning the insulating layer under the conductive pattern by using a mask plate for making a conductive pattern includes:

forming a first pattern of an insulating layer;

Coat photoresist on the base plate that is formed with the first pattern of described insulating layer, utilize the mask board that makes conductive pattern to expose to described photoresist, make photoresist form photoresist unreserved area and light Resist reserved area, wherein, the photoresist reserved area corresponds to the area where the conductive pattern is located, and the photoresist unreserved area corresponds to the area other than the described conductive pattern. Developing treatment is carried out, and the photolithography of the photoresist unreserved area The glue is completely removed, and the thickness of the photoresist in the photoresist-retained area remains unchanged;

Part of the insulating layer in the region where the photoresist is not retained is etched away by an etching process, and the remaining photoresist is peeled off to form a second pattern of the insulating layer corresponding to the conductive pattern, and the edge of the second pattern is There are slopes.

Further, the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions.

Further, the patterning of the conductive layer by using a mask for making conductive patterns to form the conductive patterns includes:

depositing a conductive layer on the insulating layer;

Coating a photoresist on the conductive layer, using a mask plate for making a conductive pattern to expose the photoresist, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, wherein the photoresist The resist reserved area corresponds to the area where the conductive pattern is located, and the photoresist unreserved area corresponds to the area outside the conductive pattern. After developing treatment, the photoresist in the photoresist unreserved area is completely removed, and the photoresist is completely removed. The photoresist thickness in the reserved area remains constant;

The conductive layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form the conductive pattern.

Further, the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a gate line or a pixel electrode.

Specifically, the conductive pattern may be a source electrode, a drain electrode, and a data line, and the array substrate includes an insulating layer located under the source electrode, the drain electrode, and the data line, and the insulating layer may be an etching stopper layer, Before making the conductive pattern, patterning the insulating layer under the conductive pattern using a mask plate for making the conductive pattern includes:

Before making the pattern of source electrode, drain electrode and data line, utilize the mask plate of making source electrode, drain electrode and data line to carry out patterning to the etch stop layer under described source electrode, drain electrode and data line, engrave Etching away part of the etch stop layer, so that the etch stop layer includes patterns corresponding to source electrodes, drain electrodes and data lines;

The patterning of the conductive layer by using a mask plate for making conductive patterns to form the conductive patterns includes:

Depositing source electrodes, drain electrodes, and data line metal layers on the etching barrier layer;

Coat photoresist on described source electrode, drain electrode, data line metal layer, utilize the mask board that makes source electrode, drain electrode and data line to expose to described photoresist, make photoresist form photoresist Glue unreserved area and photoresist reserved area, wherein, the photoresist reserved area corresponds to the area where the source electrode, the drain electrode and the data line are located, and the photoresist unreserved area corresponds to the area other than the source electrode, the drain electrode data line, Carry out developing treatment, the photoresist in the photoresist unreserved area is completely removed, and the photoresist thickness in the photoresist reserved area remains unchanged;

The source electrode, the drain electrode, and the metal layer of the data line in the region where the photoresist is not retained are completely etched away by an etching process, and the remaining photoresist is stripped to form patterns of the source electrode, the drain electrode, and the data line.

Further, the array substrate includes an insulating layer under the gate electrode and the gate line, the conductive pattern may be the pattern of the gate electrode and the gate line, and the insulating layer under the conductive pattern may be the gate electrode and the gate line. The buffer layer under the line. Before making the conductive pattern, patterning the insulating layer under the conductive pattern by using a mask plate for making the conductive pattern includes:

Before making the pattern of the gate electrode and the grid line, the buffer layer under the grid electrode and the grid line is patterned by using the mask plate for making the gate electrode and the grid line, and part of the buffer layer is etched away, so that the buffer layer includes Graphics corresponding to gate electrodes and gate lines;

The patterning of the conductive layer by using a mask plate for making conductive patterns to form the conductive patterns includes:

depositing a gate metal layer on the buffer layer;

Coating a photoresist on the gate metal layer, and exposing the photoresist by using a mask plate for making gate electrodes and grid lines, so that the photoresist forms a photoresist unretained area and a photoresist reserved area , wherein the photoresist reserved area corresponds to the area where the gate electrode and the grid line are located, and the photoresist unreserved area corresponds to the area other than the gate electrode and the grid line, and the photoresist in the photoresist unreserved area is processed by development. Completely removed, the photoresist thickness in the photoresist-retained area remains unchanged;

The gate metal layer in the area not retained by the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form patterns of the gate electrode and the gate line.

Further, the array substrate includes a passivation layer under the pixel electrode, the conductive pattern may be a pattern of the pixel electrode, and the insulating layer under the conductive pattern may be the passivation layer under the pixel electrode, Before making the conductive pattern, patterning the insulating layer under the conductive pattern using a mask plate for making the conductive pattern includes:

Before making the pattern of the pixel electrode, the passivation layer under the pixel electrode is patterned by using the mask plate for making the pixel electrode, and part of the passivation layer is etched away, so that the passivation layer includes the pattern of the corresponding pixel electrode;

The patterning of the conductive layer by using a mask plate for making conductive patterns to form the conductive patterns includes:

depositing a pixel electrode layer on the passivation layer;

Coating a photoresist on the pixel electrode layer, exposing the photoresist by using a mask plate for making the pixel electrode, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, wherein, The photoresist reserved area corresponds to the area where the pixel electrode is located, and the photoresist unreserved area corresponds to the area other than the pixel electrode. After developing treatment, the photoresist in the photoresist unreserved area is completely removed, and the photoresist reserved area is completely removed. The photoresist thickness remains constant;

The pixel electrode layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the pixel electrode.

In the above solution, before making the conductive pattern, the insulating layer under the conductive pattern is patterned by using a mask plate for making the conductive pattern, so that the insulating layer under the conductive pattern has an insulating layer pattern corresponding to the conductive pattern. When depositing the conductive film layer on the insulating layer afterwards, because there is a slope at the edge of the insulating layer pattern, the conductive film layer at the slope is very thin, which makes the process of etching the conductive pattern easier, even if the conductive film layer below the slope has The residue will also be blocked by the non-residual slope, which has a good isolation effect. A non-residual isolation zone is formed around the conductive pattern, which separates the conductive pattern from the part of the etching residue, so that the etching effect is reflected. The influence of etching residue on the performance of the display device is reduced.

Taking the conductive pattern as the pixel electrode and the insulating layer under the conductive pattern as the passivation layer as an example, the array substrate of the present invention and its manufacturing method are described in detail below:

In the existing manufacturing method of the array substrate, the conventional pixel electrode is often made of indium tin oxide (ITO) material. When using ITO to form the pixel electrode, the ITO film layer is first formed on the substrate through the sputtering (sputtering) film forming process. In this process, it is easy to form ITO crystals due to the temperature rise caused by long-term sputtering. For thicker ITO film layers, this kind of residue is more common, because the etching difficulty of crystalline ITO is greater than that of normal ITO. , as shown in Figure 3, after etching to form the pattern of the pixel electrode, in the peripheral area 6 of the area 7 where the ITO film layer remains, there will still be ITO crystal grains, resulting in the presence of conductive particles between adjacent areas 7, It will seriously affect the overall performance of the display device.

In order to solve the above-mentioned problems, before the technical solution of the present invention deposits the ITO film layer, at first utilize the mask plate that forms pixel electrode to carry out a relatively shallow etching to the passivation layer under the ITO film layer, in the pixel electrode that should form A slope is formed at the edge of the passivation layer, so when the ITO film is deposited on the passivation layer, because there is a slope at the edge of the passivation layer pattern, the ITO film at the slope is thinner than the film at other flat places, so that the etching of the ITO film The process becomes easier. Even if the ITO film layer under the slope has residue, it will be blocked by the slope without residue, which has a good isolation effect and forms a non-residue isolation zone around the pixel electrode, separating the pixel electrode. The part with the etching residue enables the etching effect to be reflected, reducing the impact of the etching residue on the performance of the display device.

Specifically, the manufacturing method of the array substrate of this embodiment may include the following steps:

Step a: providing a base substrate 4, which is a transparent substrate, specifically, a glass substrate or a quartz substrate;

Step b: forming gate electrodes and gate lines on the base substrate 4;

Specifically, sputtering or thermal evaporation can be used to deposit a layer with a thickness of The gate metal layer, the gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the gate metal layer can be single-layer structure or multi-layer Structure, multi-layer structure such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the gate metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the grid line and the gate electrode is located, the unreserved area of the photoresist corresponds to the area outside the above-mentioned figure; the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist in the unreserved area of the photoresist is completely removed. The thickness of the resist remains unchanged; the gate metal film in the area where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form the pattern of the gate line and the gate electrode.

Step c: forming a gate insulating layer on the base substrate after step b;

Specifically, a plasma-enhanced chemical vapor deposition method can be used to deposit a thickness of about The gate insulating layer, wherein the material of the gate insulating layer can be selected from oxide, nitride or oxynitride, and the gate insulating layer can be a single-layer, double-layer or multi-layer structure. Specifically, the gate insulating layer may be SiNx, SiOx or Si(ON)x.

Step d: forming an active layer on the gate insulating layer;

Specifically, a layer with a thickness of about The transparent metal oxide semiconductor layer, the transparent metal oxide semiconductor layer can be selected from amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO2, SnO, CdSnO or other metal oxide semiconductor materials. Coating photoresist on the transparent metal oxide semiconductor layer, exposing and developing, etching the transparent metal oxide semiconductor layer, and peeling off the photoresist to form the pattern of the active layer composed of the transparent metal oxide semiconductor layer.

Step e: forming an etching stopper layer on the base substrate after step d;

Specifically, an etching barrier layer can be deposited on the substrate that has passed step d by using a plasma-enhanced chemical vapor deposition method, and a photoresist can be coated on the etching barrier layer, exposed, developed, etched and etched, and peeled off. Photoresist, which forms the pattern of the etch barrier layer. Wherein, the etching barrier layer can be exposed, developed, and etched using the same mask as the active layer. The material of the etching barrier layer can be selected from oxide, nitride or oxynitride, and the etching barrier layer can be a single-layer, double-layer or multi-layer structure. Specifically, the etch stop layer may be SiNx, SiOx or Si(ON)x.

Step f: forming source electrodes, drain electrodes, data lines and data lines on the etch barrier layer;

Specifically, a layer with a thickness of about The source and drain metal layers can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The source-drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. Coat a layer of photoresist on the source-drain metal layer, and use a mask to expose the photoresist, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, wherein the photoresist reserved area Corresponding to the area where the pattern of the source electrode, the drain electrode, the data line and the data line is located, the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the photoresist in the unreserved area of the photoresist is completely removed, The photoresist thickness in the photoresist reserved area remains unchanged; the source and drain metal films in the photoresist unreserved area are completely etched away by etching process, and the remaining photoresist is stripped to form data lines, source electrodes and drain electrodes graphics.

Step g: forming a passivation layer 2 on the base substrate after step f;

Specifically, magnetron sputtering, thermal evaporation, PECVD or other film-forming methods are used to deposit a thickness of The material of the passivation layer, wherein the material of the passivation layer can be selected from oxide, nitride or oxynitride, specifically, the passivation layer can be SiNx, SiOx or Si(ON)x. The passivation layer can be a single-layer structure, or a two-layer structure composed of silicon nitride and silicon oxide.

Apply a layer of photoresist on the passivation layer material; use a mask to expose the photoresist, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, wherein the photoresist is not reserved The area corresponds to the area where the via hole of the passivation layer is located, and the photoresist reserved area corresponds to the area outside the via hole; the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist in the photoresist reserved area is completely removed. The thickness of the resist remains unchanged; the material of the passivation layer in the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is peeled off to form a pattern of the passivation layer 2 including the via hole, wherein the sub-etch The etching time of the etching process is the first preset time.

Step h: Etching the passivation layer for the second time by using the mask plate for making the pixel electrode;

Coating a layer of photoresist on the passivation layer through step g; using a mask plate for making a pixel electrode to expose the photoresist, so that the photoresist forms a photoresist unretained area and a photoresist reserved area, Wherein, the photoresist reserved area corresponds to the area where the pattern of the pixel electrode is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned pattern; after developing, the photoresist in the photoresist unreserved area is completely removed. The thickness of the photoresist in the glue-retained area remains unchanged; part of the passivation layer material in the unreserved area of the photoresist is etched away by an etching process, and the remaining photoresist is peeled off to form a passivation layer pattern corresponding to the pixel electrode pattern. The etching time of this etching process is the second preset time, and the second preset time is shorter than the first preset time, so the passivation layer will not be completely etched through. The passivation layer includes a passivation layer pattern corresponding to the pixel electrode, the thickness of the passivation layer under the pixel electrode is greater than that of other regions, and there is a slope at the edge of the passivation layer pattern corresponding to the pixel electrode.

Step i: forming a pixel electrode 10 on the base substrate 4 after step h.

Specifically, magnetron sputtering, thermal evaporation or other film-forming methods are used to deposit a thickness of The ITO film layer can form the structure shown in Figure 5. Coat a layer of photoresist on the ITO film layer; use the pixel electrode mask to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist remains The region corresponds to the region where the pattern of the pixel electrode is located, and the unreserved region of the photoresist corresponds to the region other than the above-mentioned pattern; the development process is carried out, the photoresist in the region where the photoresist is not retained is completely removed, and the photoresist in the region where the photoresist remains The thickness of the glue remains unchanged; the transparent conductive layer in the unreserved area of the photoresist is completely etched away by the etching process, and the remaining photoresist is peeled off to form the pattern of the pixel electrode. The pixel electrode passes through the via hole of the passivation layer and the drain electrode electrical connection.

As shown in Figure 5, when depositing the ITO layer, the thickness of the part of the ITO layer facing the target is a, and at the slope of the passivation layer, the thickness of the part of the ITO layer facing the target is b, and b is larger than a There is a noticeable decrease. After the development process, the photoresist covers the part above the slope, that is, the area where the ITO layer needs to be retained. In the process of etching to form the pixel electrode, etching is performed using an etching solution for the a-thick ITO layer, which is different from dry etching. , in the etchant, the etching degree in all directions is consistent, so the etching effect at the slope is obviously better than that of the ITO layer facing the target, and the ITO layer at the slope can be completely Removed, no ITO or ITO crystal remains, finally as shown in FIG. It is reflected that the influence of etching residue on the performance of the display device is reduced. Certainly, the pixel electrode is not limited to the ITO material, and materials such as indium zinc oxide (IZO) can also be used to form the pixel electrode by the above-mentioned manufacturing method of the array substrate.

The above-mentioned embodiment takes the etching of the ITO layer as an example to illustrate the manufacturing method of the array substrate of the present invention. In fact, not only the ITO layer, but also various metal layers or metal oxide layers that are difficult to etch can be processed by this method: Before the metal layer or metal oxide layer, use the mask plate for making the metal layer or metal oxide layer to pre-etch the insulating layer under the metal layer or metal oxide layer, so that the insulating layer has the same pattern as the metal layer pattern or metal layer. The corresponding figure of the oxide layer pattern has a slope on the edge of the metal layer pattern or metal oxide layer pattern that should be formed, so that when the metal layer or metal oxide layer is deposited subsequently, a thinner metal layer or metal oxide layer can be formed on the slope. Oxide layer, after finally etching to form a metal layer pattern or a metal oxide layer pattern, form a non-residual isolation zone around the metal layer pattern or metal oxide layer pattern, separate the metal layer pattern or metal oxide layer pattern from etching The residual portion reduces the impact of etching residue on the performance of the display device.

An embodiment of the present invention also provides an array substrate with the above manufacturing method, the insulating layer under at least one conductive pattern of the array substrate includes an insulating layer pattern corresponding to the conductive pattern, the conductive pattern and the conductive pattern Align the edges of the insulating layer pattern.

Further, the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions.

Further, there is a slope at the edge of the insulating layer pattern corresponding to the conductive pattern. The conductive patterns may be source electrodes, drain electrodes, data lines, gate electrodes, gate lines or pixel electrodes.

In the array substrate of the present invention, the insulating layer under the conductive pattern has an insulating layer pattern corresponding to the conductive pattern. In this way, when a conductive film layer is deposited on the insulating layer of the array substrate to make a conductive pattern, since there is a slope on the edge of the insulating layer pattern, the conductive film layer at the slope is very thin, which makes the process of etching the conductive pattern easier. Even if the conductive film layer under the slope remains, it will be blocked by the slope without residue, which has a good isolation effect. A non-residual isolation zone is formed around the conductive pattern, which separates the conductive pattern from the part of the etching residue. The effect of etching is realized, and the influence of etching residue on the performance of the display device is reduced.

Further, the array substrate includes an insulating layer located under the source electrode, the drain electrode and the data line, the insulating layer may be an etching stopper layer, a buffer layer or a passivation layer, and under the conductive pattern When the insulating layer is an etch barrier layer, the etch barrier layer under the source electrode, drain electrode and data line of the array substrate has an etch barrier corresponding to the source electrode, drain electrode, data line and data line Layer patterns, source electrodes, drain electrodes, data lines are aligned with the edges of the etch barrier layer.

Further, the array substrate includes an insulating layer under the gate electrode and the gate line, the conductive pattern may be the pattern of the gate electrode and the gate line, and the insulating layer under the conductive pattern may be the gate electrode and the gate line. The buffer layer under the line, the gate electrode and the buffer layer under the gate line of the array substrate have a buffer layer pattern corresponding to the gate electrode and the gate line, and the gate electrode and the gate line are aligned with the edge of the buffer layer pattern.

Further, the array substrate includes an insulating layer under the pixel electrode, the conductive pattern may be a pattern of the pixel electrode, and the insulating layer under the conductive pattern may be a passivation layer under the pixel electrode, so The passivation layer under the pixel electrode of the array substrate has a passivation layer pattern corresponding to the pixel electrode, and the pixel electrode is aligned with the edge of the passivation layer.

An embodiment of the present invention also provides a display device, including the above-mentioned array substrate. Wherein, the structure and working principle of the array substrate are the same as those of the above-mentioned embodiments, and will not be repeated here. In addition, the structure of other parts of the display device can refer to the prior art, which will not be described in detail herein. The display device may be a product or component with any display function, such as a liquid crystal panel, an electronic paper, an OLED (Organic Light Emitting Diode, organic light emitting diode) panel, a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone, and a tablet computer.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (10)

1. the manufacture method of an array base palte, it is characterised in that including:

Before making conductive pattern, utilize the mask plate making conductive pattern that the insulating barrier under described conductive pattern is carried out Composition；

Deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned forming described conductive pattern to described conductive layer.

The manufacture method of array base palte the most according to claim 1, it is characterised in that described utilization makes conductive pattern Insulating barrier under described conductive pattern is patterned including by mask plate:

Form the first figure of insulating barrier；

The substrate of the first figure being formed with described insulating barrier coats photoresist, utilizes the mask plate pair making conductive pattern Described photoresist is exposed, and makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist is protected Staying region to correspond to described conductive pattern region, photoresist does not retains region corresponding to the district beyond described conductive pattern Territory, carries out development treatment, and photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region Keep constant；

Etch away photoresist by etching technics and do not retain the partial insulative layer in region, peel off remaining photoresist, formed described The second graph corresponding with described conductive pattern of insulating barrier, the edge of described second graph there are slope.

The manufacture method of array base palte the most according to claim 2, it is characterised in that the insulating barrier under described conductive pattern Thickness is more than the thickness of insulating layer at other regions.

4. according to the manufacture method of the array base palte according to any one of claim 1-3, it is characterised in that described utilization makes The mask plate of conductive pattern is patterned forming described conductive pattern and includes described conductive layer:

Described insulating barrier deposits conductive layer；

Described conductive layer coats photoresist, utilizes the mask plate making conductive pattern that described photoresist is exposed, make Photoresist forms photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region corresponding to described conduction Figure region, photoresist does not retains region and corresponds to the region beyond described conductive pattern, carries out development treatment, photoresist The photoresist not retaining region is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；

Etched away photoresist by etching technics completely and do not retain the conductive layer in region, peel off remaining photoresist, formed described Conductive pattern.

The manufacture method of array base palte the most according to claim 4, it is characterised in that described conductive pattern be source electrode, Drain electrode, data wire, gate electrode, grid line or pixel electrode.

6. the array base palte made with method according to any one of claim 1-5, it is characterised in that at least one conductive pattern Insulating barrier under shape includes the layer pattern corresponding with described conductive pattern, described conductive pattern and described insulating barrier figure The justified margin of shape.

Array base palte the most according to claim 6, it is characterised in that the thickness of insulating layer under described conductive pattern is more than it Thickness of insulating layer at his region.

Array base palte the most according to claim 6, it is characterised in that the layer pattern corresponding with described conductive pattern Marginal existence has slope.

Array base palte the most according to claim 6, it is characterised in that described conductive pattern is source electrode, drain electrode, data Line, gate electrode, grid line or pixel electrode.

10. a display device, it is characterised in that include the array base palte as according to any one of claim 6-9.