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CN112310061A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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Publication number
CN112310061A
CN112310061A CN202010768717.6A CN202010768717A CN112310061A CN 112310061 A CN112310061 A CN 112310061A CN 202010768717 A CN202010768717 A CN 202010768717A CN 112310061 A CN112310061 A CN 112310061A
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China
Prior art keywords
semiconductor package
semiconductor
insulating substrate
semiconductor die
redistribution layer
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Pending
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CN202010768717.6A
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English (en)
Inventor
齐彦尧
刘乃玮
林子闳
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MediaTek Inc
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MediaTek Inc
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Publication of CN112310061A publication Critical patent/CN112310061A/zh
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    • H01L25/162—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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Abstract

本发明公开一种半导体封装结构，包括：天线装置，包括：导电图案层，包括第一天线元件，形成在绝缘基板中并且邻近于该绝缘基板的第一表面；第二天线元件，形成在该绝缘基板的与该第一表面相对的第二表面上；以及半导体封装，包括：重分布层结构，接合并电连接到该导电图案层；第一半导体晶粒，电连接到该重分布层结构；密封层，形成在该重分布层结构上并围绕该第一半导体晶粒。这样将半导体封装设置在绝缘基板外，从而可以减小带有天线的绝缘基板的厚度，并且可以减小半导体封装结构的尺寸以及晶粒到天线的损耗。

Description

半导体封装结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体封装结构。
背景技术
为了确保电子产品和通信装置的持续小型化和多功能性，半导体封装必须尺寸小、支持多针(multi-pin)连接、高速操作(operate)并且具有高功能性。此外，在诸如射频(radio frequency，RF)封装系统(system-in-package，SiP)组件之类的高频应用中，天线通常用于启用无线通信。
当构造具有天线的无线通信封装时，封装设计需要提供良好的天线特性(例如高效率、宽带宽(bandwidth)等)，同时提供可靠且低成本的封装解决方案。在常规的半导体封装结构中，基于基板的天线与芯片接合。由于基于基板的天线较厚，因此难以减小封装尺寸，并且由于较长的走线长度而导致芯片间天线损耗较高。而且，基于基板的天线由于接合在其上的芯片的散热路径较长而提供了较差的热性能。
发明内容
有鉴于此，本发明提供一种半导体封装结构，以解决上述问题。
根据本发明的第一方面，公开一种半导体封装结构，包括：
天线装置，包括：导电图案层，包括第一天线元件，形成在绝缘基板中并且邻近于该绝缘基板的第一表面；第二天线元件，形成在该绝缘基板的与该第一表面相对的第二表面上；以及
半导体封装，包括：重分布层结构，接合并电连接到该导电图案层；第一半导体晶粒，电连接到该重分布层结构；密封层，形成在该重分布层结构上并围绕该第一半导体晶粒。
根据本发明的第二方面，公开一种半导体封装结构，包括：
重分布层结构，具有第一表面和与该第一表面相对的第二表面；
第一半导体晶粒，具有形成在该重分布层结构的该第一表面上的有源表面；
第一电连接器，形成在该重分布层结构的该第二表面上；
绝缘基板，具有第一表面，堆栈在重分布层结构的第二表面上；
导电图案层，包括第一天线元件，形成在该绝缘基板中并与绝缘基板的该第一表面相邻；
第二天线元件，形成在该绝缘基板的与该绝缘基板的该第一表面相对的第二表面上；以及
第二电连接器，形成在该绝缘基板的该第一表面上并且电连接到该第一天线元件，其中，该第二电连接器的尺寸大于该第一电连接器的尺寸。
本发明的半导体封装结构由于包括天线装置，包括：导电图案层，包括第一天线元件，形成在绝缘基板中并且邻近于该绝缘基板的第一表面；第二天线元件，形成在该绝缘基板的与该第一表面相对的第二表面上；以及半导体封装，包括：重分布层结构，接合并电连接到该导电图案层；第一半导体晶粒，电连接到该重分布层结构；密封层，形成在该重分布层结构上并围绕该第一半导体晶粒。这样将半导体封装设置在绝缘基板外，从而可以减小带有天线的绝缘基板的厚度，并且可以减小半导体封装结构的尺寸以及晶粒到天线的损耗。
附图说明
图1是根据一些实施例的示例性半导体封装结构的截面图。
图2是根据一些实施例的示例性半导体封装结构的截面图。
图3是根据一些实施例的示例性半导体封装结构的截面图。
图4是根据一些实施例的示例性半导体封装结构的截面图。
具体实施方式
以下描述是实施本发明的最佳构想模式。进行该描述是为了说明本发明的一般原理，而不应被认为是限制性的。本发明的范围由所附权利要求书确定。
将针对特定实施例并参考某些附图来描述本发明，但是本发明不限于此，而是仅由权利要求书来限制。所描述的附图仅是示意性的而非限制性的。在附图中，为了说明的目的，一些元件的尺寸可能被放大并且未按比例绘制。在本发明的实施中，尺寸和相对尺寸不对应于实际尺寸。
图1是根据一些实施例的示例性半导体封装结构10的截面图。在一些实施例中，半导体封装结构10是晶圆级(wafer-level)半导体封装结构，并且是倒装芯片(flip-chip)半导体封装结构。半导体封装结构10可以安装在基座(base)(未示出)上。例如，半导体封装结构10可以是系统单芯片(system-on-chip，SOC)封装结构。而且，基座可以包括印刷电路板(printed circuit board，PCB)并且可以由聚丙烯(polypropylene，PP)形成。
替代地，基座是封装基板。半导体封装结构10通过接合制程安装到基座上。例如，半导体封装结构10包括电连接器150，该电连接器150通过接合制程安装在基座上并电耦接至基座。如图1所示，在一些实施例中，每个电连接器150包括导电凸块结构，例如铜凸块或焊球。可替换地，每个电连接器150包括导电柱结构、导线结构、或导电膏(paste)结构。
在一些实施例中，如图1所示，半导体封装结构10还包括半导体封装110a、电连接器140和经由电连接器140堆栈并安装在下面的半导体封装110a上的天线装置130。在一些实施例中，每个电连接器140包括导电凸块结构，例如铜凸块或焊球。可选地，每个电连接器140包括导电柱结构、导线结构或导电膏结构。在一些实施例中，电连接器140和电连接器150是焊球，并且电连接器140的尺寸(例如高度或体积等)不同于(例如小于)电连接器150的尺寸。例如，电连接器140的高度H1低于电连接器150的高度H2，如图1所示。
在一些实施例中，半导体封装110a包括半导体晶粒100。例如，半导体晶粒100是系统单芯片(system-on-chip，SOC)晶粒，其可以包括微控制器(microcontroller，MCU)、微处理器(microprocessor，MPU)、电源管理集成电路(power management integratedcircuit，PMIC)、全球定位系统(global positioning system，GPS)装置或射频(radiofrequency，RF)装置或这些任意组合。
半导体晶粒100具有两个相对的侧面。更具体地，半导体晶粒100具有有源表面(active surface)100a和与有源表面100a相对的非有源表面100b(non-active surface)。非有源表面100b也可以称为后表面(rear surface)，并且有源表面100a也可以称为与后表面相对的前表面(front surface)。在一些实施例中，半导体晶粒100包括焊盘101，其布置在有源表面100a上并且电连接到半导体晶粒100的一个或多个功能电路(未示出)。在一些实施例中，半导体晶粒100的焊盘101属于半导体晶粒100的互连结构(未示出)的最上层金属层。
在一些实施例中，半导体封装结构10的半导体封装110a包括具有第一表面102a和与第一表面102a相对的第二表面102b的重分布层(redistribution layer，RDL)结构102。RDL结构102，也称为扇出(fan-out)RDL结构。在一些实施例中，RDL结构102设置在半导体晶粒100的有源表面100a上，并通过半导体晶粒100的焊盘101电连接到半导体晶粒100。
在一些实施例中，RDL结构102包括设置在金属间介电(inter-metal dielectric，IMD)层中的一个或多个导电迹线。例如，第一导电迹线设置在与RDL结构102的第一表面102a相邻的IMD层的第一层级。第一导电迹线中的至少一个电耦接至半导体晶粒100。导电迹线设置在高于IMD层的第一层级的第二层级处并且与RDL结构102的第二表面102b相邻。此外，第二导电迹线中的至少一个接合并且电耦接至一个或多个电连接器140，使得电连接器140通过RDL结构102电耦接到半导体晶粒100。
IMD层可以包括从半导体晶粒100的有源表面100a连续地堆栈的第一子介电层和第二子介电层，从而在第一子介电层中形成第一导电迹线，并且第二导电迹线形成在第二子介电层中。在一些实施例中，IMD层由有机材料(该有机材料包括聚合物基础材料)、非有机材料(该非有机材料包括氮化硅(SiNX)、氧化硅(SiOX)、石墨烯等)形成。例如，第一子介电层和第二子介电层可以由聚合物基础材料制成。在一些其他实施例中，IMD层由高k(k是介电层的介电常数)介电层制成。
应当注意，图1所示的RDL结构102的导电迹线的数量和子介电层的数量仅是示例，并不限于实施例中公开的内容。
在一些实施例中，半导体封装结构10的半导体封装110a还包括形成在RDL结构102的第一表面102a上的封装层104。封装层104围绕半导体晶粒100并覆盖非有源表面。封装层104具有与RDL结构102的侧壁(或边缘)基本对准(或与之对齐)的侧壁(或边缘)。
此外，封装层104和半导体晶粒100通过RDL结构102与电连接器140分开。换句话说，电连接器140不与封装层104和半导体晶粒100接触。
封装层104可以由模塑料材料制成，例如环氧树脂、树脂、可模制聚合物等。可以在基本上为液体的同时施加模塑料材料，然后可以通过化学反应例如在环氧树脂或树脂中使其固化。例如，模塑料材料可以是紫外线(ultraviolet，UV)或热固化的聚合物，其被施加为能够设置在半导体晶粒100周围的凝胶或可延展的固体，然后通过UV或热固化制程来固化。模塑料可以用模具(未示出)固化。
在一些实施例中，天线装置130包括绝缘基板120。绝缘基板120具有第一表面120a和与第一表面120a相对的第二表面120b。在一些实施例中，绝缘基板120的第一表面120a经由电连接器140粘附至第二表面RDL结构102。
绝缘基板120可以是单层或多层结构，并且包括芯(core)绝缘材料中的任何一种，例如，玻璃环氧树脂、双马来酰亚胺-三嗪(bismaleimide-triazine，BT)或ABF(AjinomotoBuild up Film，味之素复合薄膜)。在一些实施例中，绝缘基板120包括从绝缘基板120的第一表面120a连续堆栈的第一子介电层115a、第二子介电层115b和第三子介电层115c。
在一些实施例中，天线装置130包括导电图案层116，该导电图案层116包括第一天线元件116a和一个或多个导电迹线116b，该导电图案层116形成在绝缘基板120的第一子介电层115a中。第一天线元件116a导电迹线116b接合并且电连接到一个或多个电连接器150，并且导电迹线116b接合并且电连接到电连接器140和150。
在那些情况下，电连接器140接合在RDL结构102和导电图案层116之间，使得导电图案层116与RDL结构102通过间隙141分开。此外，电连接器150是电连接到导电图案层116的第一天线元件116a并围绕半导体封装110a。
在一些实施例中，天线装置130进一步包括形成在绝缘基板120的第二表面120b(即，第三子介电层115c的上表面)上的第二天线元件118和一个或多个贯穿通孔结构119(或通孔结构119)，贯穿通孔结构119在第一子介电层115a、第二子介电层115b和第三子介电层115c中形成的。贯穿通孔结构119可以称为贯穿绝缘体通孔(through insulator via，TIV)，并且电连接在第一天线元件116a和第二天线元件118之间，以便在天线装置130中形成天线。导电图案层116、第二天线元件118和通孔结构119由金属材料制成，例如铜或其他合适的天线材料。
应当注意，图1所示的绝缘基板的导电图案层的数量和子介电层的数量仅是示例，并且不限于实施例中公开的内容。
图2是根据本发明的一些实施例的示例性半导体封装结构20的截面图。为简洁起见，以下实施例中与先前参考图1描述的元件相同或相似的元件的描述可以省略。在该实施例中，半导体封装结构20类似于图1所示的半导体封装结构10。如图2所示，与半导体封装结构10的半导体封装110a不同，半导体封装结构20的半导体封装110b包括多个半导体晶粒。在一些实施例中，半导体封装110b包括电连接到RDL结构102并由封装层104围绕的半导体晶粒200和300。更具体地，类似于图1所示的半导体晶粒100，半导体晶粒200具有有源表面200a和与有源表面200a相对的非有源表面200b。半导体晶粒300具有有源表面300a和与有源表面300a相对的非有源表面300b。此外，RDL结构102设置并接合到半导体晶粒200的有源表面200a和半导体晶粒300的有源表面300a上，从而半导体晶粒200与半导体晶粒300通过焊盘101和RDL结构102相互电连接。
在一些实施例中，半导体晶粒200的尺寸不同于半导体晶粒300的尺寸。例如，半导体晶粒200的尺寸(例如高度或体积等)小于半导体晶粒300的尺寸。
应当注意，图2所示的半导体晶粒的数量仅是示例，并且不限于实施例中公开的数量。
在其他一些实施例中，半导体晶粒200的功能电路与半导体晶粒300的功能电路不同。例如，半导体晶粒200和/或半导体晶粒300是包括中央处理单元(central processingunit，CPU)、图形处理单元(graphics processing unit，GPU)，动态随机接入存储器(dynamic random access memory，DRAM)控制器或这些任意组合。替代地，半导体晶粒200和/或半导体晶粒300是系统单晶粒(SOC)晶粒。在那些情况下，半导体晶粒200和300可以由不同的技术节点(例如10nm和14nm等等)形成。半导体晶粒200的尺寸和功能电路可以与半导体晶粒300的尺寸和功能电路均不同，或者至少其中任一一项不同。
图3是根据本发明的一些实施例的示例性半导体封装结构30的截面图。为简洁起见，以下实施例中与先前参考图2描述的元件相同或相似的元件的描述可以省略。在该实施例中，半导体封装结构30与图2所示的半导体封装结构20相似，除了半导体封装结构30还包括形成在导电图案层116和RDL结构102之间的间隙141中的无源器件170，并无源器件170电连接到RDL结构102。无源装置170可以设置在至少两个电连接器140之间，如图3所示。在一些实施例中，无源装置170包括电容器、电感器、电阻器或它们的组合。在一些实施例中，无源装置170是集成无源装置(integrated passive device，IPD)。在一些实施例中，无源器件170可以接触绝缘基板120的第二表面120b。
图4是根据本发明的一些实施例的示例性半导体封装结构40的截面图。为简洁起见，以下实施例中与先前参考图3描述的元件相同或相似的元件的描述可以省略。在该实施例中，半导体封装结构40类似于图3中所示的半导体封装结构30，除了半导体封装结构40还包括具有与无源器件170的尺寸(例如高度或体积等)不同的尺寸的无源器件172。在一些实施例中，无源器件172电连接到导电图案层116并且在半导体封装110b和电连接器150中的至少一个之间。在一些实施例中，无源器件172具有比无源器件170更大的尺寸。此外，无源器件172具有比电连接器140和无源器件170大的尺寸(例如，高度H3)。作为示例，无源器件172具有不小于100um的高度H3，无源器件170的高度不大于100um。此外，无源器件172的高度H3大于无源器件170的高度。本实施例中，无源器件170和无源器件172可以根据需求选择其中一个进行设置于半导体封装结构中，也可以均设置于半导体封装结构中。
在先前技术中，通常是单独的半导体晶粒或芯片安装在基板上，并且通过焊球或电连接器等连接到基板的RDL结构，这种方式需要在基板中形成RDL结构以及天线结构，然而RDL结构和天线结构所要求的制程是不同的，并且各自要求也不同(例如RDL结构要求间距较小，以实现更密集的布线；而天线结构的布置更多的考虑减小所受到的干扰)，因此若是在同一个基板上形成RDL结构和天线结构，将会使基板的制程更加复杂，成本更高，并且良品率也难以保证。本发明实施例中，将RDL结构设置在晶粒所在的封装结构中，而将RDL结构(用于将晶粒电连接到其他结构)设置在晶粒所在的封装结构中，这样就可以将不同要求的两种布线(RDL结构和天线结构)分开在两个封装中形成；这样就将需要更加精密制程的RDL结构与晶粒在一个封装中制造形成，将无需那样精密制程的天线结构放在基板的制程中一起形成；以实现更高的制造效率，并且简化制程步骤，降低成本，同时分开制造不仅可以提高制造时的良品率，并且还可以在两个封装组装时，使用已知良好的封装进行组装，从而进一步提高良品率。另外，本实施例中将较大的电连接器150设置在天线结构所在的基板上(绝缘基板120)，以与天线结构的制程相适应(天线结构的布线间距较宽，因此更加容易设置较大的焊球或电连接器)，方便制造。半导体封装(半导体封装110a或110b)上仅有较小的电连接器140，并且位于天线基板(绝缘基板120)与半导体封装(半导体封装110a或110b)之间以将两者电连接，因此整个半导体封装结构(半导体封装结构10-40，或称为天线封装结构)的尺寸(例如高度或厚度)较小，适用范围更广，使用场景更灵活。本实施例中半导体晶粒30或40可以仅通过电连接器140连接到外部，因此RDL结构等的布线更加一致，方便布线和制造。本实施例中，晶粒可以通过导电迹线116b连接到电连接器150，并且天线元件(例如第二天线元件118)也可以连接到电连接器150，这样不仅均可以通过电连接器150连接到封装结构(或天线封装)外部，并且还可以将天线元件与半导体晶粒电连接，因此这种连接方式使用了更加简便和短路径进行电连接，简化了布线并且提高了传输效率，减小了传输损耗。根据前述实施例，半导体封装结构被设计为将天线制造集成到半导体封装结构中。在半导体封装结构中，允许在绝缘基板中形成天线，该绝缘基板通过使用凸块结构(例如，焊球)而接合到半导体封装的RDL结构。与接合有半导体晶粒/芯片的基于基板的天线相比，由于下面的半导体封装的细间距(fine pitch)的RDL结构，可以减小带有天线的绝缘基板的厚度。因此，可以减小半导体封装结构的尺寸以及晶粒到天线的损耗。由于天线是通过成熟的基板技术制造的，因此紧凑且扇出与天线集成的封装，可以降低半导体封装结构的制造成本，并且可以简化半导体封装结构的制造制程。
根据前述实施例，由于其中具有天线的绝缘基板的厚度减小，以提供半导体封装中的半导体晶粒的短的散热路径，所以可以提高热性能。
根据前述实施例，因为天线形成在与其中具有半导体晶粒的半导体封装件分离的绝缘基板中，所以在半导体封装结构的制造期间可以使用已知的良好的晶粒封装和已知的良好的天线从而防止了良率损失并进一步降低了半导体封装结构的制造成本。
根据前述实施例，由于在将那些半导体晶粒放置在半导体封装中之前，可以通过不同的技术节点来形成半导体晶粒，所以可以启用晶粒分隔，并且可以简化半导体封装的制造制程，从而降低了半导体封装的制造成本。
根据前述实施例，由于无源器件集成在半导体封装结构中，所以可以改善电性能。
根据前述实施例，由于可以将具有不同尺寸的无源器件集成在半导体封装结构中，因此可以进一步提高电性能。此外，可以增加将大型无源器件集成到半导体封装结构中的灵活性。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (10)

1.一种半导体封装结构，其特征在于，包括：
天线装置，包括：导电图案层，包括第一天线元件，形成在绝缘基板中并且邻近于该绝缘基板的第一表面；第二天线元件，形成在该绝缘基板的与该第一表面相对的第二表面上；以及
半导体封装，包括：重分布层结构，接合并电连接到该导电图案层；第一半导体晶粒，电连接到该重分布层结构；密封层，形成在该重分布层结构上并围绕该第一半导体晶粒。
2.如权利要求1所述的半导体封装结构，其特征在于，还包括：
第一电连接器，将该重分布层结构接合到该导电图案层，使得该导电图案层与该重分布层结构由间隙隔开；以及
第二电连接器，电连接到该导电图案层并围绕该半导体封装。
3.如权利要求2所述的半导体封装结构，其特征在于，该第一电连接器和该第二电连接器是焊球，并且该第二电连接器的焊球尺寸不同于该第一电连接器的焊球尺寸。
4.如权利要求2所述的半导体封装结构，其特征在于，还包括：
无源器件，形成在该导电图案层和该重分布层结构之间的该间隙中并电连接到该重分布层结构，或/和，电连接到该导电图案层并且在该半导体封装和该第二电连接器中的至少一个之间。
5.如权利要求4所述的半导体封装结构，其特征在于，该第一电连接器的高度低于该无源器件的高度。
6.如权利要求1所述的半导体封装结构，其特征在于，所述半导体封装还包括：
第二半导体晶粒，电连接至该重分布层结构并由封装层围绕，其中，该第二半导体晶粒的尺寸不同于该第一半导体晶粒的尺寸，或/和，该第二半导体晶粒的功能电路与该第一半导体晶粒的功能电路不同。
7.如权利要求1所述的半导体封装结构，其特征在于，该天线装置还包括：
至少一个通孔结构，形成在该绝缘基板中并该电连接在该第一天线元件和该第二天线元件之间。
8.一种半导体封装结构，其特征在于，包括：
重分布层结构，具有第一表面和与该第一表面相对的第二表面；
第一半导体晶粒，具有形成在该重分布层结构的该第一表面上的有源表面；
第一电连接器，形成在该重分布层结构的该第二表面上；
绝缘基板，具有第一表面，堆栈在重分布层结构的第二表面上；
导电图案层，包括第一天线元件，形成在该绝缘基板中并与绝缘基板的该第一表面相邻；
第二天线元件，形成在该绝缘基板的与该绝缘基板的该第一表面相对的第二表面上；以及
第二电连接器，形成在该绝缘基板的该第一表面上并且电连接到该第一天线元件，其中，该第二电连接器的尺寸大于该第一电连接器的尺寸。
9.如权利要求8所述的半导体封装结构，其特征在于，还包括：
封装层，形成在该重分布层结构的该第一表面上并围绕该第一半导体晶粒。
10.如权利要求8所述的半导体封装结构，其特征在于，还包括：
第二半导体晶粒，具有在该重分布层结构的该第一表面上形成的该有源表面；以及
密封层，形成在该重分布层结构的该第一表面上并且在该第一半导体晶粒和该第二半导体晶粒之间并围绕该第一半导体晶粒和该第二半导体晶粒。
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