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TWI872938B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI872938B
TWI872938B TW113104160A TW113104160A TWI872938B TW I872938 B TWI872938 B TW I872938B TW 113104160 A TW113104160 A TW 113104160A TW 113104160 A TW113104160 A TW 113104160A TW I872938 B TWI872938 B TW I872938B
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Taiwan
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package
semiconductor device
bottom package
conductive
area
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TW113104160A
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English (en)
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TW202439553A (zh
Inventor
郭哲宏
于達人
黃啟宏
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聯發科技股份有限公司
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Abstract

提供了一種半導體裝置。該半導體裝置包括底部封裝和頂部封裝。該頂部封裝安裝在底部封裝上。該頂部封裝的至少一部分從底部封裝的側壁突出。該半導體裝置進一步包括一個被動元件，安裝在頂部封裝的部分的突出區域上。

Description

半導體裝置
本發明涉及一種半導體裝置，特別是一種封裝上封裝（package-on-package，簡稱 PoP）半導體封裝。
隨著對更小型且功能更多的裝置需求增加，封裝上封裝（PoP）技術變得越來越受歡迎。PoP技術垂直堆疊兩個或更多封裝，並將不同元件（例如控制器和記憶體裝置）之間的跟踪長度最小化。這提供了更好的電氣性能，因為較短的互連路由導致信號傳播更快，並減少了噪聲和串擾缺陷。
儘管現有的半導體封裝通常是足夠的，但它們在各方面並不令人滿意。例如，滿足高速記憶體封裝要求的同時，保持邏輯封裝的尺寸和製造成本是一個挑戰。因此，有必要進一步改進半導體封裝，以提供結構設計的靈活性。
為解決上述問題，本發明提供了半導體裝置。由於如本發明提供的半導體裝置，可以保持底部封裝的小尺寸並提高設計靈活性。
本發明的一個實施例提供了一種半導體裝置。該半導體裝置包括底部封裝和頂部封裝。頂部封裝安裝在底部封裝上。頂部封裝的至少一部分從底部封裝的側壁突出。
在一些實施例中，頂部封裝使用第一導電元件安裝在底部封裝上。在一些實施例中，第一導電元件與底部封裝重疊。在一些實施例中，從底部封裝的側壁突出的部分的距離大於0毫米且小於或等於5毫米。在一些實施例中，頂部封裝在俯視圖中完全覆蓋底部封裝。在一些實施例中，頂部封裝的一個邊與相應的底部封裝側壁齊平。在一些實施例中，頂部封裝的兩個或三個邊與相應的底部封裝側壁齊平。在一些實施例中，頂部封裝在俯視圖中部分覆蓋底部封裝。在一些實施例中，底部封裝的第一部分在俯視圖中從頂部封裝露出。
在一些實施例中，半導體裝置進一步包括安裝在頂部封裝的部分的突出區域上的被動元件。在一些實施例中，被動元件和底部封裝並排排列且設置在頂部封裝的同一側。在一些實施例中，被動元件和底部封裝透過不同的導電元件與頂部封裝電連接。在一些實施例中，在俯視圖中，底部封裝具有第一面積並且頂部封裝具有大於第一面積的第二面積，其中，第一面積與第二面積之差值與第一面積的比值大於0且小於或等於0.56。在一些實施例中，底部封裝包括多晶粒封裝。在一些實施例中，底部封裝包括位於底部封裝的第一半導體晶粒和頂部封裝之間的路由結構。在一些實施例中，半導體裝置是高帶寬封裝上封裝（high bandwidth package-on-package，簡稱 HBPoP）封裝或扇出封裝上封裝（扇出 package-on-package，簡稱 扇出 PoP）封裝。在一些實施例中，頂部封裝透過導電元件安裝在底部封裝上。導電元件與路由結構接觸。在一些實施例中，底部封裝包括圍繞底部封裝的至少一個第一半導體晶粒的導電互連件。導電元件分別與第一導電互連件接觸。在一些實施例中，底部封裝包括覆蓋第一半導體晶粒的第一模塑料，導電互連件穿過第一模塑料。在一些實施例中，頂部封裝包括第二半導體晶粒和第二模塑料。第二模塑料覆蓋第一半導體晶粒並且與第一模塑料由導電元件分隔。
本發明的另一個實施例提供了一種半導體裝置。該半導體裝置包括底部封裝和頂部封裝。頂部封裝安裝在底部封裝上。頂部封裝的至少一個邊緣向外延伸超出底部封裝的相應側壁。
在一些實施例中，頂部封裝的至少一個邊緣向外延伸超出底部封裝的相應側壁一距離，其中該距離大於0毫米且小於或等於5毫米。在一些實施例中，頂部封裝部分覆蓋底部封裝，或頂部封裝完全覆蓋底部封裝。在一些實施例中，底部封裝具有第一面積並且頂部封裝具有大於第一面積的第二面積，其中，第一面積與第二面積之差值與第一面積的比值大於0且小於或等於0.56。在一些實施例中，半導體裝置進一步包括安裝在頂部封裝的延伸部分上的被動元件，其中被動元件設置在底部封裝的相應側壁旁邊。
本發明的半導體裝置由於包括：底部封裝和頂部封裝。頂部封裝安裝在底部封裝上。頂部封裝的至少一部分從底部封裝的側壁突出。本發明的方案可以保持底部封裝的小尺寸並提高設計靈活性。並且不必為了較大尺寸的頂部封裝而特意更換較大尺寸的底部封裝，因此，底部封裝的成本可以降低。此外本發明的方案使頂部封裝和底部封裝的搭配具有更加靈活的選擇和配置。
本發明的以下描述旨在說明本發明的一般原則，不應以限制性的方式理解。本發明的範圍最好通過參考所附的請求項來確定。
在先進的封裝技術中，高端產品通常採用封裝上封裝（package-on-package ，PoP）結構（例如，動態隨機存取記憶體（dynamic random access memory ，DRAM）封裝堆疊在系統單晶片（system-on-chip ，SOC）封裝之上）以滿足高速雙倍數據速率（double data rate ，DDR）的性能要求。通常，底部封裝（例如，SOC封裝）的尺寸大於或等於頂部封裝（例如，DRAM封裝）。為了滿足高速DRAM的要求，DRAM封裝的尺寸可以大於當前SOC封裝的尺寸。隨著DRAM封裝尺寸的增加，底部封裝（例如，SOC封裝）的尺寸和製造成本可以相應增加，以遵循傳統的封裝堆疊規則（底部封裝尺寸≥頂部封裝尺寸）。因此，一種新型的封裝上封裝（PoP）結構是可取的。
第1圖是根據本發明一些實施例的半導體裝置500A的橫截面視圖。在一些實施例中，半導體裝置500A是一種三維（three-dimensional ，3D）封裝上封裝（PoP）半導體封裝，包含高帶寬封裝上封裝（high bandwidth package-on-package ，HBPoP）封裝或扇出封裝上封裝（fan-out PoP，扇出PoP）封裝。例如，半導體裝置500A可以是一種高帶寬封裝上封裝（HBPoP）封裝。第2圖是根據本發明一些實施例的第1圖中半導體裝置500A的頂部封裝400的透視底視圖。半導體裝置500A可以包括至少兩個垂直堆疊的半導體封裝，安裝在基座200上。如第1圖所示，在一些實施例中，半導體裝置500A包括底部封裝300A和垂直堆疊在底部封裝300A上的頂部封裝400。在一些實施例中，底部封裝300A包括一種扇出封裝，例如系統單晶片（system-on-chip，SOC）封裝。或者，底部封裝300A可以包括堆疊晶片封裝。頂部封裝400包括一種記憶體封裝，例如動態隨機存取記憶體（DRAM）封裝。
如第1圖所示，基座200，例如印刷電路板（PCB），可以由聚丙烯（polypropylene ，PP）、預浸料（Pre-preg）、FR-4和/或其他環氧層壓材料製成。還應該注意，基座200可以是單層或多層結構。多個焊墊（pad）202和/或導電線路（未顯示）設置在基座200上。在一個實施例中，導電線路可以包括信號線路段或接地線路段，用於底部封裝300和頂部封裝400的輸入/輸出（input/output ，I/O）連接。此外，底部封裝300A直接安裝在導電線路上。在其他一些實施例中，焊墊202設置在基座200上，並且焊墊202連接到導電線路的不同端子。焊墊202用於直接安裝在其上的底部封裝300A。
如第1圖所示，底部封裝300A通過接合製程安裝在基座200上。底部封裝300A使用導電元件322安裝在基座200上。在一些實施例中，底部封裝300A是一種三維（3D）半導體封裝，包含至少一個半導體晶粒102、前側路由結構316、背側路由結構366、導電互連件314和導電元件322。
半導體晶粒102具有主動表面102as和與主動表面102as相對的背側表面102bs。在一些實施例中，半導體晶粒102是通過倒裝晶片技術製造的。半導體晶粒102可以被翻轉以置於與導電元件322相對的前側路由結構316上。在一些實施例中，半導體晶粒102包括系統單晶片（SOC）晶粒、邏輯裝置、記憶體裝置、射頻（radio frequency，RF）裝置、類似裝置或其任何組合。例如，半導體晶粒102可以包括微控制單元（micro control unit ，MCU）晶粒、微處理器單元（microprocessor unit，MPU）晶粒、功率管理集成電路（power management integrated circuit ，PMIC）晶粒、全球定位系統（global positioning system，GPS）裝置、中央處理單元（central processing unit ，CPU）晶粒、圖形處理單元（graphics processing unit ，GPU）晶粒、輸入輸出（input-output，IO）晶粒、動態隨機存取記憶體（dynamic random access memory ，DRAM）IP核心、靜態隨機存取記憶體（static random-access memory，SRAM）、高帶寬記憶體（high bandwidth memory ，HBM）、類似裝置或其任何組合。
前側路由結構316設置在半導體晶粒102的主動表面102as上。此外，前側路由結構316沿方向120設置在半導體晶粒102和基座200之間。主動表面102as上的焊墊104通過導電元件112電連接到前側路由結構316。在一些實施例中，導電元件112包括導電材料，例如金屬。導電元件112可以包括微凸塊、控制塌陷晶片連接（controlled collapse chip connection ，C4）凸塊、球柵陣列（ball grid array ，BGA）球、類似裝置或其組合。在一些實施例中，前側路由結構316包括中介層、重分佈層（redistribution layer，RDL）結構或基板。例如，前側路由結構316可以是中介層316。如第1圖所示，前側路由結構316可以包括一個或多個導電線路319、設置在一個或多個介電層317中的一個或多個通孔318和接觸焊墊320。導電線路319電連接到相應的接觸焊墊320。接觸焊墊320暴露於阻焊層（solder mask layer）（未顯示）的開口處並靠近基座200。導電元件322設置在並與相應的接觸焊墊320接觸。因此，導電元件322在半導體封裝300A的接觸焊墊320和基座200的焊墊202之間電連接。半導體晶粒102通過前側路由結構316的通孔318、導電線路319和接觸焊墊320以及相應的導電元件322電連接到基座200。在一些實施例中，通孔318、導電線路319和接觸焊墊320包括導電材料，例如包括銅、金、銀或其他適用金屬。介電層317可以包括超低K（extra-low K ，ELK）介電材料和/或超低K（ultra-low K ，ULK）介電材料。此外，介電層317可以包括環氧樹脂。然而，應該注意的是，第1圖中顯示的介電層317的數量、通孔318的數量、導電線路319的數量和接觸焊墊320的數量僅僅是一個例子，並不限制本發明。
導電互連件314，例如通孔（through via，TV）、中介層柱（interposer pillar）或導電球結構，設置在前側路由結構316上並位於半導體晶粒102旁邊。如第1圖所示，導電互連件314電連接到前側路由結構316的通孔318、導電線路319和接觸焊墊320。導電互連件314可以圍繞底部封裝300A的半導體晶粒102。此外，導電互連件314可以通過前側路由結構316內的通孔318和導電線路319電連接到半導體晶粒102。
如第1圖所示，底部封裝300進一步包括模塑料312，設置在並接觸前側路由結構316上。模塑料312覆蓋並接觸半導體晶粒102。此外，模塑料312圍繞並接觸導電互連件314。導電互連件314可以穿過模塑料312。半導體晶粒102的背側表面102bs可以被模塑料312覆蓋或從模塑料312露出。在一些實施例中，模塑料312可以由非導電材料製成，例如環氧樹脂、樹脂、可模塑聚合物或類似物。模塑料312可以在基本上是液態時應用，然後可以通過化學反應固化，例如在環氧樹脂或樹脂中。在其他實施例中，模塑料312可以是作為凝膠或可塑固體應用的紫外線（ultraviolet ，UV）或熱固化聚合物，能夠被設置在半導體晶粒102周圍，然後使用UV或熱固化製程固化。模塑料312可以使用模具固化。
背側路由結構366設置在半導體晶粒102的背側表面102bs上。此外，背側路由結構366沿著方向120位於半導體晶粒102和頂部封裝400之間，並且背側路由結構366與導電互連件314電連接。如第1圖所示，半導體晶粒102通過背側路由結構366與頂部封裝400分隔。模塑料312填充前側路由結構316和背側路由結構366之間的空間（未顯示），並且模塑料312與半導體晶粒102的側壁相鄰，模塑料312也與前側路由結構316的表面和背側路由結構366的表面相鄰。前側路由結構316和背側路由結構366與導電互連件314的相對應的相對端接觸。換句話說，半導體晶粒102和導電互連件314被前側路由結構316和背側路由結構366夾持。在一些實施例中，背側路由結構366通過導電互連件314和前側路由結構316與半導體晶粒102電連接。在一些實施例中，模塑料312的側壁312E與前側路由結構316的相應側壁316E和背側路由結構366的相應側壁366E齊平。因此，模塑料312的側壁312E、前側路由結構316的側壁316E和背側路由結構366的側壁366E可以共同作為底部封裝300A的封裝側壁（例如，如第1圖所示的底部封裝300A的對面側壁300S1和300S3）。
導電元件322與前側路由結構316接觸並電連接。此外，導電元件322與基座200電連接。在一些實施例中，導電元件322包括導電球結構，例如銅球，導電凸塊結構，例如銅凸塊或焊料凸塊結構，或導電柱結構，例如銅柱結構。例如，導電元件322可以是由導電柱結構和導電凸塊結構組成的控制塌陷晶片連接（controlled collapse chip connection，簡稱C4）結構。
在一些實施例中，背側路由結構366包括重分佈層（redistribution layer，簡稱RDL）結構或中介層。例如，背側路由結構366可以是中介層366。在一些實施例中，背側路由結構366包括一個或多個導電跡線369，一個或多個設置在一個或多個介電層367中的通孔368和接觸焊墊370。在一些實施例中，導電跡線369和接觸焊墊370的材料可以與導電線路319和接觸焊墊320的材料相似。通孔368的材料可以與通孔318的材料相似。此外，介電層367的材料可以與介電層317的材料相似。應該注意的是，如第1圖所示的介電層367的數量、通孔368的數量、導電跡線369的數量和接觸焊墊370的數量僅是一個例子，並不限制本發明。
如第1圖所示，頂部封裝400通過導電元件422使用接合製程安裝在底部封裝300A上。此外，導電元件422與背側路由結構366接觸。如第2圖所示，頂部封裝400可以具有矩形平面視圖形狀。頂部封裝400可以具有沿方向100基本上相對的邊緣（或侧壁）400S1和400S3以及沿方向110基本上相對的邊緣（或侧壁）400S2和400S4。在一些實施例中，頂部封裝400包括記憶體封裝。例如，頂部封裝400包括動態隨機存取記憶體（dynamic random access memory，簡稱DRAM）封裝或其他適用的記憶體封裝。在一些實施例中，頂部封裝400包括基板418，至少一個半導體晶粒，例如兩個堆疊在基板418上的半導體晶粒402和404，以及導電元件422。在一些實施例中，每個半導體晶粒402和404包括動態隨機存取記憶體（DRAM）晶粒（例如，雙數據速率4（double data rate 4，DDR4）DRAM晶粒，低功耗DDR4（low-power DDR4，LPDDR4）DRAM晶粒），同步動態隨機存取記憶體（synchronous dynamic random access memory，簡稱SDRAM）晶粒或類似物）或其他適用的記憶體晶粒。在其他實施例中，半導體晶粒402和404可以包括相同或不同的裝置。在一些實施例中，頂部封裝400還包括一個或多個被動元件（未顯示），例如電阻、電容、電感、類似物或其組合。
在此實施例中，如第1圖所示，有兩個半導體晶粒402和404通過焊膏（未顯示）安裝在基板418上。半導體晶粒402和404具有相應的焊墊408和410。半導體晶粒402和404的焊墊408和410可以使用相應的接合引線414和416與基板418電連接。然而，堆疊半導體晶粒的數量不限於揭露的實施例。或者，如第1圖所示的半導體晶粒402和404可以並排排列並通過焊膏（未顯示）安裝在基板418上。或者，半導體晶粒402和404可以通過倒裝晶片（flip-chip）技術製造並且不使用接合引線414和416與基板418電連接。
如第1圖所示，基板418可以包括通孔428和設置在一個或多個超低K（extra-low K，簡稱ELK）和/或超低K（ultra-low K，簡稱ULK）介電層（未顯示）中的接觸焊墊420和430。接觸焊墊420設置在靠近基板418的頂表面（晶粒附接表面）418T的通孔428的頂部。此外，接合引線414和416與相應的接觸焊墊420電連接。接觸焊墊430設置在靠近基板418的底表面（凸塊附接表面）418B的通孔428的底部。接觸焊墊430可以位於通孔428的正下方或不正下方。接觸焊墊430與相應的接觸焊墊420電連接。在一些實施例中，接合引線414和416、接觸焊墊420和430以及通孔428包括導電材料，例如金屬包括銅、金、銀或其他適用金屬。
在一些實施例中，如第1圖所示，記憶體封裝400進一步包括覆蓋基板418的頂表面（晶粒附接表面）418T和半導體晶粒402和404的模塑料412。此外，模塑料412可以封裝半導體晶粒402和404以及接合引線414和416。模塑料412的頂表面可以作為頂部封裝400的頂表面400T。如第1圖所示，頂部封裝400的模塑料412可以通過導電元件422與底部封裝300A的模塑料312分隔。在一些實施例中，模塑料312和412可以包括相同或類似的材料和製造製程。
第2圖同時顯示了頂部封裝400的導電結構422堆疊在底部封裝300A上的位置。為了說明，虛線用來顯示底部封裝300A的位置。如第1圖所示，導電結構422設置在基板418的底表面418B上，與半導體晶粒402和404相對。導電結構422與基板418的相應接觸焊墊430以及背側路由結構366電連接（或接觸）。在一些實施例中，頂部封裝400的導電結構422（例如DRAM封裝）根據給定的排列方式排列。如第2圖所示，頂部封裝400的導電結構422沿著方向100和110以多列排列。在一些實施例中，導電結構422可以根據DDR的數據速率標準排列。例如，導電結構422的分佈區域可以具有空心正方形形狀。
如第2圖所示，導電結構422的位置可以保持在頂部封裝400和底部封裝300A的中心區域。在一些實施例中，導電結構422與底部封裝300A重疊。在一些實施例中，導電結構422包括導電球結構，如銅球，導電凸塊結構，如銅凸塊或焊錫凸塊結構，或導電柱結構，如銅柱結構。
第3、4、5和6圖是根據本發明的一些實施例，顯示頂部封裝400堆疊在底部封裝300A上的半導體裝置500A的平面圖，顯示頂部封裝400堆疊在底部封裝300A上的相對位置。請注意，第3、4、5和6圖僅為了說明而顯示頂部封裝400的邊緣400S1至400S4和底部封裝300A的側壁，其餘特徵可以顯示在第1圖的示意性剖面圖中。此外，第1圖也可以作為顯示在第3、4、5和6圖中的半導體裝置500A的沿著線A-A'的剖面圖。在一些實施例中，頂部封裝400至少有一部分400-EP從底部封裝300A的側壁300S（包括側壁300S1、300S2、300S3和300S4）突出。如第3、4、5和6圖所示，底部封裝300A可以具有矩形平面圖形狀。底部封裝300A可以具有相對的側壁300S1和300S3沿著方向100延伸，以及相對的側壁300S2和300S4沿著方向110延伸。在一些實施例中，如第3圖所示，頂部封裝400的邊緣400S1在方向110上向外延伸超出底部封裝300A的側壁300S1距離D1，邊緣400S2在方向100上向外延伸超出底部封裝300A的側壁300S2距離D2，邊緣400S3在方向110上向外延伸超出底部封裝300A的側壁300S3距離D3，以及邊緣400S4在方向100上向外延伸超出底部封裝300A的側壁300S4距離D4。在一些實施例中，距離D1、D2、D3和D4可以都不相等，或者至少有兩個是相等的。在一些實施例中，如第4圖所示，頂部封裝400的邊緣400S1在方向110上向外延伸超出底部封裝300A的側壁300S1距離D1，邊緣400S2可以與底部封裝300A的側壁300S2在方向100上齊平，邊緣400S3在方向110上向外延伸超出底部封裝300A的側壁300S3距離D3，以及邊緣400S4在方向100上向外延伸超出底部封裝300A的側壁300S4距離D4。在一些實施例中，距離D1、D3和D4可以都不相等，或者至少有兩個是相等的。上述設計可以增強靈活性並提供更多選擇以適應不同的應用場景。
在一些實施例中，頂部封裝400可以在俯視圖中完全覆蓋底部封裝300A，如第3和4圖所示。因此，如第3和4圖所示的半導體裝置500A也可以稱為全懸垂（fully-overhang）型半導體裝置500A，且頂部封裝400完全遮擋底部封裝300A，在俯視圖中底部封裝300A的任何部分都不會從頂部封裝400露出。例如，如第1和3圖所示，部分400-EP可以從底部封裝300A的四個側壁300S1、300S2、300S3和300S4突出。例如，如第1和4圖所示，部分400-EP可以從底部封裝300A的三個側壁300S1、300S3和300S4突出。在一些實施例中，全懸垂型半導體裝置500A可以保持較小的底部封裝尺寸並提高設計靈活性。因此，底部封裝300A的製造成本可以降低。此外，基座200可以提供額外的區域200R用於元件放置，如第1圖所示。
如第3和4圖所示，底部封裝300A可以具有第一面積A1，頂部封裝400具有大於第一面積A1的第二面積A2。在一些實施例中，第一面積A1與第二面積A2之差與第一面積A1的比值大於0且小於或等於0.56。如果該比值大於0.56，頂部封裝400的質心（重心）的垂直投影（沿著方向120）可能会位於俯視圖中底部封裝300A的外側。半導體裝置500A可以具有不平衡的質量分佈，並受到頂部封裝400的安裝穩定性影響。
在一些實施例中，頂部封裝400可以部分覆蓋底部封裝300A，並且在俯視圖中至少有一部分400-EP從底部封裝300A的側壁300S突出，如第5圖或第6圖所示。因此，如第5圖和第6圖所示的半導體裝置500A也可以稱為部分懸垂（partial-overhang）型半導體裝置500A。例如，如第1圖、第5圖和第6圖所示，部分400-EP可以從底部封裝300A的兩個側壁300S1和300S3突出並且圍繞底部封裝300A的兩個側壁300S1和300S3。在一些實施例中，在俯視圖中，底部封裝300A可以有從頂部封裝400露出的一個或多個部分P1。例如，如第5圖所示，底部封裝300A有兩個部分P1分別靠近側壁300S2和300S4，並在俯視圖中從頂部封裝400露出。例如，如第6圖所示，底部封裝300A有一個部分P1靠近側壁300S2，並在俯視圖中從頂部封裝400露出。需要注意的是，底部封裝300A從頂部封裝400露出的部分P1的數量和位置不限於公開的實施例。在一些實施例中，如第5圖所示，頂部封裝400的邊緣400S1在方向110上向外延伸超出底部封裝300A的側壁300S1距離D1，底部封裝300A的側壁300S2在方向100上向外延伸超出頂部封裝400的邊緣400S2，頂部封裝400的邊緣400S3在方向110上向外延伸超出底部封裝300A的側壁300S3距離D3，底部封裝300A的側壁300S4在方向100上向外延伸超出頂部封裝400的邊緣400S4。在一些實施例中，距離D1和D3可以相等或不等。在一些實施例中，如第6圖所示，頂部封裝400的邊緣400S1在方向110上向外延伸超出底部封裝300A的側壁300S1距離D1，底部封裝300A的側壁300S2在方向100上向外延伸超出頂部封裝400的邊緣400S2，頂部封裝400的邊緣400S3在方向110上向外延伸超出底部封裝300A的側壁300S3距離D3，頂部封裝400的邊緣400S4可以與底部封裝300A的側壁300S4在方向100上齊平。在一些實施例中，距離D1和D3可以相等或不等。上述設計可以增強靈活性，提供更多選擇以適應不同的應用場景。
在一些實施例中，部分懸垂型半導體裝置500A可以適用於不同尺寸的頂部封裝400，並提高設計靈活性。例如，頂部封裝400的第二面積A2可以大於、等於或小於底部封裝300A的第一面積A1。
如第3圖、第4圖、第5圖和第6圖所示，在一些實施例中，從底部封裝300A的側壁300S突出的部分400-EP的每個距離D1、D2、D3、D4都大於0且小於或等於5毫米。如果距離D1、D2、D3、D4大於5毫米，頂部封裝400可以有較差的安裝穩定性。
在一些實施例中，完全懸垂型半導體裝置500A的頂部封裝400可以至少有一個邊與相應的底部封裝側壁齊平。第7圖是根據一些實施例的半導體裝置500A的橫截面圖。第8圖和第9圖是根據一些實施例的第7圖中的半導體裝置500A的透視底視圖，顯示堆疊在底部封裝300A上的頂部封裝400的相對位置。第4圖也可以作為第7圖中的半導體裝置500A的透視底視圖。此外，第7圖也可以作為沿著第8圖和第9圖中顯示的半導體裝置500A的線A-A’的橫截面圖，以及沿著第4圖中顯示的半導體裝置500A的線B-B’的橫截面圖。為了簡潔起見，此後的實施例中與前面參照第1圖至第6圖描述的相同或相似的元素不再重複。
例如，如第4圖和第7圖所示，頂部封裝400的邊緣400S2可以與底部封裝300A的相應側壁300S2齊平。例如，如第4圖和第8圖所示，頂部封裝400的兩個邊緣400S1和400S2可以與底部封裝300A的相應側壁300S1和300S2齊平。例如，如第4圖和第9圖所示，頂部封裝400的三個邊緣400S1、400S2和400S3可以與底部封裝300A的相應側壁300S1、300S2和300S3齊平。
同樣地，在一些實施例中，如第8圖和第9圖所示，第一面積A1與第二面積A2之差與第一面積A1的比值大於0且小於或等於0.56。此外，從底部封裝300A的側壁300S突出的部分400-EP的距離D3和D4可以大於0且小於或等於5毫米。
在一些實施例中，從底部封裝的側壁突出的頂部封裝的部分可以提供額外的區域供電子元件放置。第10圖是根據一些實施例的半導體裝置500B的橫截面圖。為了簡潔起見，此後的實施例中與前面參照第1圖至第9圖描述的相同或相似的元素不再重複。
半導體裝置500A與半導體裝置500B之間的一個區別是，半導體裝置500B進一步包括至少一個被動元件450。在一些實施例中，被動元件450可以安裝在頂部封裝400的部分400-EP的突出區域400PR上。此外，突出區域400PR可以位於頂部封裝400的基板418的底表面418B的一部分上。在一些實施例中，被動元件450和底部封裝300A並排排列且設置在頂部封裝400的同一側。例如，被動元件450和底部封裝300A並排排列且設置在頂部封裝400的基板418的底表面418B上，並且被動元件450設置在鄰近底部封裝300A的相應側壁（例如側壁300S3/300S4）旁。此外，被動元件450和底部封裝300A彼此分開。進一步地，被動元件450和底部封裝300A透過不同的導電元件與頂部封裝400電連接。例如，底部封裝300A透過導電元件422與頂部封裝400電連接。被動元件450透過與導電元件422不同的導電元件452與頂部封裝400電連接。此外，被動元件450可以設置在導電結構422的分佈區域之外。例如，被動元件450可以安裝在靠近任何邊緣400S1、400S2、400S3和400S4的突出區域400PR上。此外，被動元件450不必被模塑料覆蓋。在一些實施例中，被動元件450包括電容器、電感器、電阻器或其組合。例如，被動元件450可以是陸地側電容器（land-side capacitor，LSC）包含多層陶瓷電容器（multilayer ceramic capacitor，MLCC）、矽電容器或其他適用的電容器。
在一些實施例中，導電元件422和452可以包括相同或類似的材料和結構。此外，導電元件452的尺寸和間距可以與導電元件422相同或不同。例如，導電元件452的尺寸和間距可以小於導電元件422的尺寸和間距。
在一些實施例中，半導體裝置的底部封裝可以包括各種類型以提高設計靈活性，如下文更詳細描述。第11圖是根據本發明的一些實施例的半導體裝置500C的橫截面視圖。為了簡潔起見，以下實施例中與先前參照第1至10圖所描述的相同或類似的元素不再重複描述。在一些實施例中，半導體裝置500C包括頂部封裝400和底部封裝300B。此外，底部封裝300B可以包括多晶粒（multi-die）封裝。
如第11圖所示，底部封裝300B包括至少兩個半導體晶粒，例如，沿著方向100並排排列的半導體晶粒102和132。半導體晶粒102和132設置在前側路由結構316和背側路由結構366之間。半導體晶粒132具有主動表面132as和與主動表面132as相對的背側表面132bs。在一些實施例中，半導體晶粒102和132是使用倒裝晶片技術製造的。半導體晶粒102和132可以被翻轉以設置在與導電結構322相對的前側路由結構316上。半導體晶粒102的主動表面102as上的焊墊104和半導體晶粒132的主動表面132as上的焊墊134通過導電元件112和142與前側路由結構316電連接。半導體晶粒102和132通過前側路由結構316的通孔318、導電線路319和接觸焊墊320以及相應的導電元件322與基座200電連接。在一些實施例中，半導體晶粒132僅通過前側路由結構316內的通孔318和導電線路319與半導體晶粒102電連接。在一些實施例中，半導體晶粒102和132各自獨立包括系統單晶片（SOC）晶粒、邏輯裝置、記憶體裝置、無線頻率（RF）裝置、類似裝置或其任何組合。例如，半導體晶粒102和132可以各自獨立包括微控制單元（MCU）晶粒、微處理器單元（MPU）晶粒、電源管理集成電路（PMIC）晶粒、全球定位系統（GPS）裝置、中央處理單元（CPU）晶粒、圖形處理單元（GPU）晶粒、輸入輸出（IO）晶粒、動態隨機存取記憶體（DRAM）IP核心、靜態隨機存取記憶體（SRAM）、高帶寬記憶體（HBM）、類似裝置或其任何組合。在一些實施例中，半導體晶粒102和132具有不同的功能。在一些實施例中，半導體晶粒102和132是在不同的技術節點製造的。
第12圖是根據本發明的一些實施例的半導體裝置500D的橫截面視圖。為了簡潔起見，以下實施例中與先前參照第1至11圖所描述的相同或類似的元素不再重複描述。在一些實施例中，半導體裝置500D可以是扇出封裝上封裝（扇出POP）。半導體裝置500D包括頂部封裝400和底部封裝300C。此外，底部封裝300C可以包括設置在半導體晶粒102的主動表面102as和背側表面102bs上的前側路由結構316C和背側路由結構366C。在一些實施例中，前側路由結構316C是前側RDL結構316C，背側路由結構366C是背側RDL結構366C。在一些實施例中，前側RDL結構316C和背側RDL結構366C可以包括一個或多個導電跡線（未顯示）、設置在一個或多個介電層（未顯示）中的一個或多個通孔（未顯示）。在一些實施例中，導電元件322與前側RDL結構316C電連接並接觸，導電元件422與背側RDL結構366C電連接並接觸。
如第12圖所示，底部封裝300C可以進一步包括安裝在與半導體晶粒102相對的前側路由結構316C上的電子元件330。在一些實施例中，電子元件330具有焊墊332並通過導電線路319與前側路由結構316C電連接。在一些實施例中，電子元件330設置在導電結構322之間。電子元件330不必被模塑料覆蓋。在一些實施例中，電子元件330包括集成被動元件（integrated passive device，IPD）包含電容器、電感器、電阻器或其組合。例如，電子元件330可以是陸地側電容器（LSC）包含多層陶瓷電容器（MLCC）、矽電容器或其他適用的電容器。
第13圖是根據本發明的一些實施例的半導體裝置500D的橫截面視圖。為了簡潔起見，以下實施例中與先前參照第1至12圖所描述的相同或類似的元素不再重複描述。半導體裝置500B和半導體裝置500E之間的差異之一是，半導體裝置500E的底部封裝300D是沒有背側路由結構366製造的。因此，模塑料312的頂表面312T可以作為底部封裝300D的頂表面312T。此外，靠近頂部封裝400的導電互連件314的端部可以暴露於模塑料312的頂表面312T。在一些實施例中，導電元件422與相應的導電互連件314接觸。
值得注意的是，第10至13圖僅顯示了半導體裝置500B、500C、500D和500E的橫截面視圖以供說明。應該理解的是，儘管一些特徵在一些實施例中顯示但在其他實施例中未顯示，這些特徵可以（或可以不）在其他實施例中存在，只要可以。例如，儘管第3-6、8和9圖的示例實施例中顯示了頂部封裝400和半導體裝置500A的底部封裝300A之間的相對位置的特定排列，但第10-13圖的半導體裝置500B/500C/500D/500E的頂部封裝400和底部封裝300B/300C/300D之間的相對位置的任何其他組合的排列也可以適用。
本發明實施例提供了一種半導體裝置，例如封裝上封裝（PoP）半導體封裝。半導體裝置包括底部封裝和頂部封裝。底部封裝安裝在基座上。頂部封裝安裝在底部封裝上。在一些實施例中，頂部封裝的至少一部分從底部封裝的側壁突出。換句話說，頂部封裝可以具有至少一個懸垂部分。在一些實施例中，頂部封裝完全覆蓋底部封裝的半導體裝置可以被稱為全懸垂型半導體裝置。全懸垂型半導體裝置可以保持底部封裝的小尺寸並提高設計靈活性。因此，底部封裝的製造成本可以降低。此外，基座可以有更多可用的元件放置區域。在一些實施例中，頂部封裝可以部分覆蓋底部封裝。因此，頂部封裝部分覆蓋底部封裝的半導體裝置可以被稱為部分懸垂型半導體裝置。部分懸垂型半導體裝置可以適應不同尺寸的頂部封裝並提高設計靈活性。在一些實施例中，頂部封裝的懸垂部分可以提供額外的被動元件放置區域。在一些實施例中，底部封裝可以具有各種類型。因此，製造的半導體裝置可以具有不同的類型，例如高帶寬封裝上封裝（HBPoP）封裝或扇出封裝上封裝（扇出PoP）封裝，以提高設計靈活性。
雖然本發明已通過示例和首選實施例的方式進行了描述，但應理解本發明並不限於所披露的實施例。相反，其旨在涵蓋各種修改和類似安排（對於那些熟練的技術人員來說應該是顯而易見的）。因此，附加的請求範圍應賦予最廣泛的解釋，以涵蓋所有這些修改和類似安排。
100,110,120:方向 102:半導體晶粒 112:導電元件 102as:主動表面 102bs:背側表面 104, 202,408,410:焊墊 200:基座 200R:區域 300A:底部封裝 312,412:模塑料 320,370,420,430:接觸焊墊 300S1, 300S2,300S3, 300S4,312E, 316E,366E:側壁 314:導電互連件 316:前側路由結構 317,367:介電層 318,368:通孔 319:導電線路 322,422,452:導電元件 366:背側路由結構 369:導電跡線 500A,500B,500C,500D,500E:半導體裝置 400:頂部封裝 400S1, 400S2, 400S3, 400S4:邊緣 P1,400-EP:部分 400T, 418T:頂表面 402,404:半導體晶粒 414,416:接合引線 418:基板 418B:底表面 428:通孔 A1:第一面積 A2:第二面積 D1,D2,D3,D4:距離 450:被動元件
本發明可透過閱讀後續的詳細描述和範例，並參考隨附的圖片，以更完整地理解，其中： 第1圖是根據本發明一些實施例的半導體裝置的橫截面視圖； 第2圖是根據本發明一些實施例的第1圖中半導體裝置的頂部封裝的透視底視圖，顯示頂部封裝堆疊在底部封裝上的導電結構的位置； 第3、4、5和6圖是根據本發明一些實施例的第1圖中半導體裝置的平面視圖，顯示頂部封裝堆疊在底部封裝上的相對位置； 第7圖是根據本發明一些實施例的半導體裝置的橫截面視圖； 第8和9圖是根據本發明一些實施例的第7圖中半導體裝置的平面視圖，顯示頂部封裝堆疊在底部封裝上的相對位置； 第10圖是根據本發明一些實施例的半導體裝置的橫截面視圖； 第11圖是根據本發明一些實施例的半導體裝置的橫截面視圖； 第12圖是根據本發明一些實施例的半導體裝置的橫截面視圖；以及 第13圖是根據本發明一些實施例的半導體裝置的橫截面視圖。
100,120:方向
102:半導體晶粒
112:導電元件
102as:主動表面
102bs:背側表面
104,202,408,410:焊墊
200:基座
200R:區域
300A:底部封裝
312,412:模塑料
320,370,420,430:接觸焊墊
300S1,300S3,312E,316E,366E:側壁
314:導電互連件
316:前側路由結構
317,367:介電層
318,368:通孔
319:導電線路
322,422:導電元件
366:背側路由結構
369:導電跡線
500A:半導體裝置
400:頂部封裝
400S1,400S2,400S3,400S4:邊緣
400-EP:部分
400T,418T:頂表面
402,404:半導體晶粒
414,416:接合引線
418:基板
418B:底表面
428:通孔

Claims (13)

  1. 一種半導體裝置，包括： 底部封裝；以及 頂部封裝，安裝在該底部封裝上； 其中，該頂部封裝的至少一部分從該底部封裝的側壁突出； 其中在俯視圖中，該底部封裝具有第一面積並且該頂部封裝具有大於該第一面積的第二面積，其中，該第一面積與該第二面積之差值與該第一面積的比值大於0且小於或等於0.56； 其中該底部封裝包括位於該頂部封裝和該底部封裝的第一半導體晶粒之間的路由結構；其中該頂部封裝使用第一導電元件安裝在該底部封裝上，且該第一導電元件與該路由結構接觸。
  2. 如請求項1之半導體裝置，其中該至少一部分從該側壁突出的距離大於0毫米且小於或等於5毫米。
  3. 如請求項2之半導體裝置，其中該頂部封裝在俯視圖中完全覆蓋該底部封裝。
  4. 如請求項1之半導體裝置，其中該頂部封裝的至少一個邊與該相對應的側壁與該底部封裝齊平。
  5. 如請求項4之半導體裝置，其中該頂部封裝在俯視圖中部分覆蓋該底部封裝。
  6. 如請求項5之半導體裝置，其中該底部封裝的第一部分在俯視圖中從該頂部封裝露出。
  7. 如請求項6之半導體裝置，進一步包括： 被動元件，安裝在該頂部封裝的該至少一部分的突出區域上。
  8. 如請求項7之半導體裝置，其中該被動元件和該底部封裝並排排列且設置在該頂部封裝的同一側。
  9. 如請求項7之半導體裝置，其中該被動元件和該底部封裝透過不同的導電元件與該頂部封裝電連接。
  10. 如請求項1之半導體裝置，其中該半導體裝置是高帶寬封裝對封裝（HBPOP）封裝或扇出封裝對封裝（扇出POP）封裝。
  11. 如請求項1之半導體裝置，其中該頂部封裝使用第一導電元件安裝在該底部封裝上，其中該底部封裝包括圍繞該底部封裝的至少一個該第一半導體晶粒的導電互連件，且其中該第一導電元件與相應的該導電互連件接觸。
  12. 如請求項11之半導體裝置，其中該底部封裝包括覆蓋該第一半導體晶粒的第一模塑料，其中該導電互連件穿過該第一模塑料。
  13. 一種半導體裝置，包括： 底部封裝；以及 頂部封裝，安裝在該底部封裝上； 其中，該頂部封裝的至少一個邊緣向外延伸超出該底部封裝的相應側壁； 其中在俯視圖中，該底部封裝具有第一面積並且該頂部封裝具有大於該第一面積的第二面積，其中，該第一面積與該第二面積之差值與該第一面積的比值大於0且小於或等於0.56； 其中該底部封裝包括位於該頂部封裝件和該底部封裝的第一半導體晶粒之間的路由結構；其中該頂部封裝使用第一導電元件安裝在該底部封裝上，且該第一導電元件與該路由結構接觸。
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EP4439666A2 (en) 2024-10-02
EP4439666A3 (en) 2024-11-20

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