CN112151524A - Packaging structure and packaging method of fan-out type fingerprint identification chip - Google Patents
Packaging structure and packaging method of fan-out type fingerprint identification chip Download PDFInfo
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Abstract
Description
技术领域technical field
本发明属于半导体封装领域,特别是涉及一种扇出型指纹识别芯片的封装结构及封装方法。The invention belongs to the field of semiconductor packaging, and in particular relates to a packaging structure and a packaging method of a fan-out type fingerprint identification chip.
背景技术Background technique
随着集成电路的功能越来越强、性能和集成度越来越高,以及新型的集成电路出现,封装技术在集成电路产品中扮演着越来越重要的角色,在整个电子系统的价值中所占的比例越来越大。同时,随着集成电路特征尺寸达到纳米级,晶体管向更高密度、更高的时钟频率发展,封装也向更高密度的方向发展。As the functions of integrated circuits become stronger, their performance and integration become higher and higher, as well as the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and plays an increasingly important role in the value of the entire electronic system. The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanoscale, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density.
由于扇出晶圆级封装(fowlp)技术由于具有小型化、低成本和高集成度等优点,以及具有更好的性能和更高的能源效率,扇出晶圆级封装(fowlp)技术已成为高要求的移动/无线网络等电子设备的重要的封装方法,是目前最具发展前景的封装技术之一。Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a It is an important packaging method for electronic equipment such as high-demand mobile/wireless networks, and is one of the most promising packaging technologies at present.
指纹识别技术是目前最成熟且价格便宜的生物特征识别技术。目前来说,指纹识别的技术应用最为广泛,不仅在门禁、考勤系统中可以看到指纹识别技术的身影,市场上有了更多指纹识别的应用:如笔记本电脑、手机、汽车、银行支付都可应用指纹识别的技术。Fingerprint identification technology is currently the most mature and inexpensive biometric identification technology. At present, the technology of fingerprint recognition is the most widely used. Not only can fingerprint recognition technology be seen in access control and attendance systems, but there are more applications of fingerprint recognition in the market: such as laptops, mobile phones, automobiles, and bank payments. The technology of fingerprint recognition can be applied.
现有的一种指纹识别芯片的封装方法是将指纹采集芯片及指纹处理芯片分别焊接到PCB线路板上,而且这种封装方式需要占用较大的封装面积,PCB线路板的厚度较大,且封装线路较长,会导致封装结构具体体积大、响应速度慢等缺点。An existing packaging method for a fingerprint identification chip is to weld the fingerprint acquisition chip and the fingerprint processing chip to the PCB circuit board respectively, and this packaging method needs to occupy a large packaging area, the thickness of the PCB circuit board is relatively large, and the The long package circuit will lead to disadvantages such as large specific volume of the package structure and slow response speed.
基于以上所述,提供一种低成本、低体积以及高响应速度的指纹识别芯片的封装结构及封装方法实属必要。Based on the above, it is necessary to provide a low-cost, low-volume and high-response fingerprint identification chip packaging structure and packaging method.
发明内容SUMMARY OF THE INVENTION
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种扇出型指纹识别芯片的封装结构及封装方法,用于解决现有技术中指纹识别芯片的封装成本高、体积大及响应速度慢等问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a packaging structure and a packaging method for a fan-out fingerprint identification chip, which are used to solve the problems of high packaging cost, large volume and responsiveness of the fingerprint identification chip in the prior art. slow speed etc.
为实现上述目的及其他相关目的,本发明提供一种扇出型指纹识别芯片的封装结构,所述封装结构包括:线路层,所述线路层包括电性连接的第一面及第二面,所述线路层的第二面具有介质层,所述介质层中形成有开孔;指纹处理芯片,所述指纹处理芯片的第一面具有重新布线层,所述重新布线层用于指纹处理芯片的电性引出,所述指纹芯片的第二面粘附于所述线路层的第一面;指纹采集芯片,所述指纹采集芯片电性接合于所述重新布线层的第二面;金属连线,连接于所述重新布线层的第二面及所述线路层的第一面;封装层,覆盖于所述指纹处理芯片及所述指纹采集芯片;金属凸块,形成于所述开孔中。In order to achieve the above object and other related objects, the present invention provides a package structure of a fan-out fingerprint identification chip, the package structure includes: a circuit layer, the circuit layer includes a first surface and a second surface that are electrically connected, The second surface of the circuit layer has a dielectric layer, and the dielectric layer is formed with openings; the fingerprint processing chip, the first surface of the fingerprint processing chip has a re-wiring layer, and the re-wiring layer is used for the fingerprint processing chip The second surface of the fingerprint chip is adhered to the first surface of the circuit layer; the fingerprint collection chip is electrically connected to the second surface of the rewiring layer; the metal connection a wire connected to the second surface of the redistribution layer and the first surface of the circuit layer; a packaging layer covering the fingerprint processing chip and the fingerprint collection chip; metal bumps formed on the openings middle.
可选地,所述指纹采集芯片及所述指纹处理芯片为垂直堆叠设置。Optionally, the fingerprint collection chip and the fingerprint processing chip are vertically stacked.
可选地,所述封装层的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。Optionally, the material of the encapsulation layer includes one of polyimide, silica gel and epoxy resin.
可选地,所述指纹采集芯片显露于所述封装层的顶面。Optionally, the fingerprint collection chip is exposed on the top surface of the encapsulation layer.
可选地,所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。Optionally, the metal bumps include one of tin solder, silver solder and gold-tin alloy solder.
可选地,所述金属连线包括金线及银线中的一种。Optionally, the metal wire includes one of gold wire and silver wire.
本发明还提供一种扇出型指纹识别芯片的封装方法,包括步骤:1)提供一指纹处理芯片晶圆,于所述指纹处理芯片晶圆上形成重新布线层,所述重新布线层的第一面与所述指纹处理芯片晶圆连接,所述重新布线层用于指纹处理芯片的电性引出;2)切割所述指纹处理芯片晶圆及所述重新布线层,获得独立的指纹处理芯片;3)提供一支撑基底,于所述支撑基底上形成分离层,于所述分离层上形成所述线路层,将所述指纹处理芯片粘附于所述线路层的第一面,所述重新布线层背向所述线路层;4)提供一指纹采集芯片,将所述指纹采集芯片电性接合于所述重新布线层的第二面,所述指纹采集芯片及所述指纹处理芯片为垂直堆叠设置;5)采用金属连线连接所述重新布线层的第二面及所述线路层的第一面;6)采用封装层封装所述指纹处理芯片及所述指纹采集芯片;7)基于所述分离层剥离所述支撑基底及所述线路层,以显露所述线路层的第二面,于所述线路层的第二面形成金属凸块;8)对所述线路层进行切割,获得独立的扇出型指纹识别芯片的封装结构。The present invention also provides a packaging method for a fan-out fingerprint identification chip, comprising the steps of: 1) providing a fingerprint processing chip wafer, forming a rewiring layer on the fingerprint processing chip wafer, and the first layer of the rewiring layer is One side is connected with the fingerprint processing chip wafer, and the rewiring layer is used for electrical extraction of the fingerprint processing chip; 2) cutting the fingerprint processing chip wafer and the rewiring layer to obtain an independent fingerprint processing chip 3) Provide a support base, form a separation layer on the support base, form the circuit layer on the separation layer, and adhere the fingerprint processing chip to the first side of the circuit layer, the The rewiring layer faces away from the circuit layer; 4) a fingerprint collection chip is provided, and the fingerprint collection chip is electrically bonded to the second surface of the rewiring layer, and the fingerprint collection chip and the fingerprint processing chip are Vertical stacking arrangement; 5) Use metal wires to connect the second surface of the redistribution layer and the first surface of the circuit layer; 6) Use an encapsulation layer to encapsulate the fingerprint processing chip and the fingerprint acquisition chip; 7) The support substrate and the circuit layer are peeled off based on the separation layer to expose the second surface of the circuit layer, and metal bumps are formed on the second surface of the circuit layer; 8) Cutting the circuit layer , to obtain the packaging structure of an independent fan-out fingerprint identification chip.
可选地,所述支撑基底包括玻璃衬底、金属衬底、半导体衬底、聚合物衬底及陶瓷衬底中的一种。Optionally, the supporting base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.
可选地,所述分离层包括光热转换层;步骤7)采用激光照射所述光热转换层,以使所述光热转换层与所述封装层及所述支撑基底分离,进而剥离所述封装层及所述支撑基底。Optionally, the separation layer includes a light-to-heat conversion layer; step 7) irradiating the light-to-heat conversion layer with a laser, so as to separate the light-to-heat conversion layer from the encapsulation layer and the support substrate, and then peel off all the layers. the encapsulation layer and the support substrate.
可选地,步骤3)所述线路层的第二面具有介质层,步骤7)先于所述介质层中形成开孔,然后于所述开孔中形成所述金属凸块。Optionally, in step 3) the second surface of the circuit layer has a dielectric layer, and in step 7), an opening is formed in the dielectric layer first, and then the metal bump is formed in the opening.
可选地,采用封装层封装所述指纹处理芯片及所述指纹采集芯片的方法包括压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种,所述封装层的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。Optionally, the method for encapsulating the fingerprint processing chip and the fingerprint collection chip with an encapsulation layer includes one of compression molding, transfer molding, liquid sealing, vacuum lamination and spin coating, and the encapsulation layer has a The material includes one of polyimide, silica gel and epoxy resin.
可选地,步骤6)采用封装层封装所述指纹处理芯片及所述指纹采集芯片后,所述指纹采集芯片显露于所述封装层的顶面。Optionally, in step 6) after encapsulating the fingerprint processing chip and the fingerprint collection chip with an encapsulation layer, the fingerprint collection chip is exposed on the top surface of the encapsulation layer.
可选地,步骤5)采用焊线工艺于所述重新布线层的第二面及所述线路层的第一面之间形成所述金属连线。Optionally, step 5) adopts a wire bonding process to form the metal connection between the second surface of the redistribution layer and the first surface of the circuit layer.
可选地,所述金属连线包括金线及银线中的一种。Optionally, the metal wire includes one of gold wire and silver wire.
可选地,所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。Optionally, the metal bumps include one of tin solder, silver solder and gold-tin alloy solder.
如上所述,本发明的扇出型指纹识别芯片的封装结构及封装方法,具有以下有益效果:As described above, the packaging structure and packaging method of the fan-out fingerprint identification chip of the present invention have the following beneficial effects:
1)本发明采用扇出型封装(Fan out)指纹识别芯片,可将指纹采集芯片及指纹处理芯片集成在同一封装结构中,且指纹采集芯片及指纹处理芯片为垂直堆叠设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点。1) The present invention adopts a fan-out package (Fan out) fingerprint identification chip, which can integrate the fingerprint collection chip and the fingerprint processing chip in the same package structure, and the fingerprint collection chip and the fingerprint processing chip are vertically stacked. Some other fingerprint identification chip packages have the advantages of low cost, small thickness and high yield.
2)本发明的指纹采集芯片及指纹处理芯片垂直堆叠设置,可有效提高封装结构的响应速度。2) The fingerprint collection chip and the fingerprint processing chip of the present invention are vertically stacked, which can effectively improve the response speed of the packaging structure.
3)本发明在封装工艺中采用支撑基底进行支撑,可以有效保证工艺稳定性,提高封装良率。3) In the present invention, a support base is used for support in the packaging process, which can effectively ensure process stability and improve packaging yield.
附图说明Description of drawings
图1~图14显示为本发明的扇出型指纹识别芯片的封装方法各步骤所呈现的结构示意图,其中,图14显示为扇出型指纹识别芯片的封装结构的结构示意图。1 to 14 are schematic structural diagrams of each step of the packaging method of the fan-out fingerprint identification chip of the present invention, wherein FIG. 14 is a schematic structural diagram of the packaging structure of the fan-out fingerprint identification chip.
元件标号说明Component label description
201 指纹处理芯片晶圆201 Fingerprint processing chip wafer
202 重新布线层202 Rewiring Layer
20 指纹处理芯片20 Fingerprint processing chip
203 贴膜203 Film
301 线路层301 Line layer
302 介质层302 dielectric layer
303 开孔303 Opening
304 分离层304 Separation Layer
305 支撑基底305 Support base
401 指纹采集芯片401 Fingerprint Acquisition Chip
402 金属连线402 metal wire
403 封装层403 encapsulation layer
501 金属凸块501 Metal bump
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
如在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.
为了方便描述,此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到,这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外,当一层被称为在两层“之间”时,它可以是所述两层之间仅有的层,或者也可以存在一个或多个介于其间的层。For convenience of description, spatially relative terms such as "below," "below," "below," "below," "above," "on," etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. In addition, when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
在本申请的上下文中,所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.
需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and the number of components in the actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.
如图1~图14所示,本实施例提供一种扇出型指纹识别芯片的封装方法,所述封装方法包括以下步骤:As shown in FIG. 1 to FIG. 14 , this embodiment provides a packaging method for a fan-out fingerprint identification chip, and the packaging method includes the following steps:
如图1~图2所示,首先进行步骤1),提供一指纹处理芯片晶圆201,于所述指纹处理芯片晶圆201上形成重新布线层202,所述重新布线层202的第一面与所述指纹处理芯片晶圆201连接,所述重新布线层202用于指纹处理芯片20的电性引出,所述指纹处理芯片20用于对指纹采集芯片401所采集的指纹信号进行特征提取及特征比对等处理,实现指纹识别功能。As shown in FIG. 1 to FIG. 2 , step 1) is first performed, a fingerprint
所述指纹处理芯片晶圆201中具有多个阵列排布的指纹处理芯片20,每个指纹处理芯片20设置有相应的电极,首先在所述指纹处理芯片晶圆201上形成种子层,如Cu/Ti叠层等,然后刻蚀所述种子层,形成图形化的种子层,该图形化的种子层与指纹处理芯片20的电极连接,然后基于所述图形化的种子层,在所述指纹处理芯片晶圆201上形成重新布线层202。所述重新布线层202可以包括若干介质层及若干依据图形需求排布的金属布线层,相邻两金属布线层之间通过导电栓塞连接。所述介质层可以采用如涂覆或沉积等方法形成,其材料可以为环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃,含氟玻璃中的一种或两种以上组合。在本实施例中,所述介质层的材料可以为PI(聚酰亚胺),以进一步降低工艺难度以及工艺成本。所述金属布线层可以采用如电镀或溅射的方法以及刻蚀工艺形成,也可以采用如金属剥离工艺形成,其材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。在本实施例中,所述金属布线层的材料为铜。The fingerprint
如图3~图5所示,然后进行步骤2),切割所述指纹处理芯片晶圆201及所述重新布线层202,获得独立的指纹处理芯片20。As shown in FIGS. 3 to 5 , step 2) is performed, and the fingerprint
具体地,先将所述指纹处理芯片晶圆201背面粘附于一贴膜203,如蓝膜等,然后采用机械切割刀或激光切割刀对所述指纹处理芯片晶圆201进行切割,获得独立的指纹处理芯片20。Specifically, the backside of the fingerprint
如图6~图8所示,接着进行步骤3),提供一线路层301,将所述指纹处理芯片20粘附于所述线路层301的第一面,所述重新布线层202背向所述线路层301。As shown in FIG. 6 to FIG. 8 , step 3) is performed next, a
例如,步骤3)提供所述线路层301包括步骤:For example, step 3) providing the
3-1)提供一支撑基底305,于所述支撑基底305上形成分离层304,如图6所示。3-1) Provide a
例如,所述支撑基底305包括玻璃衬底、金属衬底、半导体衬底、聚合物衬底及陶瓷衬底中的一种。在本实施例中,所述支撑基底305选用为玻璃衬底,所述玻璃衬底成本较低,容易在其表面形成分离层304,且能降低后续的剥离工艺的难度。所述分离层304包括光热转换层,通过旋涂工艺形成于所述支撑基底305上后,通过固化工艺使其固化成型。光热转换层(LTHC)性能稳定,表面较光滑,有利于后续获得平坦的,在后续的剥离工艺中,剥离的难度较低。For example, the supporting
3-2)于所述分离层304上形成所述线路层301,如图7所示。所述线路层301可以包括若干介质层及若干依据图形需求排布的金属布线层,相邻两金属布线层之间通过导电栓塞连接,其中,所述线路层的第二面为介质层302,所述线路层的第二面的介质层302可有效保护所述线路层底部的金属,提高线路层的稳定性。所述介质层可以采用如涂覆或沉积等方法形成,其材料可以为环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃,含氟玻璃中的一种或两种以上组合。在本实施例中,所述介质层的材料可以为PI(聚酰亚胺),以进一步降低工艺难度以及工艺成本。所述金属布线层可以采用如电镀或溅射的方法以及刻蚀工艺形成,也可以采用如金属剥离工艺形成,其材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。在本实施例中,所述金属布线层的材料为铜。3-2) The
在形成所述线路层301后,可以采用粘附胶水将所述指纹处理芯片20粘附于所述线路层301的第一面,所述指纹处理芯片20具有重新布线层202的一面朝上放置,即背向所述线路层301,所述重新布线层202表面显露有金属布线层,如图8所示。After the
如图9所示,接着进行步骤4),提供一指纹采集芯片401,将所述指纹采集芯片401电性接合于所述重新布线层202的第二面,所述指纹采集芯片401及所述指纹处理芯片20为垂直堆叠设置。所述指纹采集芯片401用于采用人体指纹,并将采集信号传送至指纹处理芯片20进行处理。As shown in FIG. 9 , then proceed to step 4), providing a
例如,可以采用焊接工艺将所述指纹采集芯片401接合于所述重新布线层202的第二面,所述指纹采集芯片401及所述指纹处理芯片20为垂直堆叠设置。For example, the
如图10所示,接着进行步骤5),采用金属连线402连接所述重新布线层202的第二面及所述线路层301的第一面。As shown in FIG. 10 , step 5) is performed next, and
例如,可以采用焊线工艺于所述重新布线层202的第二面及所述线路层301的第一面之间形成所述金属连线402。所述金属连线402可以为金线及银线中的一种。For example, the
如图11所示,接着进行步骤6),采用封装层403封装所述指纹处理芯片20及所述指纹采集芯片401。As shown in FIG. 11 , step 6) is performed next, and the
例如,可以采用封装层403封装所述指纹处理芯片20及所述指纹采集芯片401的方法包括压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种,所述封装层403的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。采用封装层403封装所述指纹处理芯片20及所述指纹采集芯片401后,所述指纹采集芯片401显露于所述封装层403的顶面,以提高所述指纹采集芯片401的采集精度。For example, the method of encapsulating the
如图12~图14所示,接着进行步骤7),基于所述分离层304剥离所述支撑基底305及所述线路层301,以显露所述线路层301的第二面,于所述线路层301的第二面的介质层302中形成开孔303,于所述线路层301的第二面的所述开孔303中形成金属凸块501。As shown in FIG. 12 to FIG. 14 , step 7) is performed next, and the
在本实施例中,采用激光照射所述光热转换层,以使所述光热转换层与所述封装层403及所述支撑基底305分离,进而剥离所述封装层403及所述支撑基底305。In this embodiment, the light-to-heat conversion layer is irradiated with laser light to separate the light-to-heat conversion layer from the
所述金属凸块501可以为锡焊料、银焊料及金锡合金焊料中的一种。The metal bumps 501 may be one of tin solder, silver solder and gold-tin alloy solder.
最后进行步骤8),对所述线路层301进行切割,获得独立的扇出型指纹识别芯片的封装结构。Finally, step 8) is performed, and the
如图14所示,本实施例还提供一种扇出型指纹识别芯片的封装结构,所述封装结构包括:线路层301,所述线路层301包括电性连接的第一面及第二面,所述线路层301的第二面具有介质层302,所述介质层中形成有开孔303;指纹处理芯片20,所述指纹处理芯片20的第一面具有重新布线层202,所述重新布线层202用于指纹处理芯片20的电性引出,所述指纹芯片的第二面粘附于所述线路层301的第一面;指纹采集芯片401,所述指纹采集芯片401电性接合于所述重新布线层202的第二面;金属连线402,连接于所述重新布线层202的第二面及所述线路层301的第一面;封装层403,覆盖于所述指纹处理芯片20及所述指纹采集芯片401;金属凸块501,形成于所述线路层301的第二面介质层302的所述开孔303中。As shown in FIG. 14 , this embodiment also provides a package structure of a fan-out fingerprint identification chip, the package structure includes: a
可选地,所述指纹采集芯片401及所述指纹处理芯片20为垂直堆叠设置。本发明采用扇出型封装(Fan out)指纹识别芯片,可将指纹采集芯片401及指纹处理芯片20集成在同一封装结构中,且指纹采集芯片401及指纹处理芯片20为垂直堆叠设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点,同时,可有效提高封装结构的响应速度。Optionally, the
所述封装层403的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。所述金属凸块501包括锡焊料、银焊料及金锡合金焊料中的一种。所述金属连线402包括金线及银线中的一种。The material of the
所述指纹采集芯片401显露于所述封装层403的顶面,以提高所述指纹采集芯片401的采集精度。The
如上所述,本发明的扇出型指纹识别芯片的封装结构及封装方法,具有以下有益效果:As described above, the packaging structure and packaging method of the fan-out fingerprint identification chip of the present invention have the following beneficial effects:
1)本发明采用扇出型封装(Fan out)指纹识别芯片,可将指纹采集芯片及指纹处理芯片集成在同一封装结构中,且指纹采集芯片及指纹处理芯片为垂直堆叠设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点。1) The present invention adopts a fan-out package (Fan out) fingerprint identification chip, which can integrate the fingerprint collection chip and the fingerprint processing chip in the same package structure, and the fingerprint collection chip and the fingerprint processing chip are vertically stacked. Some other fingerprint identification chip packages have the advantages of low cost, small thickness and high yield.
2)本发明的指纹采集芯片及指纹处理芯片垂直堆叠设置,可有效提高封装结构的响应速度。2) The fingerprint collection chip and the fingerprint processing chip of the present invention are vertically stacked, which can effectively improve the response speed of the packaging structure.
3)本发明在封装工艺中采用支撑基底305进行支撑,可以有效保证工艺稳定性,提高封装良率。3) In the present invention, the
所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114758958A (en) * | 2022-03-11 | 2022-07-15 | 艾司博国际有限公司 | Fan-out packaging structure embedded with sensor or display chip and packaging method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101930971A (en) * | 2009-06-17 | 2010-12-29 | 联发科技股份有限公司 | Multi-chip packaging structure and method for forming multi-chip packaging structure |
KR20170086377A (en) * | 2016-01-18 | 2017-07-26 | 하나 마이크론(주) | Device for fan-out type track pad semiconductor package and method for manufacturing the same |
CN107240556A (en) * | 2017-07-28 | 2017-10-10 | 中芯长电半导体(江阴)有限公司 | The encapsulating structure and method for packing of face recognition chip |
CN107452702A (en) * | 2017-07-28 | 2017-12-08 | 中芯长电半导体(江阴)有限公司 | The encapsulating structure and method for packing of semiconductor chip |
CN108400120A (en) * | 2017-02-08 | 2018-08-14 | 南茂科技股份有限公司 | Fingerprint identification packaging structure |
CN208873718U (en) * | 2018-10-16 | 2019-05-17 | 深圳市金鹰汇科技有限公司 | Fingerprint sensing identification chip encapsulating structure |
CN209880615U (en) * | 2019-06-28 | 2019-12-31 | 中芯长电半导体(江阴)有限公司 | Packaging structure of fan-out type fingerprint identification chip |
-
2019
- 2019-06-28 CN CN201910571499.4A patent/CN112151524A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101930971A (en) * | 2009-06-17 | 2010-12-29 | 联发科技股份有限公司 | Multi-chip packaging structure and method for forming multi-chip packaging structure |
KR20170086377A (en) * | 2016-01-18 | 2017-07-26 | 하나 마이크론(주) | Device for fan-out type track pad semiconductor package and method for manufacturing the same |
CN108400120A (en) * | 2017-02-08 | 2018-08-14 | 南茂科技股份有限公司 | Fingerprint identification packaging structure |
CN107240556A (en) * | 2017-07-28 | 2017-10-10 | 中芯长电半导体(江阴)有限公司 | The encapsulating structure and method for packing of face recognition chip |
CN107452702A (en) * | 2017-07-28 | 2017-12-08 | 中芯长电半导体(江阴)有限公司 | The encapsulating structure and method for packing of semiconductor chip |
CN208873718U (en) * | 2018-10-16 | 2019-05-17 | 深圳市金鹰汇科技有限公司 | Fingerprint sensing identification chip encapsulating structure |
CN209880615U (en) * | 2019-06-28 | 2019-12-31 | 中芯长电半导体(江阴)有限公司 | Packaging structure of fan-out type fingerprint identification chip |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114758958A (en) * | 2022-03-11 | 2022-07-15 | 艾司博国际有限公司 | Fan-out packaging structure embedded with sensor or display chip and packaging method thereof |
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