CN211480020U

CN211480020U - Fan-out type system-in-package structure

Info

Publication number: CN211480020U
Application number: CN202020535641.8U
Authority: CN
Inventors: 陈彦亨; 林正忠; 吴政达
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2020-04-13
Filing date: 2020-04-13
Publication date: 2020-09-11
Anticipated expiration: 2030-04-13

Abstract

The utility model provides a fan-out type system in package structure, packaging structure includes: rewiring layers; the metal connecting column is electrically connected with the rewiring layer; the system level chip and the power management chip are electrically connected with the rewiring layer; the packaging layer covers the system-level chip and the power management chip and exposes the metal connecting column; the connecting wiring layer is formed on the packaging layer and is electrically connected with the metal connecting column; the metal bump is formed on the surface of the rewiring layer; the memory chip and the passive component are electrically connected with the connecting wiring layer. The utility model discloses can realize the system function demand of multiple difference, improve packaging structure's performance. The utility model discloses a three-dimensional encapsulation of piling up perpendicularly effectively reduces packaging structure's area, improves packaging structure's integrated level, imitates the conduction route between the short chip, reduces packaging structure's consumption, greatly reduced packaging structure's whole thickness.

Description

Fan-out type system-in-package structure

Technical Field

The utility model belongs to semiconductor integrated circuit encapsulates the field, especially relates to a fan-out type system level packaging structure and preparation method thereof.

Background

With the advent of the 5G communication and Artificial Intelligence (AI) era, the amount of data to be transmitted and processed interactively at high speed is enormous for chips applied in such related fields, which usually have huge number of pad pins (hundreds or even thousands), ultra-fine pin sizes and pitches (several microns or even smaller). On the other hand, the demands on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package a plurality of different high-density chips together to form a system or subsystem with powerful function and smaller volume and power consumption becomes a great challenge in the field of advanced packaging of semiconductor chips.

At present, for multi-chip integrated packaging of such high-density chips, the industry generally adopts Through Silicon Vias (TSVs), silicon interposer (Si interposer) and other manners, so as to lead out and effectively interconnect ultra-fine pins of the chips to form a functional module or system, but the technology has higher cost, thereby greatly limiting the application range thereof. The fan-out packaging technology provides a good platform for realizing integrated packaging of multiple chips by adopting a mode of reconstructing wafers and rewiring RDL (remote desktop language), but the existing fan-out packaging technology has the problems of large area, high thickness and the like of a packaging body due to limited wiring precision, and various working procedures and low reliability.

In order to adapt to the development trend of multiple functions, miniaturization, portability, high speed, low power consumption and high reliability of the microelectronic packaging technology, a system-In-package (SIP) technology is used as a new heterogeneous integration technology and becomes a packaging form of more and more chips, and the system-In-package integrates various functional chips and components In one package, so that a complete function is realized. The system-in-package is a novel packaging technology and has the advantages of short development period, more functions, lower power consumption, better performance, lower cost price, smaller volume, light weight and the like.

However, with the increasing demands for package components and functions, the conventional system-in-package occupies an increasing area and thickness, which is not favorable for increasing the integration level.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a fan-out type system-in-package structure and a manufacturing method thereof, for solving the problem that the volume of the system-in-package is difficult to be reduced in the prior art.

To achieve the above and other related objects, the present invention provides a fan-out system-in-package structure, which includes: a rewiring layer including a first side and an opposing second side; a metal connection post formed on a second surface of the rewiring layer, the metal connection post being electrically connected to the rewiring layer; the system level chip and the power management chip are jointed on the second surface of the rewiring layer so as to realize the electrical connection with the rewiring layer; the packaging layer covers the metal connecting column, the system-level chip and the power management chip, and the metal connecting column is exposed out of the packaging layer; the connecting wiring layer is formed on the packaging layer and is electrically connected with the metal connecting column; the metal bump is formed on the first surface of the rewiring layer so as to realize the electrical leading-out of the rewiring layer; and the memory chip and the passive component are jointed with the connecting wiring layer to realize the electrical connection with the connecting wiring layer.

Optionally, the rerouting layer comprises: a first dielectric layer; the first graphical metal wiring layer is positioned on the first dielectric layer; the second dielectric layer is provided with a graphical through hole and is positioned on the first metal wiring layer; and the graphical second metal wiring layer is positioned on the second dielectric layer.

Optionally, the first dielectric layer has a window therein, the window exposes the first wiring metal layer, and the metal bump is formed in the window.

Optionally, the dielectric layer is made of one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the metal wiring layer is made of one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium

Optionally, the material of the metal connection column comprises one of Au, Ag, Cu, and Al.

Optionally, the memory chip includes an ePoP memory.

Optionally, the passive component includes a plurality of passive elements, and the passive elements include one of a resistor, a capacitor, and an inductor.

Optionally, the metal bump comprises one of a tin solder, a silver solder, and a gold-tin alloy solder.

Optionally, the thickness of the top surface of the package layer beyond the top surfaces of the system-on-chip and the power management chip is 0 to 10 micrometers

Optionally, the thickness of the fan-out system-in-package structure is not greater than 1 mm.

The utility model also provides a manufacturing method of fan-out type system in package structure, including the step: 1) providing a supporting substrate, and forming a separation layer on the supporting substrate; 2) forming a rewiring layer on the separation layer, wherein the rewiring layer comprises a first surface connected with the separation layer and an opposite second surface; 3) manufacturing a metal connecting column on the second surface of the rewiring layer, wherein the metal connecting column is electrically connected with the rewiring layer; 4) providing a system-level chip and a power management chip, and bonding the system-level chip and the power management chip on the second surface of the rewiring layer to realize the electrical connection with the rewiring layer; 5) packaging the metal connecting column, the system-level chip and the power management chip by adopting a packaging layer, and thinning the packaging layer to enable the metal connecting column to be exposed out of the packaging layer; 6) forming a connecting wiring layer on the packaging layer, wherein the connecting wiring layer is electrically connected with the metal connecting column; 7) providing a temporary base, and adhering the connecting wiring layer to the temporary substrate; 8) peeling the rewiring layer and the support substrate based on the separation layer to expose a first surface of the rewiring layer; 9) forming a metal bump on the first surface of the rewiring layer to realize the electrical leading-out of the rewiring layer; 10) stripping the temporary substrate to expose the connection wiring layer; 11) and providing a memory chip and a passive component, and jointing the memory chip and the passive component to the connecting wiring layer so as to realize the electrical connection with the connecting wiring layer.

Optionally, the support base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, and the temporary base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.

Optionally, the separation layer includes a light-to-heat conversion layer, and step 8) irradiates the light-to-heat conversion layer with laser light to separate the light-to-heat conversion layer from the rewiring layer and the supporting substrate, thereby peeling the rewiring layer and the supporting substrate.

Optionally, the step 2) of fabricating the redistribution layer includes the steps of: 2-1) forming a first dielectric layer on the surface of the separation layer; 2-2) forming a first metal layer on the surface of the first dielectric layer by adopting a sputtering process, and etching the metal layer to form a patterned first metal wiring layer; 2-3) forming a second dielectric layer on the surface of the patterned first metal wiring layer, and etching the second dielectric layer to form a second dielectric layer with a patterned through hole; and 2-4) filling the conductive plugs in the patterned through holes, then forming a second metal layer on the surface of the second dielectric layer by adopting a sputtering process, and etching the metal layer to form a patterned second metal wiring layer.

Optionally, the dielectric layer is made of one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the metal wiring layer is made of one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

Optionally, in step 9), a window is formed in the first dielectric layer by using laser, the window exposes the first wiring metal layer, and then the metal bump is fabricated in the window.

Optionally, the method for forming the encapsulation layer includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the encapsulation layer includes one of polyimide, silicone and epoxy resin.

Optionally, in step 3), the metal connection column is manufactured on the second surface of the redistribution layer by using a wire bonding process.

Optionally, step 4) bonds the system-on-chip and the power management chip to the second surface of the redistribution layer using metal solder, and then fills an underfill layer between the system-on-chip and the redistribution layer and between the power management chip and the redistribution layer.

Optionally, after the step 5) of thinning the package layer, the thickness of the top surface of the package layer beyond the top surfaces of the system-on-chip and the power management chip is 0 to 10 micrometers.

Optionally, step 10) first adheres the first surface of the rewiring layer to an adhesive film, and then peels off the temporary substrate to expose the connecting wiring layer.

Optionally, in step 11), the memory chip is bonded to the connection wiring layer by using a die attach process, the passive component is bonded to the connection wiring layer by using a surface mount process, and then an isolation protection layer is formed between the memory chip and the connection wiring layer by using a dispensing process.

As described above, the fan-out system-in-package structure and the manufacturing method thereof of the present invention have the following advantages:

the utility model discloses a fan-out type system in package is with the chip of multiple functions, integrate in a packaging structure including system in chip, power management chip, memory chip and passive subassembly etc. can realize the system function demand of multiple difference, improve packaging system's performance.

The utility model discloses a rewiring layer and metal connecting post have realized that system level chip, power management chip, memory chip and passive subassembly's three-dimensional pile up the encapsulation perpendicularly, effectively reduce packaging system's area, improve packaging system's integrated level.

The utility model discloses a metal connecting post realizes the zonulae occludens between the wiring layer, can effectively short the conduction route between the chip, reduces packaging system's consumption.

The utility model discloses a fan-out type system in package structure can realize the encapsulation thickness below 1 millimeter, compares in traditional SiP packaging structure, greatly reduced packaging system's whole thickness.

Drawings

Fig. 1 to 20 are schematic structural diagrams of steps of a manufacturing method of a fan-out system-in-package structure according to the present invention, in which fig. 19 is a schematic sectional structure diagram of the fan-out system-in-package structure of this embodiment, and fig. 20 is a schematic plan layout diagram of the fan-out system-in-package structure of this embodiment.

Description of the element reference numerals

101 supporting substrate

102 separating layers

103 temporary substrate

104 window

105 metal bump

106 film

20 rewiring layer

201 first dielectric layer

202 first metal routing layer

203 second dielectric layer

204 second metal routing layer

205 third dielectric layer

206 third metal routing layer

207 fourth dielectric layer

208 fourth Metal routing layer

301 metal connection post

401 system on chip

402 power management chip

403 underfill layer

404 memory chip

405 passive component

406 isolation protection layer

501 encapsulation layer

60 connecting wiring layers

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

The embodiment provides a manufacturing method of a fan-out system-in-package structure, which includes the steps of:

as shown in fig. 1, step 1) is performed to provide a supporting substrate 101, and a separation layer 102 is formed on the supporting substrate 101.

The support base 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, as an example. In this embodiment, the supporting substrate 101 is a glass substrate, which has a low cost, is easy to form the separation layer 102 on the surface thereof, and can reduce the difficulty of the subsequent stripping process.

As an example, the separation layer 102 includes a light-to-heat conversion Layer (LTHC), and is formed on the supporting substrate 101 by a spin coating process and then cured by a curing process. The light-heat conversion Layer (LTHC) has stable performance and smooth surface, is beneficial to the subsequent manufacture of a rewiring layer, and has lower stripping difficulty in the subsequent stripping process.

As shown in fig. 2 to 3, step 2) is then performed to form a redistribution layer on the separation layer 102, where the redistribution layer includes a first surface connected to the separation layer 102 and an opposite second surface.

Step 2) manufacturing the rewiring layer 20 includes the steps of:

as shown in fig. 2, performing step 2-1), forming a first dielectric layer 201 on the surface of the separation layer 102 by using a chemical vapor deposition process or a physical vapor deposition process, where the material of the first dielectric layer 201 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

Preferably, the material of the first dielectric layer 201 is PI (polyimide), so as to further reduce the process difficulty and the process cost.

As shown in fig. 3, step 2-2) is performed, a sputtering process is used to form a first metal layer on the surface of the first dielectric layer 201, and the metal layer is etched to form a patterned first metal wiring layer 202. The material of the first metal wiring layer 202 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

As shown in fig. 3, performing step 2-3), forming a second dielectric layer 203 on the surface of the patterned first metal wiring layer 202 by using a chemical vapor deposition process or a physical vapor deposition process, and etching the second dielectric layer 203 to form the second dielectric layer 203 with patterned through holes. The material of the second dielectric layer 203 includes one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass.

Preferably, the material of the second dielectric layer 203 is PI (polyimide), so as to further reduce the process difficulty and the process cost.

As shown in fig. 3, performing steps 2-4), filling conductive plugs into the patterned through holes, then forming a second metal layer on the surface of the second dielectric layer 203 by using a sputtering process, and etching the metal layer to form a patterned second metal wiring layer 204. The material of the second metal wiring layer 204 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

Next, as shown in fig. 3, the above steps 2-3) to 2-4) may be repeated to form a redistribution layer having a multi-layer stacked structure, so as to implement different routing functions, for example, in this embodiment, the redistribution layer 20 further includes a patterned third dielectric layer 205, a patterned third metal routing layer 206, a patterned fourth dielectric layer 207, and a patterned fourth metal routing layer 208.

As shown in fig. 4, step 3) is then performed to fabricate a metal connection stud 301 on the second surface of the redistribution layer 20, wherein the metal connection stud 301 is electrically connected to the redistribution layer 20.

For example, in this embodiment, a wire bonding process may be used to fabricate the metal connecting stud 301 on the second surface of the redistribution layer 20, the metal connecting stud 301 may be perpendicular to the redistribution layer 20 to shorten the conductive path, the metal connecting stud 301 is one of Au, Ag, Cu, and Al, and in this embodiment, the metal connecting stud 301 may be copper to improve the stability and reduce the impedance.

As shown in fig. 5 to fig. 6, step 4) is performed to provide a system-on-chip 401 and a power management chip 402, and the system-on-chip 401 and the power management chip 402 are bonded to the second surface of the redistribution layer 20 to electrically connect to the redistribution layer 20, where the system-on-chip 401 and the power management chip 402 are interconnected through the redistribution layer 20.

For example, the system-on-chip 401 may be a GPU chip for a mobile phone, tablet, or other smart device, and the like.

In this embodiment, the soc 401 and the power management chip 402 are bonded to the second surface of the redistribution layer 20 by using metal solder, as shown in fig. 5, and then an underfill layer 403 is filled between the soc 401 and the redistribution layer 20 and between the power management chip 402 and the redistribution layer 20, for example, a dispensing process may be used to form the underfill layer 403, as shown in fig. 6, the underfill layer 403 may provide protection for the joints between the soc 401 and the power management chip 402 and the redistribution layer 20, so as to prevent corrosion or connection damage, and on the other hand, may improve the adhesion performance between the soc 401 and the power management chip 402 and the redistribution layer 20, and improve the mechanical strength.

As shown in fig. 7 to 8, step 5) is performed, the metal connection studs 301, the soc 401 and the power management chip 402 are packaged by a package layer 501, and the package layer 501 is thinned to expose the metal connection studs 301 to the package layer 501.

For example, the formation method of the encapsulation layer 501 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the encapsulation layer 501 includes one of polyimide, silicone, and epoxy resin.

In order to reduce the thickness of the package structure, after the package layer 501 is thinned, the thickness of the top surface of the package layer 501 beyond the top surfaces of the system on chip 401 and the power management chip 402 is between 0 micron and 10 microns, for example, the thickness may be 3 microns or 5 microns, and the like.

As shown in fig. 9, step 6) is then performed to form a connecting wiring layer 60 on the package layer 501, wherein the connecting wiring layer 60 is electrically connected to the metal connection stud 301.

Specifically, the method comprises the following steps: forming a dielectric layer on the surface of the packaging layer 501, patterning the dielectric layer to form a through hole exposing the metal connecting column 301, then forming a metal layer on the through hole and the surface of the dielectric layer, and performing patterning processing on the metal layer to form a metal interconnection structure so as to form the connection wiring layer 60. Of course, according to different requirements, a multilayer wiring structure of multiple dielectric layers and multiple metal layers can be formed, and the structure is not limited to the above-mentioned examples.

As shown in fig. 10, step 7) is then performed to provide a temporary base 103, and the connecting wiring layer 60 is adhered to the temporary substrate. For example, the temporary base 103 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.

As shown in fig. 11, step 8) is performed next, in which the redistribution layer 20 and the supporting substrate 101 are peeled off based on the separation layer 102, and the first surface of the redistribution layer 20 is exposed.

In the present embodiment, the photothermal conversion layer is irradiated with laser light to separate the photothermal conversion layer from the redistribution layer 20 and the supporting substrate 101, thereby peeling the redistribution layer 20 and the supporting substrate 101.

As shown in fig. 12 to 13, step 9) is then performed to form a metal bump 105 on the first surface of the redistribution layer, so as to achieve electrical extraction of the redistribution layer.

In this embodiment, a window 104 is formed in the first dielectric layer 201 by using laser, the window 104 exposes the first wiring metal layer, as shown in fig. 12, and then the metal bump 105 is fabricated in the window 104, as shown in fig. 13. For example, the metal bump 105 may be one of a tin solder, a silver solder, and a gold-tin alloy solder.

As shown in fig. 14 and 15, step 10) is then performed to strip the temporary substrate 103 to expose the connection wiring layer 60.

Specifically, the first side of the redistribution layer may be adhered to an adhesive film 106, and then the temporary substrate 103 may be peeled off to expose the connection wiring layer 60.

As shown in fig. 16 to fig. 20, step 11) is finally performed to provide a memory chip 404 and a passive component 405, and the memory chip 404 and the passive component 405 are bonded to the connecting wiring layer 60 to achieve electrical connection with the connecting wiring layer 60.

For example, the memory chip 404 may be bonded to the connecting wiring layer 60 by a die bonding process, as shown in fig. 16, the passive component 405 may be bonded to the connecting wiring layer 60 by a surface mount process, as shown in fig. 17, and then the isolation protection layer 406 may be formed on the memory chip 404 and the connecting wiring layer 60 by a dispensing process, as shown in fig. 18.

In this embodiment, the passive component 405 includes a plurality of passive elements, which may be arranged in a parallel array, as shown in fig. 20, and the passive elements may be one of a resistor, a capacitor, and an inductor.

Finally, the formed package structure is cut, and then the adhesive film 106 is peeled off to form the fan-out type system-in-package structure, as shown in fig. 19, the system-in-chip 401, the power management chip 402, the memory chip 404 and the passive component 405 are interconnected through the redistribution layer 20, the connection wiring layer 60 and the metal connection post 301, and fan-out type packaging is realized through the metal bump 105.

Fig. 19 is a schematic cross-sectional structure diagram of the fan-out system-in-package structure of this embodiment, and fig. 20 is a schematic plan layout diagram of the fan-out system-in-package structure of this embodiment, as shown in fig. 19 to fig. 20, in a specific implementation process, an overall size (length × width) of the fan-out system-in-package structure may be 13mm × 16mm, a total height is 1mm, a size (length × width) of the SOC 401 may be 8.2 × 8.3mm, a size of the PMU of the power management chip 402 may be 5.1mm × 4.8mm, a distance between the SOC 401 and the power management chip 402 is 0.5mm, and a thickness of the memory chip 404 is 0.68 mm.

The utility model discloses a fan-out type system in package is with the chip of multiple functions, including system in chip 401, power management chip 402, memory chip 404 and passive subassembly 405 etc. integration in a packaging structure, can realize the system function demand of multiple difference, improve packaging system's performance. The utility model discloses a rewiring layer and metal connecting post 301 have realized that system level chip 401, power management chip 402, memory chip 404 and passive subassembly 405's three-dimensional vertical pile up the encapsulation, effectively reduce packaging system's area, improve packaging system's integrated level. The utility model discloses a metal connecting post 301 realizes the zonulae occludens between the rewiring layer, can effectively short the conduction path between the chip, reduces packaging system's consumption. The utility model discloses a fan-out type system in package structure can realize the encapsulation thickness below 1 millimeter, compares in traditional SiP packaging structure, greatly reduced packaging system's whole thickness.

As shown in fig. 19 and fig. 20, the present embodiment further provides a fan-out system-in-package structure, where the package structure includes: a rewiring layer 20, the rewiring layer 20 including a first side and an opposing second side; a metal connection stud 301 formed on a second side of the redistribution layer 20, the metal connection stud 301 being electrically connected to the redistribution layer 20; a system-on-chip 401 and a power management chip 402, where the system-on-chip 401 and the power management chip 402 are bonded to a second surface of the redistribution layer 20 to electrically connect to the redistribution layer 20; a package layer 501 covering the metal connection stud 301, the soc 401 and the power management chip 402, and the metal connection stud 301 is exposed from the package layer 501; a connecting wiring layer 60 formed on the package layer 501, the connecting wiring layer 60 being electrically connected to the metal connecting stud 301; a metal bump 105 formed on a first surface of the redistribution layer to electrically extract the redistribution layer; the memory chip 404 and the passive component 405 are bonded to the connecting wiring layer 60 to electrically connect with the connecting wiring layer 60.

The re-wiring layer 20 includes: a first dielectric layer 201; a patterned first metal wiring layer 202 on the first dielectric layer 201; a second dielectric layer 203 with patterned vias, located on the first metal wiring layer 202; and the patterned second metal wiring layer 204 is positioned on the second dielectric layer 203. The dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the first dielectric layer 201 and the second dielectric layer 203 are made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The re-routing layer 20 may also include more dielectric layers and metal layers to achieve different routing functions. For example, in this embodiment, the redistribution layer 20 further includes a patterned third dielectric layer 205, a patterned third metal wiring layer 206, a patterned fourth dielectric layer 207, and a patterned fourth metal wiring layer 208.

The first dielectric layer 201 has a window 104 therein, the window 104 exposes the first wiring metal layer, and the metal bump 105 is formed in the window 104.

The metal connection stud 301 may be perpendicular to the redistribution layer 20 to shorten a conduction path, the metal connection stud 301 is one of Au, Ag, Cu, and Al, and in this embodiment, the metal connection stud 301 may be copper to improve stability and reduce impedance.

The system-on-chip 401 may be a GPU chip for a mobile phone, tablet, or other smart device, etc. The memory chip 404 includes an ePoP memory. An isolation protection layer 406 is also provided between the memory chip 404 and the connecting wiring layer 60.

An underfill layer 403 is further disposed between the system-on-chip 401 and the redistribution layer 20 and between the power management chip 402 and the redistribution layer 20, and the underfill layer 403 can protect the joints between the system-on-chip 401 and the power management chip 402 and the redistribution layer 20 to prevent corrosion or connection damage, and can improve the adhesion between the system-on-chip 401 and the power management chip 402 and the redistribution layer 20 to improve the mechanical strength.

As shown in fig. 20, the passive component 405 includes a plurality of passive elements, and the passive elements include one of a resistor, a capacitor, and an inductor.

The material of the encapsulation layer 501 includes one of polyimide, silicone, and epoxy resin. The thickness of the top surface of the package layer 501 beyond the top surfaces of the system-on-chip 401 and the power management chip 402 is 0 to 10 micrometers. For example, the thickness may be 3 microns or 5 microns, etc., and of course, in order to further reduce the thickness of the package structure, the thickness may also be set to 0 micron, i.e., the top surface of the package layer 501 is flush with the top surfaces of the system-on-chip 401 and the power management chip 402.

The metal bump 105 includes one of a tin solder, a silver solder, and a gold-tin alloy solder.

The thickness of the fan-out type system-in-package structure is not more than 1 millimeter.

Fig. 19 is a schematic cross-sectional structure diagram of the fan-out system-in-package structure of this embodiment, and fig. 20 is a schematic plan layout diagram of the fan-out system-in-package structure of this embodiment, as shown in fig. 19 to fig. 20, in a specific implementation process, the overall size (length × width) of the fan-out system-in-package structure may be 13mm × 16mm, the total height is 1mm, the size (length × width) of the system-on-chip 401 may be 8.2 × 8.3mm, the size of the power management chip 402 may be 5.1mm × 4.8mm, a distance between the system-on-chip 401 and the power management chip 402 is 0.5mm, and the thickness of the memory chip 404 is 0.68 mm.

Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A fan-out system-in-package structure, the package structure comprising:

a rewiring layer including a first side and an opposing second side;

a metal connection post formed on a second surface of the rewiring layer, the metal connection post being electrically connected to the rewiring layer;

the system level chip and the power management chip are jointed on the second surface of the rewiring layer so as to realize the electrical connection with the rewiring layer;

the packaging layer covers the metal connecting column, the system-level chip and the power management chip, and the metal connecting column is exposed out of the packaging layer;

the connecting wiring layer is formed on the packaging layer and is electrically connected with the metal connecting column;

the metal bump is formed on the first surface of the rewiring layer so as to realize the electrical leading-out of the rewiring layer;

and the memory chip and the passive component are jointed with the connecting wiring layer to realize the electrical connection with the connecting wiring layer.

2. The fan-out system-in-package structure of claim 1, wherein: the re-routing layer includes:

a first dielectric layer;

the first graphical metal wiring layer is positioned on the first dielectric layer;

the second dielectric layer is provided with a graphical through hole and is positioned on the first metal wiring layer;

and the graphical second metal wiring layer is positioned on the second dielectric layer.

3. The fan-out system-in-package structure of claim 2, wherein: the first dielectric layer is provided with a window, the window exposes the first metal wiring layer, and the metal bump is manufactured in the window.

4. The fan-out system-in-package structure of claim 2, wherein: the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.

5. The fan-out system-in-package structure of claim 1, wherein: the metal connecting column is made of one of Au, Ag, Cu and Al.

6. The fan-out system-in-package structure of claim 1, wherein: the memory chip comprises an ePoP memory.

7. The fan-out system-in-package structure of claim 1, wherein: the passive component comprises a plurality of passive elements, and the passive elements comprise one of resistors, capacitors and inductors.

8. The fan-out system-in-package structure of claim 1, wherein: the thickness of the top surface of the packaging layer beyond the top surfaces of the system level chip and the power management chip is 0-10 microns.

9. The fan-out system-in-package structure of claim 1, wherein: the thickness of the fan-out type system-in-package structure is not more than 1 millimeter.