CN112014713B - Wafer electrical property test method and test equipment - Google Patents
Wafer electrical property test method and test equipment Download PDFInfo
- Publication number
- CN112014713B CN112014713B CN202011121614.7A CN202011121614A CN112014713B CN 112014713 B CN112014713 B CN 112014713B CN 202011121614 A CN202011121614 A CN 202011121614A CN 112014713 B CN112014713 B CN 112014713B
- Authority
- CN
- China
- Prior art keywords
- test
- electrical
- wafer
- position area
- item
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2648—Characterising semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a wafer electrical property test method and test equipment, defining the passing condition of each electrical property test item in an initial test parameter, then sequentially testing a plurality of position areas on a wafer, and judging whether the test result of the electrical property test item on the position area meets the passing condition or not when testing an electrical property test item on one position area; if the test result does not meet the preset passing condition, the electrical property test item is immediately retested, and if the passing condition is met or the retesting frequency reaches the preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started. The method can be used for testing the electrical property of the wafer, and can be used for effectively solving the problem of hysteresis of wafer electrical property test judgment, greatly shortening the retesting time of the electrical property test NG wafer, and effectively removing the abnormal jump point value of the electrical property test, thereby obviously improving the stability and the anti-interference capability of the test.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a wafer electrical property testing method and testing equipment.
Background
During the wafer processing, the electrical characteristics of the wafer may be abnormal due to various reasons (such as incomplete lithography, excessive corrosion, etc.). Therefore, electrical testing after wafer processing is a very important link, and the functions of wafer electrical testing mainly include: and screening out the wafers with unqualified electrical performance, and monitoring the electrical parameters of the wafer devices so as to maintain and improve the level of the process technology.
When a wafer is tested on a testing device, poor testing may be caused by external reasons, for example, a good wafer may be tested as a poor wafer due to a dirty tip of a probe card (adhering dust, adhering a plating layer on a wafer pad, etc.) or a too light pressure of the probe card or a positional deviation of the probe card during a first test.
The test flow of the conventional wafer electrical property test method comprises the following steps: after the electrical test of the whole batch of wafers is finished, the electrical test result is uploaded to a judging system, whether an electrical test NG item exists is judged through the judging system, and if the electrical test NG item exists, the wafer where the NG item is located is retested.
When the conventional wafer electrical property testing method is used for testing, the problems of data judgment lag, retest time consumption and the like exist, so that the improvement of the wafer electrical property testing method, the improvement of the wafer electrical property testing efficiency and the optimization of the wafer electrical property testing process have very remarkable practical significance.
Disclosure of Invention
The present invention is directed to a wafer electrical testing method and apparatus, which solves one or more problems of the prior art.
To solve the above technical problems, the present invention provides a wafer electrical testing method, comprising:
defining initial test parameters, wherein the initial test parameters comprise passing conditions of all the electrical test items;
sequentially testing a plurality of position areas on a wafer, and judging whether the test result of an electrical test item on one position area meets the passing condition or not when the electrical test item on the position area is tested;
if the test result does not meet the requirement, the electrical property test item is retested in real time, and if the passing condition is met or the retesting frequency reaches a preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started;
if yes, starting the test of the next electrical test item of the position area or starting the test of the next position area.
Optionally, in the wafer electrical property testing method, the passing condition is a numerical range defined by an upper threshold and a lower threshold; and when judging whether the test result meets the passing condition or not, if the test value is in the numerical range, judging that the test is passed.
Optionally, in the wafer electrical test method, the value range of each electrical test item is defined according to a wafer compliance standard, and the defined value range of each electrical test item is the same as the value range of the wafer compliance standard.
Optionally, in the wafer electrical test method, the value range of each electrical test item is defined according to an electrical test item stability standard, and the defined value range of each electrical test item is within a value range of a wafer compliance standard.
Optionally, in the wafer electrical testing method, after the testing of all the position areas is completed, the wafer electrical testing method further includes: and uploading the last test result of each electrical test item of each position area of the wafer to a judgment system so that the judgment system judges whether the wafer is in compliance.
Optionally, in the wafer electrical testing method, the wafer electrical testing method further includes:
and starting the test of the next position area after all the electrical test items on the same position area are tested.
The invention also provides a test device, which comprises a processor and a memory, wherein the memory is stored with an electrical property test algorithm and initial test parameters, the initial test parameters comprise passing conditions of each electrical property test item, and when the electrical property test algorithm is executed by the processor, the following steps are realized:
sequentially testing a plurality of position areas on a wafer, and judging whether the test result of an electrical test item on one position area meets the passing condition or not when the electrical test item on the position area is tested;
if the test result does not meet the requirement, the electrical property test item is retested in real time, and if the passing condition is met or the retesting frequency reaches a preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started;
if yes, starting the test of the next electrical test item of the position area or starting the test of the next position area.
Optionally, in the test apparatus, a numerical range of the passing condition of each of the electrical test items is the same as a value range of a wafer compliance standard.
Optionally, in the test apparatus, a numerical range of the passing condition of each of the electrical test items is within a value range of a wafer compliance standard.
Optionally, in the test apparatus, when the electrical test algorithm is executed by the processor, the following steps are further implemented:
and uploading the last test result of each electrical test item of each position area of the wafer to a judgment system so that the judgment system judges whether the wafer is in compliance.
In summary, in the wafer electrical property testing method and the testing apparatus provided by the present invention, the passing condition of each electrical property test item is defined in the initial testing parameter, then, a plurality of position areas on the wafer are sequentially tested, and when an electrical property test item on a position area is tested, whether the testing result of the electrical property test item on the position area meets the passing condition is determined; if the test result does not meet the preset passing condition, the electrical property test item is immediately retested, and if the passing condition is met or the retesting frequency reaches the preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started. In addition, the abnormal jump point value of the electrical test can be effectively removed through the secondary test of the current NG item in the test process, so that the stability and the anti-interference capability of the test are obviously improved.
Drawings
Fig. 1 is a flowchart illustrating a wafer electrical testing method according to an embodiment of the present invention;
FIG. 2 is a statistical chart of the results of a wafer capacitance test using the prior art;
FIG. 3 is a statistical chart of the results of the wafer capacitance test performed by the wafer electrical property testing method according to the embodiment of the present invention;
FIG. 4 is a diagram illustrating the elimination of abnormal skip point values by narrowing the range of values according to a second embodiment of the present invention;
fig. 5 is a flowchart of a wafer testing method according to a second embodiment of the invention.
Detailed Description
The wafer electrical testing method and the testing apparatus according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
[ EXAMPLES one ]
As shown in fig. 1, the present embodiment provides a wafer electrical testing method, which includes the following steps:
s11, defining initial test parameters, wherein the initial test parameters comprise passing conditions of each electrical test item;
s12, sequentially testing a plurality of position areas on the wafer, judging whether the test result of an electrical test item on one position area meets the passing condition when testing the electrical test item on the position area, if not, executing a step S13, and if so, executing a step S14;
s13, retesting the electrical property test item immediately, if the passing condition is met or the retest frequency reaches a preset value after retesting, executing the step S14;
and S14, starting the test of the next electrical test item in the position area or starting the test of the next position area.
In the wafer electrical test method provided by this embodiment, the passing condition of the electrical test item is defined in the initial test parameter, the test data is determined in real time, and the single electrical test item in a certain position area of the wafer is retested in real time after NG, so that the hysteresis of the wafer electrical test data determination can be solved; when retesting, only need the NG item of retesting wafer test NG position, can shorten the time that electrical test NG wafer retested greatly, in addition, also through the secondary test of current NG item, can effectively get rid of electrical test's unusual trip point value to show stability and the interference killing feature who promotes the test.
Hereinafter, each of the above steps will be described in detail.
First, before the wafer test is started, step S11 is executed to define initial test parameters, which include passing conditions of each electrical test item.
When performing electrical testing on a wafer, initial testing parameters are generally defined, which are mainly settings of some electrical testing items, including threshold voltage, saturation current, leakage current, breakdown voltage, plate capacitance, contact resistance, and the like. On the basis, the wafer electrical test method provided by the embodiment also defines the passing condition of each electrical test item in the initial test parameters, so that the test data can be synchronously determined when the electrical test items are tested.
In this embodiment, the value range of each electrical test item is defined according to a wafer compliance standard, and the value range of each defined electrical test item is the same as the value range of the wafer compliance standard.
For a wafer, the wafer can be shipped only when the electrical test data of the wafer meets the compliance standard. Therefore, when the passing condition is set, the upper and lower limit thresholds of the passing condition of each electrical test item can be valued according to the upper and lower limit thresholds of the compliance standard. For example, for a certain electrical test item, the compliance criteria is that the test value should satisfy: greater than m, less than n, the pass condition for the electrical test item may be set to [ m, n ].
Then, step S12 and step S13 are executed to sequentially test the plurality of location areas on the wafer, and if a certain electrical test item in a certain location area does not satisfy the passing condition, the electrical test item is retested in real time.
When the wafer is subjected to an electrical test, a plurality of position areas (generally 9) need to be tested, and when the position areas of the wafer are divided, grid lines can be used for dividing, and on the basis, when the plurality of position areas on the wafer are sequentially tested, each position area can be sequentially tested in a row-by-row or row-by-row mode or a snake-shaped mode.
Each location area needs to test hundreds of electrical test items, and the contents of each location area are consistent. In the prior art, if a test item in an area does not meet the shipment standard or abnormal value, it is determined that the test item can be known only after the entire batch of wafers is tested. In this embodiment, when a certain electrical test item in a certain location area is tested, the test result is determined, and if NG is tested, the NG item in the location area is retested. For example, when the 5 th electrical test item in the 3 rd position area is tested, if the 5 th electrical test item is tested for NG, the 5 th electrical test item is retested in real time.
When the NG item is retested, if the passing condition or the retest frequency after retesting reaches a predetermined value, for example, 2 times, 3 times, 4 times, etc., step S14 is executed to start the test of the next electrical test item in the location area where the NG item is located, and if the NG item is the last electrical test item in the location area, the test of the next location area is started.
For example, if the 5 th electrical test item of the 3 rd position area passes or reaches the preset number, the test of the 6 th electrical test item of the 3 rd position area is started, and if each position area only has 5 electrical test items, the test of the 4 th position area is started after the 5 th electrical test item passes or reaches the preset number.
The wafer electrical testing method provided by the present embodiment will be described below by way of example.
For foundry wafers, MOS gate oxide process capability is one of the key factors that determine foundry water. The wafer electrical test can monitor the thickness of the gate oxide layer by testing the capacitance of the gate oxide layer. The capacitance test item is subject to interference of ambient noise and fails due to the measurement using alternating current. Therefore, when the wafer electrical property testing method provided by the embodiment is implemented, the passing condition of the capacitance test can be defined in the initial testing parameters, for example, CSiO2_usl=a，CSiO2_lsl=b。
And then adding a function of 'immediate judgment of capacitance test data' into the capacitance test algorithm. And if the capacitance value is smaller than the upper limit a and larger than the lower limit b, starting the next electrical property test item test, and if the capacitance value is larger than the upper limit a or smaller than the lower limit b, retesting the capacitance item in real time until the capacitance value meets the set condition or the number of retesting times reaches a set value n, and starting the next electrical property test item test.
As shown in fig. 2, with the current measurement method, since the capacitance of the single position area site (shown as the 7 th position area) on the wafer exceeds the upper limit a, all the electrical items of the wafer need to be retested subsequently, while as shown in fig. 3, with the method provided in this embodiment, if the capacitance test of the single position area site (shown as the 7 th position area) fails during the test process, the capacitance item of the position area can be retested immediately.
Assuming that the electrical test of a single wafer takes about 30min, the capacitance test of a single site area takes about 1.5s, and a lot of samples contains 25 wafers.
For a single wafer, by adopting the existing testing method, due to the failure of the capacitance value test of the single position area of the wafer, all the electrical items of the whole wafer are required to be retested subsequently, and the total consumed time T1=30 × 2=60 min; by adopting the method provided by the embodiment, after the capacitance value test of the single position area of the wafer fails, the capacitance value of the position area is immediately retested, so that the total consumed time T2=30+0.025=30.025 min. In comparison, the wafer electrical testing method provided in this embodiment improves the single wafer testing efficiency by 49.9% compared with the conventional testing method.
For a batch of wafers, the conventional test method is adopted, and because the capacitance test of the single position area of the wafer fails, all the electrical items of the whole wafer are required to be retested subsequently, so that the total consumed time T is counted3=30 × 26=780 min; by adopting the method of the embodiment of the invention, after the capacitance value test of the single position area of the wafer fails, the capacitance value of the position area can be immediately retested, so the total consumed time T is4=30 × 25+0.025=750.025 min. In comparison, the wafer electrical testing method provided in this embodiment improves the testing efficiency of the whole batch of wafers by 3.8% compared with the conventional testing method.
In addition, the present embodiment further provides a testing apparatus, which includes a processor and a memory, where the memory stores an electrical property testing algorithm and initial testing parameters, the initial testing parameters include passing conditions of each electrical property testing item, and the electrical property testing algorithm implements the steps S12 to S14 when executed by the processor.
Corresponding to the wafer electrical testing method provided in this embodiment, in the testing apparatus provided in this embodiment, a numerical range of the passing condition of each electrical testing item is within a value range of a wafer compliance standard.
In the test device provided in this embodiment, the Memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), for example, at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
[ example two ]
As shown in fig. 4, when a wafer test is performed, due to interference from objective factors (for example, a foreign object is stuck on a test probe), abnormal jumping points may occur in a test result, and although some abnormal jumping point values are also within the compliance standard, they are not favorable for presenting stability of the test result, so as to interfere with determination of the abnormal condition of the wafer test.
Therefore, in this embodiment, different from the first embodiment, when the passing condition of each electrical test item is set, the value range of each electrical test item is defined according to the electrical test item stability standard, and the defined value range of each electrical test item is within the value range of the wafer compliance standard.
Referring to fig. 4, for the resistance test item, if the value range of the wafer compliance standard is [ b, a ], the value range can be reduced to [ d, c ] when the passing condition of the resistance test item is set, so that when some abnormal trip point values occur in the resistance test, the resistance test item is retested in real time to remove the abnormal trip point values, thereby improving the stability and the anti-interference capability of the test.
For any electrical test item, although the abnormal jumping point can be effectively removed by reducing the value range of the wafer compliance standard as the passing condition of the electrical test item, some compliant wafers may be determined as non-compliant wafers. Therefore, in this embodiment, after the testing of all the position areas is completed, the last testing result of each electrical test item of each position area of the wafer is uploaded to the determination system, so that the determination system determines whether the wafer is in compliance.
When some wafers have testing NG items, the wafers can be judged to be qualified as not good products although testing NG is judged to be qualified through further judgment of the judging system, and the wafers are in compliance and accord with the delivery standard.
Specifically, as shown in fig. 5, the wafer electrical testing method provided in the present embodiment may include the following steps:
s21, defining initial test parameters, wherein the initial test parameters comprise passing conditions of each electrical test item;
s22, sequentially testing a plurality of position areas on the wafer, judging whether the test result of an electrical test item on one position area meets the passing condition when testing the electrical test item on the position area, if not, executing a step S23, and if so, executing a step S24;
s23, retesting the electrical property test item immediately, if the passing condition is met or the retest frequency reaches a preset value after retesting, executing the step S24;
s24, starting the test of the next electrical test item in the position area or starting the test of the next position area;
s25, uploading the last test result of each electrical test item in each position area of the wafer to a determination system, so that the determination system determines whether the wafer is compliant.
In the step S21, the value range of each electrical test item is defined according to the electrical test item stability standard, and the defined value range of each electrical test item is within the value range of the wafer compliance standard.
In this embodiment, the steps S22 to S24 are the same as the steps S12 to S14 in the first embodiment, and are not repeated herein.
Similarly, the present embodiment also provides a testing apparatus, which includes a processor and a memory, wherein the memory stores an electrical property testing algorithm and initial testing parameters, the initial testing parameters include passing conditions of each electrical property testing item, and the electrical property testing algorithm implements the steps S22-S24 when being executed by the processor.
Corresponding to the wafer electrical testing method provided in this embodiment, in the testing apparatus provided in this embodiment, the numerical range of the passing condition of each electrical test item is within the value range of the wafer compliance standard, and when the electrical testing algorithm is executed by the processor, the step S25 is further implemented. For the description of the processor and the memory, please refer to embodiment one, which is not described herein again.
In summary, the wafer electrical test method and the test apparatus provided by the present invention define the passing condition of each electrical test item in the initial test parameter, then sequentially test a plurality of position areas on the wafer, and when testing an electrical test item on a position area, determine whether the test result of the electrical test item on the position area satisfies the passing condition; if the test result does not meet the preset passing condition, the electrical property test item is immediately retested, and if the passing condition is met or the retesting frequency reaches the preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started. In addition, the abnormal jump point value of the electrical test can be effectively removed through the secondary test of the current NG item in the test process, so that the stability and the anti-interference capability of the test are obviously improved.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A wafer electrical property testing method is characterized by comprising the following steps:
defining the passing condition of each electrical test item in the initial test parameters, and defining the immediate judgment function of the test data in the electrical test algorithm, so that the test data is judged synchronously when the test of each electrical test item is carried out;
executing the electrical test algorithm on a wafer to sequentially test a plurality of position areas on the wafer, wherein when an electrical test item on one position area is tested, whether the test result of the electrical test item on the position area meets the passing condition is synchronously judged;
if the test result does not meet the requirement, the electrical property test item is retested in real time, and if the passing condition is met or the retesting frequency reaches a preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started;
if yes, starting the test of the next electrical test item of the position area or starting the test of the next position area.
2. The wafer electrical property testing method of claim 1, wherein the passing condition is a numerical range defined by an upper threshold and a lower threshold; and when judging whether the test result meets the passing condition or not, if the test value is in the numerical range, judging that the test is passed.
3. The wafer electrical testing method of claim 2, wherein the value range of each electrical test item is defined according to a wafer compliance standard, and the value range of each defined electrical test item is the same as the value range of the wafer compliance standard.
4. The wafer electrical testing method of claim 2, wherein the value range of each electrical test item is defined according to an electrical test item stability criterion, and the value range of each defined electrical test item is within a value range of a wafer compliance criterion.
5. The wafer electrical testing method of claim 4, wherein after the testing of all the location areas is completed, the wafer electrical testing method further comprises: and uploading the last test result of each electrical test item of each position area of the wafer to a judgment system so that the judgment system judges whether the wafer is in compliance.
6. The wafer electrical testing method of claim 1, further comprising:
and starting the test of the next position area after all the electrical test items on the same position area are tested.
7. A test apparatus comprising a processor and a memory, the memory having stored thereon an electrical test algorithm and initial test parameters, the initial test parameters including a pass condition for each electrical test item, the electrical test algorithm when executed by the processor implementing the steps of:
sequentially testing a plurality of position areas on a wafer, and judging whether the test result of an electrical test item on one position area meets the passing condition or not when the electrical test item on the position area is tested;
if the test result does not meet the requirement, the electrical property test item is retested in real time, and if the passing condition is met or the retesting frequency reaches a preset value after retesting, the test of the next electrical property test item in the position area is started or the test of the next position area is started;
if yes, starting the test of the next electrical test item of the position area or starting the test of the next position area.
8. The test apparatus of claim 7, wherein the pass condition of each of the electrical test items has a value range that is the same as a value range of a wafer compliance standard.
9. The test apparatus of claim 7, wherein the pass condition for each of the electrical test items has a range of values within a wafer compliance standard.
10. The test apparatus of claim 9, wherein the electrical test algorithm, when executed by the processor, further performs the steps of:
and uploading the last test result of each electrical test item of each position area of the wafer to a judgment system so that the judgment system judges whether the wafer is in compliance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011121614.7A CN112014713B (en) | 2020-10-20 | 2020-10-20 | Wafer electrical property test method and test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011121614.7A CN112014713B (en) | 2020-10-20 | 2020-10-20 | Wafer electrical property test method and test equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112014713A CN112014713A (en) | 2020-12-01 |
| CN112014713B true CN112014713B (en) | 2021-02-12 |
Family
ID=73527998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011121614.7A Active CN112014713B (en) | 2020-10-20 | 2020-10-20 | Wafer electrical property test method and test equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112014713B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118655377A (en) * | 2020-12-31 | 2024-09-17 | 杭州广立测试设备有限公司 | A method for testing capacitance data |
| CN114527366A (en) * | 2021-12-31 | 2022-05-24 | 杭州广立微电子股份有限公司 | WAT automatic retest method |
| CN117054802A (en) * | 2023-10-09 | 2023-11-14 | 四川辰宇微视科技有限公司 | Device and method for detecting electric performance of photoelectric cathode assembly |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104614656A (en) * | 2013-11-05 | 2015-05-13 | 京元电子股份有限公司 | Semiconductor chip retest system and retest method thereof |
| CN106597037A (en) * | 2015-10-20 | 2017-04-26 | 创意电子股份有限公司 | Probe card and test method |
| CN107976620A (en) * | 2017-11-20 | 2018-05-01 | 上海华力微电子有限公司 | A kind of crystal round test approach |
| CN111146103A (en) * | 2018-11-06 | 2020-05-12 | 长鑫存储技术有限公司 | Wafer detection method and detection equipment |
| CN111710618A (en) * | 2020-07-15 | 2020-09-25 | 广芯微电子（广州）股份有限公司 | Method for detecting defects of passivation layer of wafer |
-
2020
- 2020-10-20 CN CN202011121614.7A patent/CN112014713B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104614656A (en) * | 2013-11-05 | 2015-05-13 | 京元电子股份有限公司 | Semiconductor chip retest system and retest method thereof |
| CN106597037A (en) * | 2015-10-20 | 2017-04-26 | 创意电子股份有限公司 | Probe card and test method |
| CN107976620A (en) * | 2017-11-20 | 2018-05-01 | 上海华力微电子有限公司 | A kind of crystal round test approach |
| CN111146103A (en) * | 2018-11-06 | 2020-05-12 | 长鑫存储技术有限公司 | Wafer detection method and detection equipment |
| CN111710618A (en) * | 2020-07-15 | 2020-09-25 | 广芯微电子（广州）股份有限公司 | Method for detecting defects of passivation layer of wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112014713A (en) | 2020-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112014713B (en) | Wafer electrical property test method and test equipment | |
| US9529036B2 (en) | Systems and methods for test time outlier detection and correction in integrated circuit testing | |
| CN112180230B (en) | Chip test parameter abnormality detection method, storage medium, terminal | |
| Jandhyala et al. | Clustering based techniques for I/sub DDQ/testing | |
| CN105702595A (en) | Wafer yield judging method and wafer qualification test multivariable detection method | |
| JP6656984B2 (en) | Method for manufacturing semiconductor device | |
| CN110543730A (en) | A kind of transformer winding deformation fault judgment method | |
| US9081051B2 (en) | Methods for testing manufactured products | |
| JP7518180B2 (en) | Prediction of die susceptible to early life failures | |
| CN117881973A (en) | System and method for multidimensional dynamic part average testing | |
| WO2008081419A2 (en) | Systems and methods for test time outlier detection and correction in integrated circuit testing | |
| CN114002574A (en) | Test methods for semiconductor structures | |
| JP2008028271A (en) | Method of testing semiconductor integrated circuit device, and apparatus for inspecting the same | |
| KR100604929B1 (en) | Standby current test method of semiconductor package | |
| Streitwieser | Real-time adaptive test algorithm including test escape estimation method | |
| Ting et al. | An overkill detection system for improving the testing quality of semiconductor | |
| CN110749813B (en) | Test system and method for generating adaptive test recipe | |
| CN118839518A (en) | Metering appliance life prediction method, device, equipment and medium | |
| CN117538733A (en) | Method and system for determining chip production test threshold | |
| JP2012088246A (en) | Inspection control system, inspection method, and inspection control program | |
| CN112462233A (en) | Site control method and system in integrated circuit test | |
| Ooi et al. | Predictive die-level reliability-yield modeling for deep sub-micron devices | |
| CN115617592A (en) | Testing method and system of chip reliability testing device | |
| JP2004158770A (en) | Method of predicting yield of semiconductor device and method of managing yield | |
| Murthy et al. | Product Performance and Production |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |