CN111697050B - Semiconductor device and method for forming the same - Google Patents

Abstract

The present invention provides a semiconductor device and its forming method. The semiconductor device comprises a substrate having a first conductivity type, an epitaxial layer having a first conductivity type, and being arranged on the substrate, and a groove is provided in the epitaxial layer, and a first well region is arranged in the epitaxial layer. layer and below the trench, and has a second conductivity type different from the first conductivity type, the first gate electrode is disposed in the trench, and has the second conductivity type, and the second gate electrode is disposed in the trench and located above the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by the first insulating layer. The invention also provides a method for manufacturing the semiconductor device. The invention has few process steps, low cost and can reduce the element size.

Description

Semiconductor device and method of forming the same

technical field

Embodiments of the present invention relate to semiconductor technology, in particular to a metal oxide semiconductor field effect transistor (MOSFET) having a trench gate and a super junction structure and a method for forming the same.

Background technique

High-voltage component technology is applied to high-voltage and high-power integrated circuits. In order to achieve high withstand voltage and high current in traditional power transistors, the flow of driving current develops from a plane direction to a vertical direction. At present, a metal oxide semiconductor field effect transistor (MOSFET) with a trench gate and a super junction structure has been developed, which can increase the doping concentration of the n-type epitaxial drift doping region, thereby improving the on-resistance of the device.

Conventionally, a multi-epi technology is used to form a super-junction structure. The above-mentioned multi-epi technology requires multiple process cycles including epitaxy, p-type dopant implantation, and high-temperature diffusion. Therefore, the above-mentioned multi-layer epitaxy technology has disadvantages such as many process steps and high cost. Moreover, it is difficult to miniaturize the element size of the traditional vertical diffused MOSFET.

Therefore, it is necessary to find a metal-oxide-semiconductor field-effect transistor with a trench gate and a super-junction structure and a method for forming the same, which can solve or improve the above-mentioned problems.

Contents of the invention

In some embodiments, a semiconductor device is provided, which has fewer process steps, low cost, and can reduce the size of the element. The semiconductor device includes a substrate with a first conductivity type; an epitaxial layer with a first conductivity type is disposed on the substrate, and epitaxial There is a groove in the layer; the first well region is arranged in the epitaxial layer and below the groove, and has a second conductivity type different from the first conductivity type; the first gate electrode is arranged in the groove, and has a second conductivity type; and a second gate electrode disposed in the trench and above the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by the first insulating layer.

In some other embodiments, a method for forming a semiconductor device is provided, the method comprising providing a substrate having a first conductivity type; forming an epitaxial layer having the first conductivity type on the substrate; forming a trench in the epitaxial layer; forming a trench in the epitaxial layer A first well region with a second conductivity type is formed in and below the trench, wherein the second conductivity type is different from the first conductivity type; a first gate electrode with the second conductivity type is formed in the trench; and a first gate electrode with the second conductivity type is formed in the trench; A second gate electrode is formed in the groove and above the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by the first insulating layer.

In the embodiment of the present invention, by setting the first well region under the bottom of the trench by ion implantation process and thermal drive-in process, it is not necessary to perform multiple processes including epitaxy, implantation of p-type dopants, and high-temperature diffusion cycle. Therefore, the process for forming the first well region is simple, and expensive epitaxy costs are not required. Furthermore, since the first well region is located under the bottom of the trench, the first well region does not occupy extra space, so the cell pitch can be reduced, thereby reducing the resistance of the channel region.

Description of drawings

Embodiments of the present invention can be better understood according to the following detailed description and accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various features in the illustrations have not necessarily been drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of illustration.

1-15 are schematic cross-sectional views of various stages in a process of forming a semiconductor device according to some embodiments.

Symbol Description:

100 semiconductor devices;

101 base;

102 epitaxial layer;

103 patterned mask;

103a, 114a openings;

104 grooves;

105 first well area;

106, 110 insulation layer;

107 the first heavily doped region;

108 a first grid electrode;

109 mask layer;

111 second grid electrode;

112 second well area;

113 second heavily doped region;

114 dielectric layer;

115 contacts;

116 contact doping region;

117 Metal layer.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different elements of the provided high voltage semiconductor device. Specific examples of each element and its configuration are described below to simplify embodiments of the present invention. Of course, these are just examples, not intended to limit the present invention. For example, if a description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements , so that they are not in direct contact with the example. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

Some variations of the embodiment are described below. In the different drawings and described embodiments, like reference numerals have been used to designate like elements.

Please refer to FIGS. 1-15 , which illustrate schematic cross-sectional views of various stages in the process of forming the semiconductor device 100 shown in FIG. 15 according to some embodiments. Additional operations may be provided before, during, and/or after the stages described in FIGS. 1-15 . In various embodiments, some of the aforementioned operations may be moved, deleted or replaced. Additional components may be added to the semiconductor device. In various embodiments, some of the components described below may be removed, deleted or substituted.

According to some embodiments, as shown in FIG. 1 , a substrate 101 of a first conductivity type is provided and used as a drain (Drain, D) of the semiconductor device 100 . In some embodiments, the substrate 101 may be made of silicon or other semiconductor materials, or the substrate 101 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 101 may be made of compound semiconductors, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 101 includes a silicon-on-insulator (SOI) substrate or other suitable substrates. In this embodiment, the first conductivity type is n-type, but it is not limited thereto. In some other embodiments, the first conductivity type may also be p-type.

Subsequently, according to some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on the substrate 101 , and the substrate 101 and the epitaxial layer 102 have the same conductivity type, such as the first conductivity type. In this embodiment, the epitaxial layer 102 is n-type. In some embodiments, the doping concentration of the epitaxial layer 102 is less than that of the substrate 101 . In some embodiments, the epitaxial growth process may be metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD, PECVD), molecular beam epitaxy (molecular beam epitaxy, MBE) , hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), liquid phase epitaxy (liquid phase epitaxy, LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods or a combination of the foregoing.

Next, according to some embodiments, as shown in FIG. 2 , a patterned mask 103 is formed on the epitaxial layer 102 through a lithographic patterning process, and the patterned mask 103 has an opening 103 a. In this embodiment, the material of the patterned mask 103 may be a photoresist material. In some other embodiments, the material of the patterned mask 103 may be a hard mask composed of an oxide layer and a nitride layer. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination of the foregoing.

According to some embodiments, as shown in FIG. 3 , after the patterned mask 103 is formed, the epitaxial layer 102 is etched through the opening 103 a of the patterned mask 103 to form the trench 104 in the epitaxial layer 102 . In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof. It should be understood that the size, shape, and position of the groove 104 shown in FIG. 3 are just examples, not intended to limit the embodiment of the present invention.

Next, according to some embodiments, as shown in FIG. 4 , the trench 104 is subjected to an ion implantation process and a thermal drive-in process using the patterned mask 103 as a protective mask to form the first well region 105 . In this embodiment, the first well region 105 is disposed below the trench 104 , and the first well region 105 vertically overlaps with the trench 104 . In this embodiment, the first well region 105 has a conductivity type different from that of the substrate 101 and the epitaxial layer 102 , such as the second conductivity type. That is to say, in this embodiment, the first well region 105 is p-type. In some embodiments, the dopant of the first well region 105 may be boron (B). In some embodiments, the doping concentration of the first well region 105 is in the range of about 1E15 atoms/cm ³ to about 1E18 atoms/cm ³ .

In this embodiment, the first well region 105 is placed under the bottom of the trench 104 by using the ion implantation process and the thermal drive-in process, so that multiple processes including epitaxy, p-type dopant implantation, and high-temperature diffusion are not required. process cycle. Therefore, the process of forming the first well region 105 is simple, and does not need to bear expensive epitaxy costs. Furthermore, since the first well region 105 is located below the bottom of the trench 104, the first well region 105 does not occupy additional space (such as the space of the lateral epitaxial layer 102), so the cell pitch (cell pitch) can be reduced, thereby reducing channel area resistance. In this embodiment, the first well region 105 of the second conductivity type is used as a reduced surface field (RESURF) region, thereby increasing the breakdown voltage of the subsequently completed semiconductor device 100 . That is to say, the first well region 105 can improve the withstand voltage capability of the semiconductor device 100 .

According to some embodiments, as shown in FIG. 5 , an insulating layer 106 is formed in the trench 104 and on the first well region 105 through an oxidation process, and a thermal drive-in process is performed on the insulating layer 106 to increase the induction of the insulating layer 106. density. In some embodiments, insulating layer 106 covers the portion of epitaxial layer 102 exposed through trench 104 . In some embodiments, the insulating layer 106 can be silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or a combination thereof. In some embodiments, the oxidation process may be thermal oxidation, radical oxidation or other suitable processes. In some embodiments, the thermal drive-in process may be a rapid thermal annealing (RTA) process.

According to some embodiments, as shown in FIG. 6 , an etching process is performed to remove the bottom of the insulating layer 106 to expose the first well region 105 . In some embodiments, sidewall portions of the insulating layer 106 remain after the etch process. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

Next, according to some embodiments, an ion implantation process is performed on the trench 104 by using the patterned mask 103 and the remaining sidewall portion of the insulating layer 106 as a protective mask, so as to form the first heavily doped region 107 . In this embodiment, the first heavily doped region 107 is in the upper part of the first well region 105 . In this embodiment, the first heavily doped region 107 and the first well region 105 have the same conductivity type, for example, the second conductivity type. That is to say, in this embodiment, the first heavily doped region 107 is p-type. In some embodiments, the dopant of the first heavily doped region 107 may be boron difluoride (BF2). In some embodiments, the doping concentration of the first heavily doped region 107 is greater than that of the first well region 105 . In some embodiments, the doping concentration of the first heavily doped region 107 ranges from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ . In this embodiment, the first heavily doped region 107 of the second conductivity type is also used as a RESURF region to further enhance the effect of reducing the surface electric field.

According to some embodiments, as shown in FIG. 7 , the first gate electrode material is formed in the trench 104 by a deposition process, a lithographic patterning process, and an etching process. Next, using the patterned mask 103 and the remaining sidewall portion of the insulating layer 106 as a protective mask, an ion implantation process and a thermal drive-in process are performed on the first gate electrode material to form the first gate electrode 108 . In this embodiment, the first gate electrode 108 fills the lower portion of the trench 104 but not fills the trench 104 , and the insulating layer 106 surrounds the first gate electrode 108 . In this embodiment, the insulating layer 106 is disposed between the first gate electrode 108 and the epitaxial layer 102 . In this embodiment, the first gate electrode 108 vertically overlaps with the first well region 105 .

In some embodiments, the first gate electrode 108 may be of one or more layers, and may be formed of amorphous silicon, polysilicon, or a combination thereof. In some embodiments, the deposition process may be physical vapor deposition (PVD). PVD) process, chemical vapor deposition (chemical vapor deposition, CVD) process, other suitable processes or a combination of the foregoing. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

In this embodiment, the first gate electrode 108 and the first well region 105 have the same conductivity type, for example, the second conductivity type. That is to say, in this embodiment, the first gate electrode 108 is of p-type. In some embodiments, the dopant of the first gate electrode 108 may be boron difluoride (BF ₂ ). In some embodiments, the doping concentration of the first gate electrode 108 is greater than that of the first well region 105 . In some embodiments, the doping concentration of the first gate electrode 108 is in the range of about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ . In this embodiment, the first gate electrode 108 of the second conductivity type also serves as a RESURF region to further enhance the effect of reducing the surface electric field.

In this embodiment, the first gate electrode 108 of the second conductivity type, the first heavily doped region 107 and the first well region 105 can collectively serve as a RESURF region to extend the length of the P-N junction depletion region , reducing the maximum electric field under the electrodes, thus increasing the breakdown voltage of the subsequently completed semiconductor device 100 . That is to say, the first gate electrode 108 , the first heavily doped region 107 and the first well region 105 can improve the withstand voltage capability of the semiconductor device 100 . Furthermore, compared with the formation of the RESURF region only by the ion implantation process, in this embodiment, the first gate electrode 108, the first heavily doped region 107 and the first well region 105 can greatly increase the RESURF region. The depth further greatly increases the withstand voltage capability of the semiconductor device 100 .

Next, according to some embodiments, as shown in FIG. 8 , the upper portion of the insulating layer 106 is removed by an etching process. In some embodiments, the top surface of the insulating layer 106 is higher than the top surface of the first gate electrode 108 after the etching process. In some other embodiments, the top surface of the insulating layer 106 is lower than the top surface of the first gate electrode 108 after the etching process. In some other embodiments, the top surface of the insulating layer 106 is coplanar with the top surface of the first gate electrode 108 after the etching process. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

According to some embodiments, as shown in FIG. 9 , a mask layer 109 is formed on the first gate electrode 108 in the trench 104 . In this embodiment, the mask layer 109 covers the insulating layer 106 and the first gate electrode 108 . In some embodiments, the material of the mask layer 109 is the same as that of the patterned mask 103 . In some other embodiments, the material of the mask layer 109 is different from the material of the patterned mask 103 . In some embodiments, a mask material is formed by a deposition process or a coating process, followed by etching back to form the mask layer 109 .

Next, according to some embodiments, as shown in FIG. 10 , after the mask layer 109 is formed, the patterned mask 103 is removed. During the removal of the patterned mask 103 , the mask layer 109 covers the first gate electrode 108 , so the mask layer 109 can prevent the removal process of the patterned mask 103 from damaging the first gate electrode 108 .

Next, according to some embodiments, as shown in FIG. 11 , after removing the patterned mask 103 , the mask layer 109 is removed to expose the first gate electrode 108 and the insulating layer 106 . According to some embodiments, after the mask layer 109 is removed, a cleaning process may optionally be performed.

According to some embodiments, as shown in FIG. 12 , an insulating layer 110 is formed on the epitaxial layer 102 , the insulating layer 106 and the first gate electrode 108 by a deposition process. In some embodiments, the insulating layer 110 extends from the top surface of the epitaxial layer 102 into the trench 104 and covers the sidewalls of the epitaxial layer 102 and the top surfaces of the insulating layer 106 and the first gate electrode 108 . In this embodiment, the insulating layer 110 does not fill the trench 104 . That is, after the insulating layer 110 is formed, there is a space on the insulating layer 110 in the trench 104 . In some embodiments, the insulating layer 110 can be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon hafnium oxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide , other suitable high-k dielectric materials or combinations thereof. In some embodiments, the material of the insulating layer 110 is different from the material of the first insulating layer 106 . In some other embodiments, the material of the insulating layer 110 is the same as that of the insulating layer 106 . In this embodiment, the deposition process is a compliant deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing.

Next, according to some embodiments, the second gate electrode 111 is formed on the insulating layer 110 in the trench 104 through a deposition process, a lithographic patterning process and an etching process. In some embodiments, the second gate electrode 111 fills up the space on the insulating layer 110 previously in the trench 104 . In this embodiment, the second gate electrode 111 is located on the first gate electrode 108 , and the second gate electrode 111 is separated from the first gate electrode 108 by the insulating layer 110 . In this embodiment, the second gate electrode 111 vertically overlaps with the first well region 105 . In some embodiments, as shown in FIG. 12 , the lateral width of the second gate electrode 111 is greater than the lateral width of the first gate electrode 108 .

In some embodiments, the second gate electrode 111 can be of one or more layers, and is made of amorphous silicon, polysilicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. formed. Specifically, the aforementioned metals may include, but are not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The aforementioned metal nitrides may include, but are not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The foregoing metal silicides may include, but are not limited to, tungsten silicide (WSix). The aforementioned conductive metal oxide may include but not limited to ruthenium metal oxide (RuO ₂ ) and indium tin oxide (ITO). In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

In this embodiment, the gate-drain capacitance (Cgd) at the bottom of the trench of a conventional super junction trench MOSFET can be eliminated by disposing the first gate electrode 108 below the second gate electrode 111. ), effectively reducing the gate-drain charge (Qgd).

In addition, in this embodiment, the first well region 105 is disposed at the bottom of the trench 104 and under the first gate electrode 108 and the second gate electrode 111, so that the traditional super junction power metal oxide semiconductor field effect transistor can be avoided. The junction field effect transistor (junction field effect transistor, JFET) effect, thereby effectively reducing the on-resistance (Rds).

According to some embodiments, as shown in FIG. 13 , an ion implantation process is performed to form a second well region 112 in the epitaxial layer 102 . Next, another ion implantation process is performed to form the second heavily doped region 113 above the second well region 112 . In some embodiments, the second well region 112 is used as a channel region of the semiconductor device 100 , and the second heavily doped region 113 is used as a source (Source, S) of the semiconductor device 100 . In this embodiment, the second well region 112 and the second heavily doped region 113 surround the second gate electrode 111 . In this embodiment, the second well region 112 is separated from the first well region 105 . In some embodiments, the bottom surface of the second well region 112 is higher than the top surface of the first gate electrode 108 . That is, the interface between the second well region 112 and the epitaxial layer 102 is higher than the top surface of the first gate electrode 108 .

In this embodiment, the second well region 112 and the first well region 105 have the same conductivity type, for example, the second conductivity type. That is to say, in this embodiment, the second well region 112 is p-type. In this embodiment, the second heavily doped region 113 and the epitaxial layer 102 have the same conductivity type, such as the first conductivity type. That is to say, in this embodiment, the second heavily doped region 113 is n-type. In some embodiments, the doping concentration of the second heavily doped region 113 is greater than that of the epitaxial layer 102 . In some embodiments, the doping concentration of the second well region 112 is in the range of about 1E16 atoms/cm ³ to about 1E18 atoms/cm ³ . In some embodiments, the doping concentration of the second heavily doped region 113 ranges from about 1E18 atoms/cm ³ to about 1E21 atoms/cm ³ .

In this embodiment, since the second well region 112 is separated from the first well region 105, it is possible to prevent the first well region 105 from generating leakage due to high electric field impact ionization (impact ionization), and the breakdown current (avalanche current) can be reduced. ) is directly introduced into the second heavily doped region 113 as the source to drain away, avoiding the breakdown current entering the second well region 112 through the first well region 105 and causing gate oxide charging/gate oxide in the surrounding insulating layer 110 charge injection (gateoxide charging/gate oxide injection), thereby improving gate oxide reliability. Furthermore, since the second well region 112 is separated from the first well region 105, electric leakage can be avoided, so it is possible to avoid the start-up of the parasitic bipolar junction transistor (BJT) due to electric leakage, thereby avoiding the non-clamping Inductive load (unclamped inductive load, UIL) durability (ruggedness) problem.

Next, according to some embodiments, as shown in FIG. 14 , a dielectric layer 114 is formed on the second gate electrode 111 by a deposition process, a lithographic patterning process and an etching process. In this embodiment, the dielectric layer 114 covers the second gate electrode 111 and the insulating layer 110 , and has an opening 114 a exposing the second well region 112 and the second heavily doped region 113 .

In some embodiments, the dielectric layer 114 can be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon hafnium oxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, zirconium oxide Hafnium, other suitable high-k dielectric materials, or combinations of the foregoing. In some embodiments, the material of the dielectric layer 114 is different from the material of the insulating layer 110 . In some other embodiments, the material of the dielectric layer 114 is the same as that of the insulating layer 110 . In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

According to some embodiments, as shown in FIG. 15 , the contact 115 is formed in the opening 114 a of the dielectric layer 114 by a deposition process, a lithographic patterning process, and an etching process. In some embodiments, the contact 115 extends through the dielectric layer 114 and the second heavily doped region 113, and extends into the second well region 112 to be electrically connected to the second well region 112 and the second heavily doped region. District 113. In some embodiments, the contacts 115 may comprise copper, silver, gold, aluminum, tungsten, or combinations thereof, or other suitable conductive materials. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

According to some embodiments, as shown in FIG. 15 , before forming the contact 115 , an ion implantation process may be performed to form the contact doped region 116 in the second well region 112 . In some embodiments, the contact doped region 116 is located below the contact 115 , and the contact doped region 116 and the second well region 112 have the same conductivity type, such as the second conductivity type. That is to say, in this embodiment, the doped contact region 116 is p-type. In some embodiments, the doping concentration of the doped contact region 116 ranges from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ .

In some embodiments, a barrier layer (not shown) may be formed between the contact 115 and the dielectric layer 114 by a deposition process, a lithographic patterning process, and an etching process. In some embodiments, the barrier layer may include titanium nitride (TiN), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta ₂ O ₅ ), silicon dioxide (SiO ₂ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), magnesium fluoride (MgF ₂ ), calcium fluoride (CaF ₂ ), or a combination of the foregoing.

According to some embodiments, as shown in FIG. 15 , after the contact 115 is formed, a metal layer 117 may be formed on the contact 115 by a deposition process. In some embodiments, the metal layer 117 covers the dielectric layer 114 and the contact 115 and is electrically connected to the contact 115 . In some embodiments, the metal layer 117 may include copper, silver, gold, aluminum, tungsten or combinations thereof or other suitable conductive materials. In some embodiments, the material of the metal layer 117 is the same as that of the contact 115 . In some other embodiments, the material of the metal layer 117 is different from the material of the contact 115 . In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, after the metal layer 117 is formed, the process of the semiconductor device 100 is completed.

According to some embodiments of the present invention, by disposing the first well region under the bottom of the trench by ion implantation process and thermal drive-in process, it is not necessary to carry out multiple processes including epitaxy, implanting p-type dopant, and high-temperature diffusion. process cycle. Therefore, the process for forming the first well region is simple, and expensive epitaxy costs are not required. Furthermore, since the first well region is located below the bottom of the trench, the first well region does not occupy extra space (such as the space of the lateral epitaxial layer 102 ), so the cell pitch can be reduced, thereby reducing the resistance of the channel region.

In addition, the first gate electrode, the first heavily doped region and the first well region can collectively serve as a RESURF region, thereby increasing the breakdown voltage of the semiconductor device, that is, improving the withstand voltage capability of the semiconductor device. Furthermore, compared with the formation of the RESURF region only by ion implantation, in this embodiment, the first gate electrode, the first heavily doped region and the first well region can greatly increase the depth of the RESURF region, Further greatly increase the withstand voltage capability of the semiconductor device.

In addition, because the second well region is separated from the first well region, it is possible to avoid the leakage of the first well region due to high electric field impact ionization, and to directly introduce the breakdown current into the second heavily doped region as the source. drain to avoid gate oxide charge/gate oxide charge injection issues and improve gate oxide reliability. Furthermore, since the second well region is separated from the first well region, electric leakage can be avoided, so that the parasitic bipolar junction field effect transistor (BJT) can be prevented from starting due to electric leakage, thereby avoiding the durability of the unclamped inductive load (UIL). Questions of ruggedness.

The foregoing summary outlines features of many embodiments so that those of ordinary skill in the art can better understand aspects of the embodiments of the present invention. Ordinary persons in the art may design or modify other processes and structures based on the embodiments of the present invention without difficulty, so as to achieve the same purpose and/or obtain the same advantages as the embodiments of the present invention. Those skilled in the art should also understand that various changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention, and such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims (17)

1. A semiconductor device, comprising:

a substrate having a first conductivity type;

an epitaxial layer of the first conductivity type disposed on the substrate, the epitaxial layer having a trench therein;

a first well region disposed in the epitaxial layer and below the trench, and having a second conductivity type different from the first conductivity type;

a first gate electrode disposed in the trench and having the second conductivity type; and

a second gate electrode disposed in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer;

the doping concentration of the first grid electrode is greater than that of the first well region.

2. The semiconductor device of claim 1, wherein the first gate electrode and the second gate electrode vertically overlap the first well region.

3. The semiconductor device of claim 1, further comprising:

the first heavily doped region is arranged in the upper part of the first well region and has the second conduction type.

4. The semiconductor device of claim 3, wherein a doping concentration of the first heavily doped region is greater than a doping concentration of the first well region.

5. The semiconductor device of claim 1, further comprising:

a second insulating layer disposed between the first gate electrode and the epitaxial layer.

6. The semiconductor device of claim 1, further comprising:

a second well region surrounding the second gate electrode and having the second conductivity type.

7. The semiconductor device of claim 6, wherein the second well region is spaced apart from the first well region.

8. The semiconductor device of claim 6, further comprising:

and a second heavily doped region surrounding the second gate electrode and located above the second well region and having the first conductivity type.

9. The semiconductor device of claim 8, further comprising:

a dielectric layer disposed on the second gate electrode; and

a contact extending through the dielectric layer and electrically connected to the second well region and the second heavily doped region.

10. The semiconductor device of claim 9, further comprising:

a contact doped region disposed in the second well region and below the contact, and having the second conductivity type.

11. The semiconductor device of claim 9, further comprising:

a metal layer disposed on the contact and the dielectric layer; and

a barrier layer disposed between the contact and the dielectric layer.

12. A method of forming a semiconductor device, comprising:

providing a substrate with a first conductive type;

forming an epitaxial layer of the first conductivity type on the substrate;

forming a trench in the epitaxial layer;

forming a first well region of a second conductivity type in the epitaxial layer and below the trench, wherein the second conductivity type is different from the first conductivity type;

forming a first gate electrode having the second conductivity type in the trench; and

forming a second gate electrode in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer;

the doping concentration of the first grid electrode is greater than that of the first well region.

13. The method of forming a semiconductor device according to claim 12, wherein the step of forming the trench comprises:

forming a patterned mask with a first opening on the epitaxial layer; and

an etching process is performed on the epitaxial layer through the first opening.

14. The method of claim 13, wherein forming the first well region comprises:

and performing an ion implantation process and a thermal drive-in process on the trench by using the patterned mask as a protective mask.

15. The method of forming a semiconductor device according to claim 12, further comprising:

after the first well region is formed and before the first gate electrode is formed, an ion implantation process is performed to form a first heavily doped region having the second conductive type in an upper portion of the first well region.

16. The method of forming a semiconductor device according to claim 13, further comprising:

forming a mask layer over the first gate electrode in the trench after forming the first gate electrode and before forming the second gate electrode;

removing the patterned mask; and

the mask layer is removed.

17. The method of forming a semiconductor device of claim 12, further comprising:

forming a second well region of the second conductivity type surrounding the second gate electrode, and

a second heavily doped region of the first conductivity type is formed over the second well region, the second heavily doped region surrounding the second gate electrode.

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