CN107910271A - Power semiconductor and its manufacture method - Google Patents

Abstract

This application discloses power semiconductor and its manufacture method.This method includes：Multiple grooves are formed in the semiconductor substrate, and the multiple groove includes the first groove of first size and the second groove of the second size, and the first size is more than second size；Splitting bar structure is formed in the first groove；Grid wiring is formed in the second groove, the grid wiring is connected with grid conductor；In the Semiconductor substrate Zhong Ti areas；Source region is formed in the body area；And formation source electrode and gate electrode, the source electrode are electrically connected with the source region and the shielded conductor, the gate electrode is electrically connected with the grid wiring.This method utilizes the filling effect of different dimensioned trenches, while forms grid conductor and grid wiring, so as to simplify technique, reduces manufacture cost.

Description

Power semiconductor device and manufacturing method thereof

technical field

The present invention relates to the technical field of electronic devices, and more specifically, to a power semiconductor device and a manufacturing method thereof.

Background technique

Power semiconductor devices are also known as power electronic devices, including power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (laterally diffused metal oxide semiconductor) field effect transistors and IGBT (insulated gate bipolar transistors), etc. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate, and in an on state, current mainly flows along the longitudinal direction of the semiconductor substrate.

In the high-frequency application of power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. On the basis of the VDMOS field effect transistor, the trench type MOS field effect transistor is further developed, in which the gate conductor is formed in the trench, and the gate dielectric is formed on the side wall of the trench to separate the gate conductor and the semiconductor layer , thereby forming a channel in the semiconductor layer along the direction of the sidewall of the trench. The trench (Trench) process changes the channel from horizontal to vertical, eliminates the influence of the parasitic JFET resistance of the planar structure, and greatly reduces the cell size. On this basis, increasing the original cell density and increasing the total width of the channel per unit area of the chip can increase the channel width-to-length ratio of the device on the unit silicon chip, thereby increasing the current, reducing the on-resistance and related parameters. It has been optimized to achieve the goal of higher power and high performance for smaller-sized dies, so the trench process is increasingly used in new power semiconductor devices.

However, as the unit density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly. The gate-to-drain capacitance Cgd is directly related to the switching characteristics of the device. In order to reduce the gate-to-drain capacitance Cgd, split gate trench (Split Gate Trench, abbreviated as SGT) power semiconductor devices have been further developed, in which the gate conductor extends to the drift region, and a thick oxide layer is used between the gate conductor and the drain. Objects are separated, thereby reducing the gate-to-drain capacitance Cgd, increasing the switching speed, and reducing the switching loss. At the same time, the shielding conductor under the gate conductor and the source electrode are connected to the common ground, thereby introducing a charge balance effect and reducing the surface electric field (Reduced Surface Field, abbreviated as RESURF) in the vertical direction of the power semiconductor device. ) effect, further reducing the on-resistance Rdson, thereby reducing the conduction loss.

Figures 1a and 1b respectively show cross-sectional views of main steps of a method of manufacturing an SGT power semiconductor device according to the prior art. As shown in FIG. 1 a , a trench 102 is formed in a semiconductor substrate 101 . A first insulating layer 103 is formed at a lower portion of the trench 102 , and a shield conductor 104 fills the trench 102 . In the upper part of the trench 102, two openings separated by the shield conductor 104 are formed. Further, as shown in FIG. 1b, a gate dielectric 105 is formed on the upper sidewall of the trench 102 and the exposed portion of the shielding conductor 104, and then a conductive material is filled in the two openings separated by the shielding conductor 104 to form two gate conductor 106 .

In the SGT power semiconductor device, the shielding conductor 104 is connected to the source electrode of the power semiconductor device to generate the RESURF effect. Two gate conductors 106 are located on both sides of the shield conductor 104 . The shielding conductor 104 is separated from the drain region of the power semiconductor device by the first insulating layer 103 , and is separated from the gate electrode 106 by the gate dielectric 105 . The gate conductor 106 is separated from the well region in the semiconductor substrate 101 by the gate dielectric 105, thereby forming a channel in the well region. As shown, the thickness of the first insulating layer 103 is smaller than the thickness of the gate dielectric 105 .

According to the SGT theory, no matter what kind of SGT structure, the material of shielding conductor 104 needs to be isolated from the second conductive material and the material used for isolation needs to meet certain capacitance parameters, otherwise gate-source short circuit, gate-drain capacitance Cgd abnormality and other failures will easily occur. . How to optimize the device structure and meet the parameters and reliability requirements of the product, and at the same time make the wiring method the most efficient and low-cost is the content to be studied by those skilled in the art.

Contents of the invention

In view of the above problems, the object of the present invention is to provide a power semiconductor device and its manufacturing method, in which the gate conductor and gate wiring are formed simultaneously by utilizing the filling effect of trenches of different sizes, so that the process can be simplified.

According to an aspect of the present invention, there is provided a method of manufacturing a power semiconductor device, comprising: forming a plurality of trenches in a semiconductor substrate of a first doping type, the plurality of trenches including a first trench of a first size A trench and a second trench of a second size, the first dimension being greater than the second dimension; forming a split gate structure in the first trench, the split gate structure including a shield conductor, a gate conductor, and a clip a second insulating layer in between; forming a gate wiring in the second trench, the gate wiring being connected to the gate conductor; in a region of the semiconductor substrate adjacent to the trench forming a body region of a second doping type opposite to the first doping type; forming a source region of the first doping type in the body region; and forming a source electrode and a gate electrode, the source electrode is electrically connected to the source region and the shielding conductor, and the gate electrode is electrically connected to the gate wiring.

Preferably, the step of forming a split gate structure includes: forming an insulating stack on the sidewall and bottom of the first trench, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounds the second insulating layer; fills the shielding conductor in the first trench; forms first openings on both sides of the shielding conductor in the upper part of the first trench, and the first opening exposing sidewalls of the upper portion of the first trench; forming a gate dielectric on the sidewalls of the upper portion of the first trench; and forming the gate conductor to fill the first opening, wherein the gate conductors are isolated from each other by at least one layer of the insulating stack, the gate conductors are isolated from the body region by the gate dielectric, the shield conductors are isolated from the The semiconductor substrates are isolated from each other by the insulating stack.

Preferably, the step of forming gate wiring includes: filling the first insulating layer in the second trench; forming a second opening on the upper part of the second trench, the second opening exposing the first forming the gate dielectric on the sidewall of the upper part of the second trench; and forming the gate wiring to fill the second opening; wherein, the gate wiring and The body regions are isolated from each other by the gate dielectric.

Preferably, the first insulating layers in the first trench and the second trench are respectively a conformal layer and a filling layer, and are formed at the same time.

Preferably, a planarization step is further included between the step of filling the shielding conductor and the step of forming the first opening.

Preferably, prior to the planarization step, said shielding conductor, said first insulating layer and said second insulating layer respectively comprise a first portion located in said first trench and laterally on the surface of said semiconductor substrate. Extending the second portion, in a planarization step, with the semiconductor substrate as a stop layer, removing respective second portions of the shield conductor, the second insulating layer and the first insulating layer, such that, Top ends of respective first portions of the shielding conductor, the second insulating layer and the first insulating layer are flush with the surface of the first insulating layer.

Preferably, in the step of forming the first opening, a portion of the first portion of the first insulating layer located above the first trench is removed, and the shielding conductor extends downward from the surface of the semiconductor substrate to a predetermined depth. The first opening extending downward from the surface of the semiconductor substrate to a predetermined depth is thereby formed.

Preferably, the step of forming the gate conductor includes: depositing a first conductive layer to fill the first opening.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the depths of the first groove and the second groove are in the range of 0.1 to 50 micrometers.

Preferably, the width of the first groove is greater than or equal to 1.5 times the width of the second groove.

Preferably, the width of the first trench is in the range of 0.2 to 10 microns.

Preferably, the width of the second trench is in the range of 0.1 to 5 microns.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

Preferably, the sidewalls of the first trench are inclined such that the width of the top of the first trench is greater than the width of the bottom of the first trench.

Preferably, the steps of filling the shielding conductor and forming the gate conductor each comprise at least one deposition.

According to another aspect of the present invention, a power semiconductor device is provided, comprising: a plurality of trenches located in a semiconductor substrate, the semiconductor substrate is of a first doping type, and the plurality of trenches comprise a first dimension a first trench of a second size and a second trench of a second size, the first size being larger than the second size; a split gate structure located in the first trench, the split gate structure comprising a shielding conductor, a gate a pole conductor and a second insulating layer interposed therebetween; a gate wiring located in the second trench, the gate wiring being connected to the gate conductor; a gate wiring located in the semiconductor substrate a body region, the body region is adjacent to the upper part of the first trench, and is of a second doping type, and the second doping type is opposite to the first doping type; a source region located in the body region , the source region is of the first doping type; a source electrode electrically connected to the source region and the shielding conductor; and a gate electrode electrically connected to the gate wiring.

Preferably, the split gate structure includes: an insulation stack located on the lower sidewall and bottom of the first trench, the insulation stack includes a first insulation layer and the second insulation layer, and the first insulation a layer surrounding the second insulating layer; at least a portion of a shield conductor in the first trench, the shield conductor extending from above the first trench to the bottom thereof, and connected to the semiconductor substrate by The insulation stacks are isolated from each other; the gate conductors located on both sides of the shielding conductor in the upper part of the first trench; wherein the gate conductor and the shielding conductor are separated by the insulation stack At least one layer of each is isolated from each other, the gate conductor is isolated from the body region by the gate dielectric, and the shield conductor is isolated from the semiconductor substrate by the insulating stack.

Preferably, the first insulating layer fills the lower part of the second trench, the gate wiring fills the upper part of the second trench, and the gate wiring and the body region are connected by the gate pole dielectrics are isolated from each other.

Preferably, the shielding conductor extends downward from the surface of the semiconductor substrate to a predetermined depth.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the depths of the first groove and the second groove are in the range of 0.1 to 50 micrometers.

Preferably, the width of the first groove is greater than or equal to 1.5 times the width of the second groove.

Preferably, the width of the first trench is in the range of 0.2 to 10 microns.

Preferably, the width of the second trench is in the range of 0.1 to 5 microns.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

Preferably, the sidewalls of the first trench are inclined such that the width of the top of the first trench is greater than the width of the bottom of the first trench.

Preferably, the power semiconductor device is one selected from CMOS devices, BCD devices, MOSFET transistors, IGBTs and Schottky diodes.

In a method according to an embodiment of the present invention, an SGT structure is formed in a power semiconductor device, wherein an insulating stack is formed between a shield conductor and a semiconductor substrate, thereby reducing the gate-to-drain capacitance Cgd.

The method utilizes the filling effect of trenches with different sizes to simultaneously form the gate conductor and the gate wiring, thereby simplifying the process. Realize the SGT structure through relatively simple process steps, solve the complex process in the conventional process, prone to gate-source short circuit, gate-to-drain capacitance Cgd abnormality and other problems, so as to meet the product parameters and reliability requirements, at the same time, combine the specific process steps to make the wiring method to the most efficient and low cost. Compared with the prior art, based on the 0.25-0.35um process, the method can reduce the number of photoresist masks used in the current manufacturing process by 3-4 photoresist masks.

The structure of a split-gate power semiconductor device with reduced source-drain capacitance and its forming method adopted in the embodiment of the present invention can also be applied to products such as CMOS, BCD, power MOSFET, high-power transistor, IGBT, and Schottky.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

1a and 1b respectively show cross-sectional views of the main steps of a method of manufacturing a power semiconductor device according to the prior art.

FIG. 2 shows a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention.

3a to 3i show cross-sectional views of different stages of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

If it is to describe the situation directly on another layer or another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In the present application, "A is located directly in B" means that A is located in B, and A is adjacent to B, but not that A is located in a doped region formed in B.

In the present application, the term "semiconductor structure" refers to a general designation of the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

Unless otherwise specified below, various parts of the semiconductor device may be composed of materials known to those skilled in the art. The semiconductor material includes, for example, Group III-V semiconductors, such as GaAs, InP, GaN, SiC, and Group IV semiconductors, such as Si and Ge.

Fig. 2 shows a flowchart of a method for manufacturing an SGT power semiconductor device according to an embodiment of the present invention, and Figs. 3a to 3i show cross-sectional views in different steps, respectively. The steps of the manufacturing method according to the embodiment of the present invention are described below with reference to FIGS. 2 and 3a to 3i.

The method starts with a semiconductor substrate 101 . The semiconductor substrate is, for example, an N-type doped silicon substrate, and the vertical doping of the silicon substrate is uniform, and the resistivity is, for example, in the range of 1˜15 Ω·cm. The semiconductor substrate has opposing first and second surfaces. Preferably, on the first surface of the semiconductor substrate, a voltage-dividing ring structure of the power semiconductor is formed by processes such as photolithography, etching, ion implantation, and impurity activation. The voltage-dividing ring structure belongs to a well-known device structure in the field. The structural part will not be described in detail here. Preferably, the semiconductor substrate 101 used in this embodiment may be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, and Schottky diodes.

In step S101 , a first trench 1021 and a second trench 1022 are respectively formed in the first region 201 and the second region 202 of the semiconductor substrate 101 , as shown in FIG. 3 a .

The process for forming the first trench 1021 and the second trench 1022 includes forming a resist mask through photolithography and etching, and etching away exposed portions of the semiconductor substrate 101 through openings of the resist mask.

In this embodiment, the first region 201 refers to the wiring region of the source region and the shield conductor in the SGT structure, and the second region 202 refers to the wiring region of the gate conductor in the SGT structure.

The first trench 1021 and the second trench 1022 extend downward from the surface of the semiconductor substrate 101 and reach a predetermined depth in the semiconductor substrate 101 . The depths of the first groove 1021 and the second groove 1022 are in the range of 0.1 to 50 micrometers. The width of the first trench 1021 is greater than or equal to 1.5 times the width of the second trench 1022 . In this embodiment, the width of the first trench 1021 is in the range of 0.2 to 10 microns. The width of the second trench 1022 is in the range of 0.1 to 5 microns. The width of the trench of the SGT structure is much wider than that of conventional trench power semiconductor devices with the same conduction efficiency level, and the depth of the trench is also much deeper than that of conventional trench power semiconductor devices.

Preferably, the sidewalls of the first trench 1021 and the second trench 1022 are inclined, for example at an angle of 85 to 89 degrees relative to the top of the vertical trench, so that the bottom width of the trench is smaller than the top width. The angle of the groove is oblique, which is beneficial to the subsequent filling of various dielectric layers and conductive materials, and reduces defects caused by filling gaps.

In step S102 , an insulating stack is sequentially formed on the surface of the semiconductor substrate 101 , the insulating stack includes a conformal first insulating layer 122 and a second insulating layer 123 , as shown in FIG. 3 b .

In the first trench 1021 , the first insulating layer 122 surrounds the second insulating layer 123 . In the second trench 1022 , the first insulating layer 122 fills the inner space of the trench, and the second insulating layer 123 covers the first insulating layer 122 in this region. The size of the first trench 1021 is larger than that of the second trench 1022 , therefore, even if the first insulating layer 122 is deposited and formed in the same process, insulating layers with different filling effects can be obtained. The first insulating layer 122 in the first trench 1021 is a conformal layer, and the first insulating layer 122 in the second trench 1022 is a filling layer. When the width of the second trench 1022 is, for example, twice or more than the thickness of the first insulating layer 122 , the first insulating layer 122 may completely fill the second trench 1022 .

The first insulating layer 122 and the second insulating layer 123 are composed of different insulating materials. In this embodiment, the first insulating layer 122 is made of silicon oxide, for example. The second insulating layer 123 is, for example, composed of at least one selected from silicon nitride, oxynitride or polysilicon. Preferably, the second insulating layer 123 is composed of silicon nitride. The thickness of the first insulating layer 122 is, for example, 500 to 50000 angstroms, and the thickness of the second insulating layer 123 is, for example, 50 to 5000 angstroms. The larger the thickness of the first insulating layer 122 is, the smaller the gate-to-drain capacitance Cgd is.

The process for forming the first insulating layer 122 includes forming an oxide layer on the inner wall of the first trench 1021 by thermal oxidation, chemical vapor deposition (CVD) or high density plasma chemical vapor deposition. The oxide layer conformally covers the sidewalls and the bottom of the first trench 1021 , thereby still retaining a part of the inner space of the first trench 1021 .

The process for forming the second insulating layer 123 includes forming a nitride layer on the surface of the first insulating layer 122 by chemical vapor deposition (CVD) or high density plasma chemical vapor deposition. The nitride layer conformally covers the surface of the first insulating layer 122 , thereby still retaining a part of the inner space of the first trench 1021 .

In step S103, the shielding conductor 104 is formed in the first trench 1021, as shown in FIG. 3c.

The shielding conductor 104 consists, for example, of doped amorphous silicon or polycrystalline silicon. The process for forming the shielding conductor 104 includes, for example, depositing polysilicon by a process such as sputtering, so that the polysilicon fills the remaining part of the first trench 1021, and removing the polysilicon located outside the first trench 1021 by chemical mechanical planarization (CMP), The polysilicon filling the first trench 1021 is made to form the shielding conductor 104 .

The deposition rate of the polysilicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the shield conductor 104, its resistance can be adjusted. In this embodiment, the square resistance Rs of the shielding conductor 104 is, for example, less than 20 ohms. Further, the smaller the sheet resistance Rs of the shielding conductor 104 is, the larger the thickness of the oxide layer formed in the subsequent oxidation layer is compared with that of silicon. Further, if the material of the shielding conductor 104 is amorphous, the easier it is to form a lower sheet resistance Rs.

In the above deposition steps, one or more depositions may be used to deposit the material forming the shielding conductor 104 . During multiple depositions, the rate of subsequent deposition steps is less than that of previous deposition steps, so that the deposition rate gradually decreases. In the trench filling process, the slower the deposition rate, the better the filling effect. Filling the bottom of the trench is more difficult than filling the top of the trench. Therefore, when filling multiple times, the deposition rate in the front should be lower than that of any subsequent deposition.

In the above-mentioned chemical mechanical planarization step, the semiconductor substrate 101 is used as a stop layer. At the first trench 1021 , the planarization not only removes the portion of the polysilicon located outside the first trench 1021 , but also removes the portions of the second insulating layer 123 and the first insulating layer 122 located outside the first trench 1021 . Therefore, in the first trench 1021 , the tops of the shield conductor 104 , the second insulating layer 123 and the first insulating layer 122 are flush with the surface of the semiconductor substrate 101 . At the second trench 1022 , the planarization not only removes the portion of the first insulating layer 122 outside the second trench 1022 , but also removes the second insulating layer 123 and polysilicon above the first insulating layer 122 . Therefore, the top of the first insulating layer 122 is flush with the surface of the semiconductor substrate 101 .

In step S104, a part of the first insulating layer 122 is removed by etching, thereby forming first openings 1241 on both sides of the shielding conductor 104 on the upper part of the first trench 1021, and forming second openings 1022 on the upper part of the second trench 1022, As shown in Figure 3d. The first opening 1241 and the second opening 1022 re-expose the upper sidewall of the first trench 1021 .

The etching process is, for example, wet etching. The exposed portion of the first insulating layer 122 is removed with respect to the semiconductor substrate 101 , the second insulating layer 123 and the shield conductor 104 due to the selectivity of the etchant. The etching back etches the portion of the first insulating layer 122 inside the first trench 1021 and the second trench 1022 , thereby exposing the surface of the semiconductor substrate 101 . The second insulating layer 123 and a portion of the shielding conductor 104 extend upward from the surface of the semiconductor substrate 101 to a height corresponding to the thickness of the first insulating layer 122 , for example, 500 to 50000 angstroms. The extended height is beneficial to the subsequent contact hole opening process. The depth to which the first insulating layer 122 extends downward from the surface of the semiconductor substrate 101 is, for example, 0.5 to 5 microns. After etching, a portion of the first insulating layer 122 at the lower sidewall and bottom of the first trench 1021 remains, so that the lower portion of the shielding conductor 104 and the semiconductor substrate 101 are still isolated from each other by the insulating stack. A portion of the first insulating layer 122 at the lower portion of the second trench 1022 remains. As described above, since the first insulating layer 122 is a filling layer in the second trench 1022, no shield conductor is formed therein.

In step S105, a gate dielectric 105 is formed on the upper sidewall of the first trench 1021 and the top of the shielding conductor 104, and the gate dielectric 105 is formed on the upper sidewall of the second trench 1022, as shown in FIG. 3e.

The process for forming the gate dielectric 105 may employ thermal oxidation. The thermal oxidation temperature is, for example, 950 to 1200 degrees Celsius. The exposed silicon material of the semiconductor substrate 101 and the shield conductor 104 forms silicon oxide during the thermal oxidation process. In the thermal oxidation step, the surface of the semiconductor substrate 101 is also exposed to the atmosphere. The gate dielectric 105 not only covers the upper sidewalls of the first trench 1021 and the second trench 1022 , but also covers the surface of the semiconductor substrate 101 .

Compared with the dense semiconductor substrate 101, the shielding conductor 104 is a heavily doped amorphous or polycrystalline material with a looser structure and higher doping concentration. As a result, the thickness of the second portion of the gate dielectric 105 on the surface of the shield conductor 104 is greater than the thickness of the first portion on the surface of the semiconductor substrate 101 and in the first trench 1021 and the second trench 1022 . The thickness of the first part of the gate dielectric 105 is, for example, 50 to 5000 angstroms, and the thickness of the second part is, for example, 60 to 10000 angstroms.

In step S106, the gate conductor 106 is formed in the first opening 1241, the gate wiring 131 is formed in the second opening 1242, and the body region 107 is formed in the region of the semiconductor substrate 101 adjacent to the first trench 1021. and source region 108, as shown in Figure 3f.

The gate conductor 106 and the gate wiring 131 are composed of doped amorphous silicon or polysilicon, for example. The process for forming the gate conductor 106 and the gate wiring 131 includes, for example, depositing polysilicon by a process such as sputtering so that the polysilicon fills the remaining parts of the first trench 1021 and the second trench 1022, and chemical mechanical planarization (CMP) ) remove the polysilicon outside the first opening 1241 and the second opening 1242, so that the polysilicon fills the openings on both sides of the shielding conductor 104, thereby forming the gate conductor 106 in the first opening 1241 and forming the gate conductor in the second opening 1242. Wiring 131.

The deposition rate of the polysilicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the gate conductor 106, its resistance can be adjusted. In this embodiment, the sheet resistance Rs of the gate conductor 106 is, for example, less than 20 ohms. Further, the smaller the sheet resistance Rs of the gate conductor 106 is, the larger the thickness of the oxide layer formed in the subsequent oxidation layer is compared with that of silicon. Further, if the material of the gate conductor 106 is amorphous, the easier it is to form a lower sheet resistance Rs.

In the above deposition steps, one or more depositions may be used to form the material of the gate conductor 106 . During multiple depositions, the rate of subsequent deposition steps is less than that of previous deposition steps, so that the deposition rate gradually decreases. In the trench filling process, the slower the deposition rate, the better the filling effect. Filling the bottom of the trench is more difficult than filling the top of the trench. Therefore, when filling multiple times, the deposition rate in the front should be lower than that of any subsequent deposition.

Next, a P-type body region 107 is formed in the semiconductor substrate 101 , and an N-type source region is formed in the body region 107 . The process for forming the body region 107 and the source region 108 is, for example, multiple ion implantations. Different types of doped regions are formed by selecting appropriate dopants, followed by thermal annealing to activate the impurities. In ion implantation, using the shield conductor 104 and the gate conductor 106 as a hard mask, the lateral positions of the body region 107 and the source region 108 can be defined, so that a photoresist mask can be omitted. The angle of the ion implantation is, for example, zero angle, that is, the implantation is vertical to the surface of the semiconductor substrate 101 . By controlling the energy of ion implantation, the implantation depths of the body region 107 and the source region 108 can be limited, thereby defining the vertical position.

When forming the body region 107, the dopant used is B11 or BF2, or B11 can be injected first and then BF2 can be injected, the implantation energy is 20-100Kev, the implantation dose is 1E14-1E16, and the thermal annealing temperature is 500-1000 degrees Celsius. When forming the source region 108, the dopant used is P+ or AS+, the implantation energy is 60-150Kev, the implantation dose is 1E14-1E16, and the thermal annealing temperature is 800-1100 degrees Celsius.

In this step, an SGT structure is formed in the first trench 1021 , including the shield conductor 104 and the gate conductor 106 located in the trench. The gate conductor 106 includes a first portion located in the first trench 1021 , and a second portion extending over the semiconductor substrate 101 . First portions of the gate conductor 106 are formed in the first openings 1241 on both sides of the shield conductor 104 so that the shield conductor 104 is sandwiched therebetween. The shielding conductor 104 and the gate conductor 106 are isolated from each other by the second insulating layer 123 . The lower portion of the shielding conductor 104 extends to the lower portion of the first trench 1021 , and is isolated from the semiconductor substrate 101 by an insulating stack, which includes a first insulating layer 122 and a second insulating layer 123 . Gate conductor 106 is adjacent to body region 107 and source region 108 and is isolated from each other by gate dielectric 105 .

In step S107, an interlayer dielectric layer 109 is deposited on the surface of the semiconductor structure, as shown in FIG. 3g.

The interlayer dielectric layer 109 covers the first region and the second region of the semiconductor substrate 101. The interlayer dielectric layer 109 may be composed of at least one selected from silicon dioxide, silicon nitride, and silicon oxynitride, and may be a single layer. or laminated structures. In this embodiment, the interlayer dielectric layer 109 may be, for example, borophosphosilicate glass (BPSG) with a thickness of 2000 to 15000 angstroms.

In step S108, a plurality of contact holes 125 reaching the source region 108, the gate conductor 106 and the shielding conductor 104 are formed in the interlayer dielectric layer 109, and contact regions 110 are respectively formed at the bottoms of the plurality of contact holes 125 by ion implantation. , as shown in Figure 3h.

A process for forming the contact hole 125 is, for example, dry etching. The sidewalls of the contact hole 125 are inclined, for example, at an angle of 85 to 89.9 degrees relative to the vertical tops of the first trench 1021 and the second trench 1022 , so that the bottom width of the contact hole 125 is smaller than the top width. The angle of the contact hole 125 is oblique, which is beneficial to the subsequent filling of the conductive material and reduces problems such as defects caused by filling gaps.

In the first region 201 of the semiconductor substrate 101, the first group of contact holes in the plurality of contact holes 125 sequentially pass through the interlayer dielectric layer 109 and the gate dielectric 105, extending to a predetermined depth in the shielding conductor 104, and the second The set of contact holes sequentially pass through the interlayer dielectric layer 109 , the gate dielectric 10 , and the source region 108 to a predetermined depth in the body region 107 . The predetermined depth is, for example, 0.1 to 1 micron.

In the second region 202 of the semiconductor substrate 101 , a third group of contact holes of the plurality of contact holes 125 sequentially pass through the interlayer dielectric layer 109 and extend to a predetermined depth in the gate conductor 106 .

In the ion implantation, the interlayer dielectric layer is used as a hard mask to define the lateral position of the contact region 110, so that the photoresist mask can be omitted. The dopant used in the ion implantation is B11 or BF2, or B11 can be injected first and then BF2, the implantation energy is 20-100Kev, the implantation dose is 1E14-1E16, and the thermal annealing temperature is 500-1000 degrees Celsius. After ion implantation, a thermal anneal may be performed to activate the dopants.

In step S109, a source electrode 111 and a gate electrode 112 are formed, as shown in FIG. 3i.

This step includes, for example, depositing a metal layer and patterning. The metal layer is made of, for example, one selected from Ti, TiN, TiSi, W, AL, AlSi, AlSiCu, Cu, Ni or an alloy thereof. The metal layer is patterned into source electrodes 111 and gate electrodes 112 by etching. As shown, the source electrode 111 and the gate electrode 112 are isolated from each other.

In the first region 201 of the semiconductor substrate 101, the source electrode 111 reaches the shield conductor 104 through the first group of contact holes in the plurality of contact holes 125, and reaches the shield conductor 104 through the second group of contact holes in the plurality of contact holes 125. The holes reach the source region 108, thereby electrically connecting the source region 108 and the shield conductor 104 to each other. In the second region 202 of the semiconductor substrate 101 , the gate electrode 112 reaches the gate conductor 106 via a third set of contact holes of the plurality of contact holes 125 .

After step S109, the metallization of the power semiconductor device has been achieved. Further, according to the needs of the product, the protection of the passivation layer can be added to complete the processing of the front structure of the power semiconductor device. The final realization of the device is completed through a series of back-end processes such as thinning, gold backing, and scribing.

It should be noted that although the shielding conductors 104 and the gate conductors 106 in different trenches are isolated from each other in the above cross-sectional view, however, in an actual power semiconductor device, viewed from the planar structure, the above-mentioned different trenches The shield conductors 104 may be connected to each other, and the gate conductors 106 may also be connected to each other. In one embodiment, the connection method is, for example, that the gate conductor 106 in different first trenches 1021 and the gate wiring in the second trench 1022 are integrally formed by a single conductive layer, and the gate conductors 106 in different first trenches 1021 The shield conductor 104 is integrally formed from a single conductive layer. In an alternative embodiment, the connection method is, for example, using a common source electrode to connect the shielding conductors 104 in different first trenches 1021 to each other, and using a common gate electrode to connect the gate conductors 104 in different first trenches 1021 to each other. The pole conductor 106 and the gate wiring 131 in the second trench 1022 are connected to each other.

It should be noted that in this document, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

Embodiments according to the present invention are described above, and these embodiments do not exhaustively describe all details, nor limit the invention to only specific embodiments. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (28)

1. A method of manufacturing a power semiconductor device, comprising: A plurality of trenches are formed in a semiconductor substrate of a first doping type, the plurality of trenches include a first trench of a first size and a second trench of a second size, the first size being larger than the second size; forming a split gate structure in the first trench, the split gate structure including a shield conductor, a gate conductor and a second insulating layer sandwiched therebetween; forming a gate wiring in the second trench, the gate wiring being connected to the gate conductor; forming a body region of a second doping type opposite to the first doping type in a region of the semiconductor substrate adjacent to the trench; forming a source region of the first doping type in the body region; and A source electrode and a gate electrode are formed, the source electrode is electrically connected to the source region and the shield conductor, and the gate electrode is electrically connected to the gate wiring. 2. The method according to claim 1, wherein the step of forming the split gate structure comprises: forming an insulating stack on sidewalls and a bottom of the first trench, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; filling the shield conductor in the first trench; forming first openings on both sides of the shielding conductor on the upper portion of the first trench, the first openings exposing sidewalls of the upper portion of the first trench; forming a gate dielectric on sidewalls of the upper portion of the first trench; and forming the gate conductor to fill the first opening, Wherein, the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, and the gate conductor and the body region are isolated from each other by the gate dielectric, so The shielding conductor and the semiconductor substrate are isolated from each other by the insulating layer. 3. The method according to claim 2, wherein the step of forming the gate wiring comprises: filling the first insulating layer in the second trench; forming a second opening on the upper portion of the second trench, the second opening exposing a sidewall of the upper portion of the second trench; forming the gate dielectric on sidewalls of the upper portion of the second trench; and forming the gate wiring to fill the second opening; Wherein, the gate wiring and the body region are isolated from each other by the gate dielectric. 4. The method according to claim 3, wherein the first insulating layers in the first trench and the second trench are respectively a conformal layer and a filling layer, and are formed simultaneously. 5. The method of claim 3, further comprising a planarization step between the step of filling the shield conductor and the step of forming the first opening. 6. The method of claim 5, wherein, prior to the planarizing step, the shield conductor, the first insulating layer, and the second insulating layer each comprise a first portion located in the first trench and a second portion extending laterally over the surface of the semiconductor substrate, In the planarization step, with the semiconductor substrate as a stop layer, the shielding conductor, the second insulating layer and the respective second portions of the first insulating layer are removed such that the shielding conductor, the Top ends of the first portions of the second insulating layer and the first insulating layer are flush with the surface of the first insulating layer. 7. The method according to claim 6, wherein, in the step of forming the first opening, a portion of the first portion of the first insulating layer located above the first trench is removed, and the shielding conductor is removed from the first trench. The surface of the semiconductor substrate extends downward by a predetermined depth to form the first opening extending downward from the surface of the semiconductor substrate by a predetermined depth. 8. The method of claim 3, wherein forming a gate conductor comprises depositing a first conductive layer to fill the first opening. 9. The method according to claim 3, wherein the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon. 10. The method of claim 3, wherein the depth of the first groove and the second groove is in the range of 0.1 to 50 micrometers. 11. The method according to claim 10, wherein the width of the first trench is greater than or equal to 1.5 times the width of the second trench. 12. The method of claim 11, wherein the width of the first trench is in the range of 0.2 to 10 microns. 13. The method of claim 12, wherein the width of the second trench is in the range of 0.1 to 5 microns. 14. The method according to claim 3, wherein the first doping type is one of N-type and P-type, and the second doping type is the other one of N-type and P-type. 15. The method of claim 1, wherein sidewalls of the first trench are sloped such that a top width of the first trench is greater than a bottom width of the first trench. 16. The method of claim 1, wherein the steps of filling the shield conductor and forming the gate conductor each comprise at least one deposition. 17. A power semiconductor device comprising: a plurality of trenches in a semiconductor substrate, the semiconductor substrate being of a first doping type, the plurality of trenches comprising a first trench of a first size and a second trench of a second size, the a first dimension is greater than said second dimension; a split gate structure in the first trench, the split gate structure comprising a shield conductor, a gate conductor and a second insulating layer sandwiched therebetween; a gate wiring in the second trench, the gate wiring being connected to the gate conductor; a body region located in the semiconductor substrate, the body region is adjacent to the upper portion of the first trench, and has a second doping type, the second doping type is opposite to the first doping type; a source region in the body region, the source region being of the first doping type; a source electrode electrically connected to the source region and the shield conductor; and a gate electrode electrically connected to the gate wiring. 18. The power semiconductor device of claim 17, wherein the split gate structure comprises: an insulation stack located on the lower sidewall and bottom of the first trench, the insulation stack includes a first insulation layer and the second insulation layer, the first insulation layer surrounds the second insulation layer; at least a portion of a shielding conductor located in the first trench, the shielding conductor extending from above the first trench to the bottom thereof, and being isolated from the semiconductor substrate by the insulating stack; gate conductors on both sides of the shield conductor in the upper portion of the first trench; Wherein, the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, and the gate conductor and the body region are isolated from each other by the gate dielectric, so The shielding conductor and the semiconductor substrate are isolated from each other by the insulating layer. 19. The power semiconductor device according to claim 18, wherein the first insulating layer fills a lower portion of the second trench, the gate wiring fills an upper portion of the second trench, and the gate The wiring and the body region are isolated from each other by the gate dielectric. 20. The power semiconductor device of claim 17, wherein the shield conductor extends downward from the surface of the semiconductor substrate to a predetermined depth. 21. The power semiconductor device according to claim 17, wherein the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon . 22. The power semiconductor device according to claim 19, wherein the depth of the first trench and the second trench is in the range of 0.1 to 50 microns. 23. The power semiconductor device according to claim 22, wherein the width of the first trench is greater than or equal to 1.5 times the width of the second trench. 24. The power semiconductor device according to claim 23, wherein the width of the first trench is in the range of 0.2 to 10 microns. 25. The power semiconductor device according to claim 24, wherein the width of the second trench is in the range of 0.1 to 5 microns. 26. The power semiconductor device according to claim 17, wherein the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type kind. 27. The power semiconductor device of claim 17, wherein sidewalls of the first trench are sloped such that a top width of the first trench is greater than a bottom width of the first trench. 28. The power semiconductor device according to claim 17, wherein the power semiconductor device is one selected from CMOS devices, BCD devices, MOSFET transistors, IGBTs and Schottky diodes.