CN111653484B - Method for optimizing self-alignment process of silicon carbide MOSFET - Google Patents

Abstract

The invention discloses a method for optimizing the self-alignment process of silicon carbide MOSFET. This method only uses a layer of P-well mask to etch out the first ion implantation area for forming the P-well; and then through deposition and etching and other processes to form a second ion implantation region in the first ion implantation region for forming the NPlus region and the PPlus region of the stack; finally, a trench with a depth greater than the depth of the NPlus region and less than the depth of the PPlus region is etched grooves to form corresponding PN junctions on the silicon carbide substrate. This method only uses one layer of photomask in the process of forming the P-well, NPlus area and PPlus area, thereby reducing two processes of film deposition, glue coating, exposure, development, glue removal, etc., thus greatly shortening the processing cycle time and reduce manufacturing costs.

Description

A method to optimize the self-alignment process of silicon carbide MOSFETs

Technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for optimizing the self-alignment process of silicon carbide MOSFET.

Background technique

The traditional self-alignment process of silicon carbide MOSFET usually requires three layers of photomasks: Pwell, NPlus, and PPlus, and repeated processes such as film deposition, photolithography, etching, and ion implantation to finally form the corresponding PN junction on silicon carbide. As shown in Figure 1.

From a cost perspective, each additional layer of photomask will increase the manufacturing cost of semiconductor devices; from a processing cycle perspective, each additional layer of photomask will increase the processing time by approximately 7 days. Therefore, it is desired to provide a method for optimizing the self-aligned trench etching process to optimize the above-mentioned self-aligned process, so as to shorten the processing cycle and reduce manufacturing costs.

Contents of the invention

In view of this, it is necessary to provide a method to optimize the self-alignment process of silicon carbide MOSFET, which can eliminate the use of two layers of NPlus and PPlus masks to reduce the corresponding deposition, photolithography, glue coating, exposure, development, glue removal, etc. process, thereby achieving the purpose of reducing manufacturing costs and shortening the processing cycle.

The technical solutions proposed by the present invention to achieve the above objects are as follows:

A method for optimizing the self-alignment process of silicon carbide MOSFET, including the following steps:

S1. Provide a silicon carbide substrate, with a first mask layer deposited on the surface of the silicon carbide substrate;

S2. Perform photolithography on the first mask layer through a P-well mask to etch out a first mask region and a first ion implantation region, and etching the first mask layer through the first mask region. Al ions are injected into the ion implantation area to form a P well;

S3. Deposit a second mask layer, and use dry etching to reverse-etch the second mask layer to form a second ion implantation region and a second mask region;

S4. Inject N ions into the second ion implantation area through the second mask area to form an NPlus area;

S5. Inject Al ions into the second ion implantation area through the second mask area to form a PPlus area. The implantation depth of the PPlus area is greater than the depth of the NPlus area and less than the depth of the P well;

S6. After etching the first mask layer cleanly, sequentially form a second SiO ₂ thin film layer and a gate electrode on the silicon carbide substrate, and use photolithography and etching processes to form a second SiO ₂ film layer on the silicon carbide substrate. An etched area is formed on the thin film layer and the gate electrode;

S7. Deposit an interlayer dielectric layer, and use dry etching to etch the interlayer dielectric layer and the silicon carbide substrate in the etching area to form a trench. The depth of the groove is greater than the depth of the NPlus region and less than the depth of the PPlus region;

S8. Deposit the source metal so that the source metal forms good ohmic contact with the NPlus region and the PPlus region.

Further, in step S1, the first mask layer includes a first SiO ₂ thin film layer and a polysilicon layer, and the first SiO ₂ thin film layer is located between the silicon carbide substrate and the polysilicon layer.

Further, in step S3, the second mask layer at the bottom of the second ion implantation region is etched cleanly to expose the upper surface of the silicon carbide substrate, leaving only the sidewalls of the second ion implantation region. a second mask layer to form the second mask area.

Further, the method used to deposit the second mask layer in step S3 is a low pressure chemical vapor deposition method.

Further, the material of the second mask layer in step S3 is silicon oxide.

Further, in step S6, the etching region and the second ion implantation region are on the same center line, and the width of the etching region is smaller than the width of the second ion implantation region.

Further, the material of the gate electrode in step S6 is polysilicon.

Further, in step S8, a wet etching method is used to etch the interlayer dielectric layer above the NPlus region, so that a step is formed between the NPlus region and the interlayer dielectric layer.

The above-mentioned method of optimizing the self-alignment process of silicon carbide MOSFET is to only use a layer of P-well mask to etch out the first ion implantation area to form the P-well; and then use deposition, etching and other processes to create the first ion implantation area. A second ion implantation region is formed in the region to form the NPlus region and PPlus region of the stack; finally, a trench with a depth greater than the depth of the NPlus region and less than the depth of the PPlus region is etched to form a groove on the silicon carbide substrate. A corresponding PN junction is formed on it. This method only uses one layer of photomask in the process of forming the P-well, NPlus area and PPlus area, thereby reducing two processes of film deposition, glue coating, exposure, development, glue removal, etc., thus greatly shortening the processing cycle time and reduce manufacturing costs.

Description of drawings

Figure 1 is a self-alignment process diagram of silicon carbide MOSFET devices in the prior art.

Figure 2-10 is a schematic cross-sectional structural diagram of the process of a method for optimizing the self-alignment process of silicon carbide MOSFET according to the present invention.

Description of main component symbols

Silicon carbide substrate 10

P trap 12

NPlus area 14

PPlus area 16

First mask layer 20

First _SiO2 thin film layer 21

First mask area 22

Polysilicon layer 23

First ion implantation area 24

Second mask layer 30

Second ion implantation area 32

Second mask area 34

Second _SiO2 thin film layer 40

Gate electrode 50

Etched area 60

Interlayer dielectric layer 70

Groove 80

Source metal 90

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

The present invention provides a method for optimizing the self-alignment process of silicon carbide MOSFET. Referring to Figures 2 to 10, a method for optimizing a silicon carbide MOSFET self-alignment process according to a preferred embodiment of the present invention includes the following steps:

S1. As shown in FIG. 2 , a silicon carbide substrate 10 is provided, and a first mask layer 20 is deposited on the surface of the silicon carbide substrate 10 . In this embodiment, the first mask layer 20 includes a first SiO ₂ thin film layer 21 and a polysilicon layer 23. The first SiO ₂ thin film layer 21 is located between the silicon carbide substrate 10 and the polysilicon layer 23. between.

S2. As shown in Figure 3, photolithography is performed on the first mask layer 20 through a P-well mask to etch out the first mask region 22 and the first ion implantation region 24, and pass through the first In the mask region 22 , Al ions are implanted into the first ion implantation region 24 to form the P well 12 .

S3. As shown in FIGS. 4 to 5 , deposit the second mask layer 30 , and use dry etching to reverse-etch the second mask layer 30 to form the second ion implantation region 32 and the second ion implantation region 32 . Mask area 34. Specifically, the second mask layer at the bottom of the second ion implantation region 32 is etched cleanly to expose the upper surface of the silicon carbide substrate 10 , leaving only the second mask layer on the sidewall of the second ion implantation region 32 . A mask layer is formed to form the second mask area 34 .

In this embodiment, the material of the second mask layer 30 is silicon oxide. In other embodiments, the material of the second mask layer 30 may also be one of silicon oxide, polysilicon, and silicon nitride. species or any combination of species. In this embodiment, the method used to deposit the second mask layer 30 is low pressure chemical vapor deposition (LPCVD).

S4. As shown in FIG. 6 , N ions are implanted into the second ion implantation region 32 through the second mask region 34 to form the NPlus region 14 .

S5. As shown in FIG. 7 , Al ions are implanted into the second ion implantation region 32 through the second mask region 34 to form the PPlus region 16 , and the implantation depth of the PPlus region 16 is greater than the NPlus region 14 The depth is smaller than the depth of the P-well 12 .

S6. As shown in Figure 8, after the first mask layer 20 is etched cleanly, a second _SiO2 thin film layer 40 is formed on the silicon carbide substrate 10 through a growth or deposition process (equivalent to the layer in Figure 1 Gate SiO ₂ ) and the gate electrode 50 (equivalent to the Poly layer in FIG. 1 ), and through photolithography and etching processes, an etching region is formed on the second SiO ₂ thin film layer 40 and the gate electrode 50 60.

In this embodiment, the etching region 60 and the second ion implantation region 32 share a center line, and the width of the etching region 60 is smaller than the width of the second ion implantation region 32 .

In this embodiment, the gate electrode 50 is made of polysilicon.

S7. As shown in Figure 9, deposit the interlayer dielectric layer 70, and use dry etching to etch the interlayer dielectric layer 70 and the silicon carbide substrate 10 in the etching area 60. , to form a trench 80. The depth of the trench 80 is greater than the depth of the NPlus region 14 and less than the depth of the PPlus region 16 .

S8. As shown in Figure 10, wet etching is used to etch the interlayer dielectric layer 70 above the NPlus region 14, so that a step is formed between the NPlus region 14 and the interlayer dielectric layer 70. , and deposit the source metal 90 , photolithography and high-temperature alloying, so that the source metal 90 forms good ohmic contact with the NPlus region 14 and the PPlus region 16 .

To sum up, the method of optimizing the self-alignment process of silicon carbide MOSFET of the present invention is to only use a layer of P-well mask to etch out the first ion implantation region 24 to form the P-well 12; and then through deposition, Etching and other processes form the second ion implantation region 32 in the first ion implantation region 24 for forming the NPlus region 14 and the PPlus region 16 of the stack; finally, etching is performed to a depth greater than the depth of the NPlus region 14 and less than the depth of the NPlus region 14 . The depth of the trench 80 in the PPlus region 16 is to form a corresponding PN junction on the silicon carbide substrate 10 . This method uses only one photomask in the process of forming the P-well 12, the NPlus region 14 and the PPlus region 16, thereby reducing two processes of film deposition, glue coating, exposure, development, glue removal, etc., so that it is extremely cost-effective. Dadi shortens the processing cycle and reduces manufacturing costs.

The above content is a further detailed description of the present invention in combination with specific/preferred embodiments, and it cannot be concluded that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, they can also make several substitutions or modifications to the described embodiments without departing from the concept of the present invention, and these substitutions or modifications should be regarded as belong to the protection scope of the present invention. In the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "preferred embodiments," "examples," "specific examples," or "some examples" is intended to be in conjunction with the implementation. An example or example describes a specific feature, structure, material, or characteristic that is included in at least one embodiment or example of the invention. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Claims (6)

1. A method for optimizing a silicon carbide MOSFET self-alignment process, comprising the steps of:

s1, providing a silicon carbide substrate, wherein a first mask layer is deposited on the surface of the silicon carbide substrate;

s2, photoetching the first mask layer through a P well photomask to etch a first mask region and a first ion implantation region, and implanting Al ions into the first ion implantation region through the first mask region to form a P well;

s3, depositing a second mask layer, and performing back etching on the second mask layer by adopting a dry etching method to form a second ion implantation region and a second mask region;

s4, implanting N ions into the second ion implantation region through the second mask region to form an NPlus region;

s5, injecting Al ions into the second ion injection region through the second mask region to form a PPlus region, wherein the NPlus region and the PPlus region are vertically stacked, and the injection depth of the PPlus region is greater than the depth of the NPlus region and less than the depth of the P well;

s6, etching the first mask layer completely and sequentially forming a second SiO on the silicon carbide substrate ₂ A thin film layer and a gate electrode, and performing photolithography and etching processes to obtain a first SiO layer ₂ Forming an etching area on the film layer and the gate electrode;

s7, depositing an interlayer dielectric layer, and etching the interlayer dielectric layer and the silicon carbide substrate in the etching area by adopting a dry etching method to form a groove, wherein the depth of the groove is larger than that of the NPlus area and smaller than that of the PPlus area;

s8, depositing source metal, so that the source metal forms good ohmic contact with the NPlus region and the PPlus region;

in step S6, the etching region and the second ion implantation region are concentric, and the width of the etching region is smaller than the width of the second ion implantation region;

in step S8, an interlayer dielectric layer above the NPlus region is etched by a wet etching method, so that a step is formed between the NPlus region and the interlayer dielectric layer.

2. The method of optimizing a silicon carbide MOSFET self-alignment process according to claim 1, wherein in step S1, the first mask layer comprises a first SiO ₂ A film layer and a polysilicon layer, the first SiO ₂ The thin film layer is positioned between the silicon carbide substrate and the polysilicon layer.

3. The method of optimizing a silicon carbide MOSFET self-alignment process of claim 1, wherein in step S3, the second mask layer at the bottom of the second ion implantation region is etched clean to expose the upper surface of the silicon carbide substrate, leaving only the second mask layer on the sidewalls of the second ion implantation region to form the second mask region.

4. The method of optimizing a silicon carbide MOSFET self-aligned process of claim 1, wherein the method used to deposit the second mask layer in step S3 is a low pressure chemical vapor deposition method.

5. The method of optimizing a silicon carbide MOSFET self-alignment process of claim 1, wherein said second mask layer material in step S3 is silicon oxide.

6. The method of optimizing a silicon carbide MOSFET self-alignment process of claim 1, wherein said gate electrode materials in step S6 are all polysilicon.