TW486778B - Method to prevent current leakage at edge of shallow trench isolation - Google Patents

Abstract

This invention provides a method to prevent current leakage at edge of shallow trench isolation on a semiconductor wafer. The semiconductor wafer includes a silicon substrate and a plural number of shallow trenches filled with silicon oxide material formed by high-density plasma chemical vapor deposition (HDPCVD). A phosphorus silicate glass or silicon oxide layer deposited by atmospheric pressure chemical vapor deposition (APCVD) is formed on the semiconductor wafer. A pattern is defined on the photoresist layer for the formation of salicide barrier (SAB). Then, the wafer is heated and a hydrofluoric acid vapor is used to etch the silicon oxide layer along the patterned photoresist to increase the etching selectivity of the silicon oxide layer with respect to the silicon oxide material at the edge of the shallow trench isolation and thus to expose part of the substrate surface pre-determined for the formation of a metal silicide layer. This also concurrently reduces loss of silicon oxide material at the edge of the shallow trench isolation and effectively decreases junction leakage of devices. Finally, a self-aligned metal silicide (salicide) process is carried out to form the salicide layer on the pre-determined area on the substrate surface.

Description

486778 V. Description of the invention (1) Field of the invention The present invention provides a method 4 for reducing the leakage current at the edge of shallow trench isolation, especially a shallow trench isolation (STI) edge in an electrostatic discharge (ESD) protection circuit. Leakage current (current 1 eakage) method. Background In current semiconductor processes, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) methods are generally used to isolate components. However, as the design and manufacturing line widths of semiconductor wafers become thinner, the pits, crystal defects, and bird's beak lengths generated in the L 0 C 0 S process have become too long. The shortcomings such as length will greatly affect the characteristics of the semiconductor wafer, and the field oxide layer produced by the LOCOS method occupies a larger volume and will affect the integration of the entire semiconductor wafer. Therefore, in semiconductor processes with a line width of less than 0.25 // m, the shallow trench isolation (STI) process, which has a small size and can improve the semiconductor wafer accumulation, has recently become a widely used isolation technology. A typical STI manufacturing method is to etch a silicon substrate downwards between each active area on the surface of a semiconductor wafer to form a shallow trench.

486778 V. Description of the invention (2) and filled with an insulating substance composed of silicon oxide (s i 1 i c ο η ο X i d e) to isolate the active area for subsequent semiconductor processes. However, in subsequent processes, the ion implantation (i on i mp 1 an t) of, for example, N-well (N-we 1.1) or P-well (P-we 1 1) is performed repeatedly on the semiconductor wafer or The cleaning process before the gate oxide layer is generated, and the steps such as metal silicide barrier, salicide barrier (SAB) etching, etc., are very easy to destroy the structure of the top edge of the shallow trench during these manufacturing processes. Taking the formation of a metal debris resist layer as an example, in the process of electrostatic discharge (ESD), the gate and source / drain surfaces of some regions do not need to form metal silicide, so this process is being carried out. Before the metal silicide process (salicide) is aligned, a metal stone barrier layer must be formed on the surface of this area to prevent the surface of the material in the area from being covered with a metal layer. At the same time, a metal silicide layer is formed. However, in the current semiconductor manufacturing process, both the metal silicide barrier layer and the shallow trench filling material are composed of silicon oxide compounds. Therefore, when the metal silicide barrier layer is etched, too much silicon oxide material is often lost at the edge of the shallow trench. Further, a phenomenon of current leakage occurs. Please refer to FIGS. 1 to 4, which are schematic diagrams of a conventional method for manufacturing an electrostatic discharge protection circuit. As shown in FIG. 1, the semiconductor wafer 10 includes an N-type silicon substrate 12. A plurality of active regions are disposed on the surface of the silicon substrate 12. The plurality of active regions are filled with atmospheric chemical vapor deposition. (atmospheric pressure chemical vap〇r deposition (APCVD))

486778 V. Description of the invention (3) A shallow trench 14 on the surface of the silicon substrate 12 is provided between the two active regions 11 and a P-type doped region 16 is provided on the silicon substrate 1 2 adjacent to the shallow trenches 1 2 The surface and a 500 angstrom silicon oxide layer 20 formed by low pressure chemical vapor deposition (LPCVD) are covered on the top surfaces of the P-type doped regions 16 and the shallow trenches 14. A photoresist layer 22 is then coated on the semiconductor wafer 10 to define a pattern in the photoresist layer 22 for use as a salicide barrier (SAB). As shown in FIG. 2, a dry-etching process is then used to etch down a part of the silicon oxide layer 20 covering the surface of the silicon substrate 12 along the pattern of the photoresist layer 22 to make it remain on the semiconductor wafer. The silicon oxide layer 20 on the surface 10 forms a metal silicide blocking layer 21, as shown in FIG. However, because the dry etching has a poor selection ratio of the silicon oxide material 18 in the shallow trench and the silicon oxide layer 20, the silicon oxide material 18 in the shallow trench corner 24 is often lost by etching erosion. Finally, as shown in FIG. 4, after the photoresist layer 22 is removed, a self-aligning metal salicide process is performed on the surface of the semiconductor wafer 10 to cover the surface of the silicon material not covered with the silicon oxide layer 20. A metal silicide layer 26 is formed, and then an unreacted metal layer (not shown) is removed to complete a conventional electrostatic protection circuit process. · From the above description, it is known that the #etching process of the metal oxide barrier layer that is conventionally implemented in the electrostatic protection circuit process uses a dry method to etch the silicon oxide layer 2 0, but because of the shallow trench silicon oxide Material 18 and silicon oxide layer are both dioxygen

486778 V. Description of the invention (4) Siliconized structure, so in the 0.2 5 // m process, this etching process often loses too much silicon oxide material at the shallow groove corners near the active area, resulting in Shallow trench isolation is not complete, causing a large bonding leakage current, which in turn affects the electrical performance of the component. SUMMARY OF THE INVENTION The main object of the present invention is to provide a manufacturing method for reducing the leakage current of a shallow trench isolation edge on a semiconductor wafer to solve the above problems. In a preferred embodiment of the present invention, the semiconductor wafer includes a silicon substrate and a plurality of shallow trench isolations filled with a silicon-oxygen material formed by a high-density plasma chemical vapor deposition (HD PC VD) method. In this method, a silicon oxide layer is firstly formed using a phosphorite glass or an atmospheric pressure chemical vapor deposition method is used to form a silicon oxide layer on the surface of the semiconductor wafer, and a photoresist layer is formed on the surface of the silicon oxide layer. Then define a pattern on the surface of the photoresist layer to serve as a metal oxide barrier (Sab), and then heat the semiconductor wafer, and use a vapor of hydrofluoric acid to follow the pattern of the photoresist layer. #Etch the stone oxidant layer to increase the etching selection ratio of the silicon oxylayer to each of the shallow trench isolation edges, and then expose a portion of the substrate surface intended to form a metal silicide layer, while reducing each The loss of silicon horse material at the edge of the shallow trench isolation to effectively reduce the junction leakage current of conventional components. Finally, an automatic alignment metal silicide process (s a 1 i c i d e) is performed, and the metal silicide layer is formed on a part of the surface of the substrate that is intended to form the metal silicide layer.

486778 V. Description of the invention (5) Because the present invention uses hydrofluoric acid (HF) vapor and simultaneously raises the temperature of the semiconductor wafer to etch the silicon oxide layer to increase the silicon oxide layer and the silicon at the edges of the shallow trench isolation. The etching selection ratio of the oxygen material further reduces the loss of the silicon oxide material at each of the shallow trench isolation edges, so as to effectively reduce the joint leakage current of the conventional device. Detailed description of the invention Please refer to FIG. 5 to FIG. 9, FIG. 5 to FIG. 9 are schematic diagrams of a method for manufacturing an electrostatic discharge protection circuit according to the present invention. As shown in FIG. 5, the semiconductor wafer 30 includes an N-type silicon substrate 3 2, a plurality of active regions 31 are provided on the surface of the silicon substrate 3 2, and a plurality of shallow trenches having a depth of 3 0 0 0 to 4 0 0 0 angstroms. 3 4 is disposed on the silicon substrate 32 to isolate the two active regions 31 and slightly protrude from the surface of the silicon substrate 32. A P-type doped region 36 is disposed on the silicon substrate 3 adjacent to the two shallow trenches 34. 2 surface. Among them, the shallow trench 34 is filled with a high-density silicon-oxygen material 38 formed by high-density plasma chemical vapor deposition (HDPCVD). Next, as shown in FIG. 6, an atmospheric pressure chemical vapor deposition (APCVD) or phosphosilicate glass (PSG) is used to form a silicon oxide layer 40 of about 50 angstroms on the surface of the semiconductor wafer 30. Covering the top surfaces of the P-type doped regions 36 and the shallow trenches 3 4. Then, a photoresist layer 42 is coated on the semiconductor wafer 30, and the photoresist layer is

486778 V. Description of the invention (6) 4 2 defines a pattern used as a metal silicide barrier, as shown in Figure 7. Then, the temperature of the semiconductor wafer was increased from 25 ° C to about 50 ° C, and a vapor formed by a hydrofluoric acid (hydr ogenf 1 u ride, HF) with a water ratio of 1: 100 was used ( vapor) along the pattern to engrav the stone oxide layer 4 0 to expose the top surface of the shallow trench 34 and the surface of the silicon substrate 32 which is intended to form a metal silicide layer and to make the remaining silicon The oxygen layer 40 forms a metal silicide barrier layer 41, as shown in FIG. Because the method of the present invention has a better process etching ratio, when the metal silicide barrier (SAB) etching process is performed, the 4 and 4 portions at the shallow groove corners will be more than the shallow groove corners in the conventional process. Position 2 4 is intact and is not easily eroded by hydrofluoric acid (HF) vapor 38. Finally, the photoresist layer 42 is removed, and a self-aligned metal silicidation process is performed to form a metal silicide layer 46 on the surface of the material of the stone material which is not covered with the stone material oxygen layer 40. The self-aligned metal silicidation process is to first deposit a metal layer of cobalt (Cobalt, Co), titanium (Titanium, Ti), Nicole, Ni, or tungsten (Tungsten, W) on the surface of the semiconductor wafer 30 ( (Not shown), and then a thermal process is performed to react the Shi Xi substrate 32 not covered with the Shi Xi oxygen layer 40 with the metal layer, so that the surface of the semiconductor wafer 30 is intended to form a metal silicide. Partially formed metal silicide 46, as shown in Figure IX. The unreacted metal layer is subsequently removed by wet etching to complete the fabrication of the present invention. The method of the present invention is not limited to use in electrostatic protection circuits, and other methods are used in semiconductor processes.

486778 V. Description of the invention (7) When the silicon oxide layer covering the shallow trench isolation surface needs to be etched, the method of the present invention can be applied. Since the present invention first uses HDPCVD to form a denser silicon oxide material 38 to fill the shallow trenches 34, and then uses / forms a less dense silicon oxide layer 40 formed using APCVD or PSG as a metal The silicide barrier layer (SAB), so the etching selection ratio between the two can be as high as 1: 100 to 1: 2900. Then, the present invention further uses hydrofluoric acid vapor and simultaneously applies a heating process to the semiconductor wafer 30, so that in subsequent etching, the silicon oxide layer 40 can be accurately etched without damaging the shallow trench corner 4 4 Silicone material 3 8 near active area 3 1. Compared with the conventional method of removing silicon oxide layer 20 by dry etching, the present invention uses gas-phase hydrofluoric acid for etching, and simultaneously changes the temperature of the wafer during etching, and is then matched with a high etching selection ratio. The silicon oxide material and the silicon oxide layer can effectively inhibit the silicon oxide material at the edge of the shallow trench close to the active area from being excessively eroded during the etching process, thereby greatly improving the joint leakage current problem of the existing process. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 12 486778 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 show the methods of making an electrostatic discharge protection circuit in the conventional way. 5 to 9 are schematic diagrams of a method for manufacturing an electrostatic discharge protection circuit according to the present invention. Symbols shown in the figure 10 \ 30 Semiconductor wafer 11 Active area 12 '32 Silicon substrate 14, 34 Isolation shallow trench 16 ^ 36 P-type doped region 18, 38 Silicon oxide material 20 > 40 Silicon oxide layer 21 > 41 Metal Silicide blocking layer 11, 42 Photoresisting layer 24 ^ 44 Shallow groove corner 26 > 36 Metal silicide layer

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Claims (1)

486778 VI. Scope of patent application 1. A method for reducing shallow trench isolation (STI) edge leakage current in an electrostatic discharge (ESD) protection circuit on a semiconductor wafer. The substrate comprises a substrate, the shallow trench isolation is provided on the substrate, and it is filled with a silicon oxide material deposited by a high density plasma chemical vapor deposition (HDP CVD) method. The method includes: forming a silicon oxide layer on the substrate surface and the top surface of the shallow trench isolation; the silicon oxide layer is composed of phosphosilicate glass (PSG) or an atmospheric pressure vapor deposition method (atmospheric pressure) CVD, APCVD) deposition; forming a photoresist on the surface of the silicon oxide layer; defining a pattern on the surface of the photoresist layer for use as a metal silicide barrier (SAB) Warming the semiconductor wafer 'and using a hydrofluoric acid gas (Hp) to etch the silicon oxide layer along the pattern of the photoresist layer to make the shallow The top surface of the trench isolation and a portion of the substrate surface intended to form a metal silicide layer are exposed; and the metal silicide layer is formed on a portion of the substrate surface intended to form a metal silicide layer. 2. The method according to item 1 of the patent application, wherein the thickness of the silicon oxide layer is about 500 angstroms (angstrom). 486778 VI. Patent Application Range 3. The method of applying for the first item of the patent application range, wherein the step of heating the semiconductor wafer is about heating the semiconductor wafer from 25 ° C to 50 ° C. '4. The method according to item 1 of the scope of patent application, wherein the ratio of the hydrofluoric acid to water is about 1 ·· 10 0 〇5. A method to reduce the shallow trench isolation on a semiconductor wafer (sha 1 10w trench isolation (STI) method for edge leakage current, the semiconductor wafer includes a substrate, and the shallow trench isolation is provided on the substrate, the method includes: on the surface of the substrate and on top of the shallow trench isolation A silicon oxide layer is formed on the surface; a photoresist is formed on the surface of the silicon oxide layer; a mask pattern is defined on the surface of the photoresist layer; the semiconductor wafer is heated, and Using a hydrofluoric acid gas (HF) to etch the silicon oxide layer along the pattern of the photoresist layer, so that the shallow trench isolates the top surface and a portion of the surface of the substrate that is intended to form a metal silicide layer; and The metal silicide layer is formed on a part of the surface of the substrate intended to form the metal silicide layer. 6. The method of claim 5 in which the shallow trench is isolated and I 486778 VI. Scope of patent application The metal oxide layer is used in an electrostatic discharge (ESD) protection circuit. 7. The method according to item 5 of the scope of patent application, wherein the etching selection ratio of the silicon-oxygen material filled in the shallow trench isolation and the silicon-oxygen layer is about 1: 1 0 0 to 1: 2 9 0. 8. The method according to item 5 of the patent application, wherein the silicon oxide material filled in the shallow trench isolation is deposited using a high-density plasma chemical vapor deposition (HDP CVD) method. to make. 9. The method according to item 5 of the patent application, wherein the silicon-oxygen layer is composed of phosphor-silicone glass (PSG) or is deposited by atmospheric pressure CVD (APCVD). 10 · The method according to item 5 of the patent application, wherein the thickness of the silicon oxide layer is about 500 angstroms. 1 1. The method according to item 5 of the scope of patent application, wherein the step of heating the semiconductor wafer is about heating the semiconductor wafer from 25 ° C to 50 ° C. -1 2 · The method according to item 5 of the patent application, wherein the hydrofluoric acid and water 486778 6. The scope of patent application is about 1: 1 0 0.