CN105185831A - Silicon carbide MOSFET structure with self-aligned channel and manufacturing method thereof - Google Patents

Abstract

The invention discloses a silicon carbide MOSFET structure with a self-aligned channel and a manufacturing method thereof. The silicon carbide MOSFET structure P ⁺ is contacted in a groove between N ⁺ source mesas, and is in multi-surface contact with a P-type base region; On the N- epitaxial wafer ^, use a polysilicon mask ion implantation to form a P-type base region; deposit SiO ₂ on the polysilicon and etch to form side walls, and use a self-alignment process to implant in the P-type base region to form N ⁺ Source region; the N ⁺ source region is partially etched to the P-type base region, and ion implantation forms a P ⁺ contact in the etched area; the device uses an alloy self-alignment process to form a source-drain ohmic contact; the N ⁺ One end of the substrate is used as a drain, one end of the gate dielectric layer is used as a gate, and one end of the P ⁺ region and the N ⁺ region is used as a source. The invention avoids the use of stripping technology and metal as the ion implantation blocking layer, and can reduce one photolithography compared with the traditional technology, and improves the precision of the boundary of the P ⁺ contact area.

Description

A kind of channel self-aligned silicon carbide MOSFET structure and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a channel self-aligned silicon carbide MOSFET structure and a manufacturing method thereof.

Background technique

Silicon carbide material has excellent physical and electrical properties. With its unique advantages such as large band gap, high critical breakdown electric field, high thermal conductivity and high saturation drift speed, it has become a high-voltage, high-power, high-temperature-resistant, high-frequency, anti- It is an ideal semiconductor material for irradiation devices and has broad application prospects in military and civil affairs. Power electronic devices made of silicon carbide materials have become one of the hot devices and frontier research fields in the field of semiconductors.

Silicon carbide MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) has the advantages of low on-resistance, fast switching speed, and high temperature reliability, and is expected to become the next generation of high-voltage power switching devices.

In order to improve the current control capability of silicon carbide MOSFET, the shorter the channel length of the device, the better. Considering the environmental and human influence in the photolithography process, the channel with a length of less than 0.5 μm adopts the channel self-alignment process. In the existing channel self-alignment process, before the ion implantation of the N ⁺ source region, a metal mask is formed in the P ⁺ contact area by the stripping process, which is used as a barrier layer for the ion implantation of the P + area to block the N + implantation. This method introduces a stripping process. The process is not compatible with the existing silicon process, and the metal barrier layer used in the high-temperature ion implantation process will pollute the surface of the device and the ion implanter. As shown in FIG. 1 to FIG. 3 , they are flow charts of the channel self-alignment process of the silicon carbide MOSFET device in the prior art.

Contents of the invention

The invention provides a channel self-aligned silicon carbide MOSFET structure and its manufacturing method, which can avoid the use of stripping process and metal as ion implantation barrier layer, and can reduce one photolithography compared with the traditional process, and improve the P ⁺ contact area The precision of the boundaries.

For reaching above-mentioned purpose, the present invention adopts following technical scheme:

A channel self-aligned silicon carbide MOSFET structure, the silicon carbide MOSFET structure P ⁺ contacts in the groove between N ⁺ source mesas, and multi-faceted contact with the P-type base region;

On the N ^- epitaxial wafer, use polysilicon mask ion implantation to form a P-type base region;

_SiO2 is deposited on the polysilicon and etched to form sidewalls, and a self-aligned process is used to implant in the P-type base region to form an N ⁺ source region;

The N ⁺ source region is partially etched to the P-type base region, and ion implantation is performed in the etched region to form a P ⁺ contact region;

The source-drain ohmic contact is formed by alloy self-alignment process;

One end of the N ⁺ substrate is used as a drain, one end of the gate dielectric layer is used as a gate, and one end of the P ⁺ region and the N ⁺ region is used as a source.

Optionally, the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm.

Optionally, using a channel self-alignment process, multiple nitrogen implants are used to form an N ⁺ source region and a channel smaller than 0.5 μm.

Optionally, the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact region.

Optionally, the N ⁺ substrate, N ⁻ epitaxy, P type base region, P ⁺ contact region and N ⁺ source region are all made of silicon carbide.

A method for manufacturing a channel self-aligned silicon carbide MOSFET, comprising:

Cleaning silicon carbide epitaxial wafers;

Depositing a layer of 2 μm PolySi on the silicon carbide epitaxial wafer;

Etching 2μm PolySi to form an ion implantation barrier;

Aluminum implantation forms a P-type base region;

Deposit 800nm SiO ₂ ;

Uniform photoresist on the 800nm _SiO2 layer, and photolithographically develop the N ⁺ injection window;

Photoresist mask etching 800nm SiO ₂ to form side walls;

Ion implantation forms the N ⁺ source region;

Removal of PolySi and SiO ₂ ;

Deposit 2.5 μm SiO ₂ ;

Uniform photoresist on the 2.5 μm SiO ₂ layer, and develop a P ⁺ injection window by photolithography;

Photoresist mask etching 2.5μm SiO ₂ ;

Photoresist and SiO ₂ combined mask etching silicon carbide;

remove photoresist;

Aluminum implant to form P ⁺ contact area;

Remove _SiO2 and perform ion implantation activation annealing;

Gate oxide formation and polysilicon deposition and patterning;

Interlayer dielectric deposition and etching holes;

Sputtering front and back ohmic contact, and annealing to form ohmic alloy;

Corrosion of unalloyed metals;

The metal on the front and back is thickened.

Optionally, the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm.

Optionally, using a channel self-alignment process, multiple nitrogen implants are used to form an N ⁺ source region and a channel smaller than 0.5 μm.

Optionally, the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact region.

Optionally, the N ⁺ substrate, N ⁻ epitaxy, P type base region, P ⁺ contact region and N ⁺ source region are all made of silicon carbide.

The channel self-aligned silicon carbide MOSFET structure and its manufacturing method provided by the embodiments of the present invention form a P ⁺ contact layer by ion implantation after etching the N ⁺ source region, without using a stripping process and metal as an ion implantation barrier layer, Compatible with the existing silicon process, the same mask layer is used to etch the N ⁺ region mask and the ion implantation barrier, which can improve the alignment accuracy, and at the same time reduce one photolithography, and the P ⁺ contact and the P-type base area are more fully contacted. Improves the precision of the P ⁺ contact boundary to further suppress parasitic bipolar transistor effects.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

1 to 3 are flow charts of the channel self-alignment process of silicon carbide MOSFET devices in the prior art;

4 is a flowchart of a method for manufacturing a silicon carbide MOSFET with self-aligned channels according to an embodiment of the present invention;

5 to 18 are schematic structural views obtained after performing various process steps in the method for manufacturing a silicon carbide MOSFET with a self-aligned channel according to an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 18, an embodiment of the present invention provides a silicon carbide MOSFET structure with a self ^- aligned channel ^. multifaceted contact

On the N ^- epitaxial wafer, use polysilicon mask ion implantation to form a P-type base region;

_SiO2 is deposited on the polysilicon and etched to form sidewalls, and a self-aligned process is used to implant in the P-type base region to form an N ⁺ source region;

The N ⁺ source region is partially etched to the P-type base region, and ion implantation is performed in the etched region to form a P ⁺ contact region;

The source-drain ohmic contact is formed by alloy self-alignment process;

One end of the N ⁺ substrate is used as a drain, one end of the gate dielectric layer is used as a gate, and one end of the P ⁺ region and the N ⁺ region is used as a source.

Optionally, the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm.

Optionally, using a channel self-alignment process, multiple nitrogen implants are used to form an N ⁺ source region and a channel smaller than 0.5 μm.

Optionally, the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact region.

Optionally, the N ⁺ substrate, N ⁻ epitaxy, P type base region, P ⁺ contact region and N ⁺ source region are all made of silicon carbide.

The channel self-aligned silicon carbide MOSFET structure provided by the embodiment of the present invention forms the P ⁺ contact layer by ion implantation after etching the N ⁺ source region, and does not need to use a lift-off process and metal as an ion implantation barrier layer, which is different from the existing Compatible with silicon process, the same mask layer is used to etch the N ⁺ area mask and ion implantation block, which can improve the alignment accuracy, and at the same time reduce one photolithography, the P ⁺ contact is more fully in contact with the P-type base area, and the P ⁺ contact is improved The accuracy of the region boundaries further suppresses parasitic bipolar transistor effects.

As shown in FIG. 4, an embodiment of the present invention also provides a method for manufacturing a silicon carbide MOSFET with a self-aligned channel, including the following steps:

Step S101, cleaning the silicon carbide epitaxial wafer to obtain the structure shown in Figure 5;

Step S102, depositing 2 μm PolySi on the silicon carbide epitaxial wafer and etching to form an ion implantation barrier layer to obtain the structure shown in Figure 6;

Step S103, forming the Pbase region by implanting aluminum ions to obtain the structure shown in Figure 7;

Step S104, depositing 800nm SiO ₂ to obtain the structure shown in Figure 8;

Step S105, etching 800nm SiO ₂ , forming sidewalls, and performing nitrogen ion implantation to form N+ source regions, to obtain the structure shown in FIG. 9 ;

Step S106, removing PolySi and SiO ₂ , depositing 2.5 μm SiO ₂ and uniform photoresist to obtain the structure shown in FIG. 10 ;

Step S107, develop the preliminary P ⁺ implantation window by photolithography, and at the same time perform photoresist mask etching of SiO ₂ to obtain the structure shown in Figure 11;

Step S108, photoresist and _SiO2 combination mask etching silicon carbide, to obtain the structure shown in Figure 12;

Step S109, forming a P+ contact by implanting aluminum ions to obtain a structure as shown in FIG. 13 ;

Step S110, after removing the _SiO2 mask, perform ion implantation activation annealing and gate oxide oxidation to obtain the structure shown in Figure 14;

Step S111, polysilicon deposition and patterning, to obtain the structure shown in Figure 15;

Step S112, interlayer dielectric deposition and etching opening, to obtain the structure shown in Figure 16;

Step S113, forming a source-drain ohmic alloy by an alloy self-alignment process to obtain a structure as shown in FIG. 17 ;

Step S114 , thicken the metal on the front and back, and obtain the structure shown in FIG. 18 .

So far, a complete channel self-aligned silicon carbide MOSFET has been fabricated.

Optionally, the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm.

Optionally, using a channel self-alignment process, multiple nitrogen implants are used to form an N ⁺ source region and a channel smaller than 0.5 μm.

Optionally, the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact region.

Optionally, the N ⁺ substrate, N ⁻ epitaxy, P type base region, P ⁺ contact region and N ⁺ source region are all made of silicon carbide.

The method for manufacturing a silicon carbide MOSFET with a self-aligned channel provided in an embodiment of the present invention forms a P ⁺ contact layer by etching the N ⁺ source region and then implanting an ion, without using a lift-off process and using a metal as an ion implantation barrier, which is different from the existing Compatible with some silicon processes, the same mask layer is used to etch the N ⁺ region mask and the ion implantation barrier, which can improve the alignment accuracy and reduce one photolithography ^{. +} The precision of the boundary of the contact area further suppresses the parasitic bipolar transistor effect.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A silicon carbide MOSFET structure with self-aligned channels, characterized in that, the silicon carbide MOSFET structure P ⁺ contacts are in the groove between the N ⁺ source mesas, and are in multi-surface contact with the P-type base region; On the N ^- epitaxial wafer, use polysilicon mask ion implantation to form a P-type base region; _SiO2 is deposited on the polysilicon and etched to form sidewalls, and a self-aligned process is used to implant in the P-type base region to form an N ⁺ source region; The N ⁺ source region is partially etched to the P-type base region, and ion implantation is performed in the etched region to form a P ⁺ contact region; The source-drain ohmic contact is formed by alloy self-alignment process; One end of the N ⁺ substrate is used as a drain, one end of the gate dielectric layer is used as a gate, and one end of the P ⁺ region and the N ⁺ region is used as a source. 2 . The silicon carbide MOSFET structure with self-aligned channel according to claim 1 , wherein the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm. 3 . 3 . The silicon carbide MOSFET structure with self-aligned channel according to claim 1 , characterized in that an N ⁺ source region and a channel smaller than 0.5 μm are formed by multiple nitrogen implantations using a channel self-aligned process. 4 . 4. The silicon carbide MOSFET structure with self-aligned channel according to claim 1, characterized in that, the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact region . 5. The channel self-aligned silicon carbide MOSFET structure according to any one of claims 1 to 4, wherein the N ⁺ substrate, N ^- epitaxy, P-type base region, P ⁺ contact region and The N ⁺ source regions are all silicon carbide materials. 6. A method for manufacturing a channel self-aligned silicon carbide MOSFET, characterized in that it comprises: Cleaning silicon carbide epitaxial wafers; Depositing a layer of 2 μm PolySi on the silicon carbide epitaxial wafer; Etching 2μm PolySi to form an ion implantation barrier; Aluminum implantation forms a P-type base region; Deposit 800nm SiO ₂ ; Uniform photoresist on the 800nm _SiO2 layer, and photolithographically develop the N ⁺ injection window; Photoresist mask etching 800nm SiO ₂ to form side walls; Ion implantation forms the N ⁺ source region; Removal of PolySi and SiO ₂ ; Deposit 2.5 μm SiO ₂ ; Uniform photoresist on the 2.5 μm SiO ₂ layer, and develop a P ⁺ injection window by photolithography; Photoresist mask etching 2.5μm SiO ₂ ; Photoresist and SiO ₂ combined mask etching silicon carbide; remove photoresist; Aluminum implant to form P ⁺ contact area; Remove _SiO2 and perform ion implantation activation annealing; Gate oxide formation, polysilicon deposition and patterning; interlayer dielectric deposition and etching opening; Sputtering front and back ohmic contact, and annealing to form ohmic alloy; Corrosion of unalloyed metals; The metal on the front and back is thickened. 7 . The method for manufacturing a silicon carbide MOSFET with self-aligned trenches according to claim 6 , wherein the P-type base region is formed by multiple aluminum implants, and the junction depth is 0.5 μm. 7 . 8. The method for manufacturing a channel self-aligned silicon carbide MOSFET according to claim 6, characterized in that, using the channel self-alignment process, multiple nitrogen implants are used to form an N ⁺ source region and a channel smaller than 0.5 μm . 9. The method for manufacturing a silicon carbide MOSFET with self-aligned trenches according to claim 6, wherein the N ⁺ source region is partially etched to the P-type base region, and multiple aluminum implants are performed to form a P ⁺ contact area. 10. The method for manufacturing a channel self-aligned silicon carbide MOSFET according to any one of claims 6 to 9, wherein the N ⁺ substrate, N ^- epitaxy, P-type base region, P ⁺ contact region and N ⁺ source region are silicon carbide material.