CN111540683A - Manufacturing method of power device - Google Patents

Abstract

The application discloses a manufacturing method of a power device, which relates to the field of semiconductor manufacturing and comprises the steps of forming a unit structure of the power device on a substrate, wherein the power device is an IGBT; forming a front metal layer; carrying out TAIKO thinning on the back surface of the substrate; forming a collector region on the back surface of the substrate; coating a film on the back surface of the substrate; forming a target metal on the front surface of the substrate by utilizing a chemical plating process; removing the film attached to the back surface of the substrate; forming a metal layer on the back of the substrate; the problem that wafer fragments are easily caused by increasing the thickness and the hardness of the metal on the front surface by using a chemical plating process is solved; the effects of improving the metal falling condition after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process are achieved.

Description

How to make a power device

technical field

The present application relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a power device.

Background technique

IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) device is the core device in new energy power electronic products. With the wider promotion in recent years, the application products not only include white goods, industrial frequency conversion, welding machines and other traditional products , but also high-end products such as new energy vehicles.

At present, IGBT is developing in the direction of high voltage and high current, and the chip technology and packaging of IGBT are facing new challenges. For high-current IGBT chips and modules, the realization of heat dissipation of the overall module has become the focus of research. When packaging IGBT chips, the welding process used for wire bonding has developed from traditional aluminum wire welding to copper sheet welding, which requires higher thickness and hardness of the metal on the front side of the IGBT.

However, when the thickness and hardness of the metal on the front side of the IGBT are increased by the electroless plating process, it is easy to cause wafer fragments.

SUMMARY OF THE INVENTION

In order to solve the problems in the related art, the present application provides a method for fabricating a power device. The technical solution is as follows:

On the one hand, an embodiment of the present application provides a method for fabricating a power device, the method comprising:

forming a unit structure of a power device on a substrate, the power device being an IGBT;

forming a front metal layer;

TAIKO thinning is performed on the backside of the substrate;

forming a collector region on the backside of the substrate;

Coating a film on the back of the substrate;

forming a target metal on the front side of the substrate using an electroless plating process;

removing the film attached to the back of the substrate;

A metal layer is formed on the backside of the substrate.

Optionally, the film attached to the back of the substrate is a material resistant to high temperature and strong acid and alkali.

Optionally, forming the target metal on the front surface of the substrate using an electroless plating process includes:

The target metal is plated on the front side metal layer by an electroless plating process.

Optionally, the target metal includes two layers, the first layer of target metal is nickel, and the second layer of target metal is gold.

Optionally, the target metal includes three layers, the first layer of target metal is nickel, the second layer of target metal is palladium, and the third layer of target metal is gold.

Optionally, in the target metal layer, the thickness of nickel ranges from 0.5um to 20um.

Optionally, in the target metal layer, the thickness of gold ranges from 500A to 5000A.

Optionally, in the target metal layer, the thickness of palladium ranges from 500A to 5000A.

Optionally, forming the unit structure of the power device in the substrate includes:

forming a drift region of the IGBT within the substrate;

forming a base region of the IGBT within the drift region;

forming a gate structure of the IGBT;

A source region is formed in the base region of the IGBT.

The technical solution of the present application includes at least the following advantages:

After the unit structure of the IGBT device is formed on the substrate, a front metal layer is formed on the front side of the substrate, the substrate is thinned, a collector region is formed on the back side of the substrate, and a film is coated on the back side of the substrate before electroless plating, using The protective film prevents the TAIKO ring on the back of the wafer from contacting the chemical agent used in the electroless plating process, and then uses the electroless plating process to form the target metal on the front of the substrate, then removes the film attached to the back of the wafer, and metallizes the back of the substrate. The technology solves the problem of using the chemical plating process to increase the thickness and hardness of the front metal, which is easy to cause wafer fragments; achieves the effect of improving the metal shedding after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a flowchart of a method for manufacturing a power device provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of the implementation of the IGBT device provided in the embodiment of the present application in the manufacturing process;

3 is a schematic diagram of the implementation of the IGBT device provided in the embodiment of the present application in the manufacturing process;

4 is a schematic diagram of the implementation of the IGBT device provided in the embodiment of the present application in the manufacturing process;

FIG. 5 is a schematic diagram of the implementation of the IGBT device provided in the embodiment of the present application in the manufacturing process;

FIG. 6 is a schematic diagram of the implementation of the IGBT device provided in the embodiment of the present application in the manufacturing process.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict with each other.

In the wafer manufacturing process, the TAIKO process is used for backside thinning to reduce wafer warpage and increase the strength of the wafer. The backside of the wafer thinned by the TAIKO process will form a TAIKO ring.

As the overall heat dissipation requirements for IGBT chips are getting higher and higher, in order to enhance the thickness and hardness of the metal on the front side of the wafer, an electroless plating process can be used to plate metal on the front side of the wafer. However, in the actual operation of the electroless plating process, there will be a phenomenon that the metal is attached to the TAIKO ring with an uneven surface. After the electroless plating process is completed, the metal on the TAIKO ring is likely to fall off, and even lead to wafer fragments and machine contamination.

An embodiment of the present application provides a method for fabricating a power device, and the method may include the following steps:

Step 101 , a unit structure of a power device is formed on a substrate, and the power device is an IGBT.

Step 102, forming a front metal layer.

A front metal layer is formed on the front surface of the substrate, and the gate and source regions of the IGBT are drawn out.

Step 103, performing TAIKO thinning on the backside of the substrate.

The substrate is thinned according to the thickness requirements and packaging conditions of the power device.

Step 104, forming a collector region on the backside of the substrate.

The backside of the thinned substrate is ion implanted and annealed to form the collector region of the IGBT.

Step 105, sealing the backside of the substrate with a protective material.

The backside of the substrate is sealed with a protective material, and the chemical agent is isolated from the backside of the substrate during the subsequent electroless plating process, so as to avoid metal residues on the TAIKO ring on the backside of the substrate, so as to avoid the effect of metal falling off on the TAIKO ring. .

The protective material has the characteristics of corrosion resistance, high temperature resistance, can be removed, strong acid resistance, strong alkali resistance; the protective material will not change the structure and performance of the backside of the substrate.

Optionally, the temperature resistance range of the protective material is at least 25°C to 150°C.

Step 106 , forming a target metal on the front surface of the substrate using an electroless plating process.

Optionally, the target metal is composed of multiple layers of metal, and the material and thickness of each layer of metal are determined according to actual conditions.

Optionally, the target metal is a layer of metal, for example, the target metal is nickel. The thickness and material of the target metal are determined according to the actual situation.

Step 107, removing the protective material on the backside of the substrate.

The protective material on the backside of the substrate is removed, and after the protective material is removed, the structure and performance of the backside of the substrate are not damaged.

Step 108, forming a metal layer on the backside of the substrate.

Metal is deposited on the backside of the substrate to form a metal layer, and the collector region of the IGBT is drawn out by using the metal layer.

In one example, the protective material is a protective film. The fabrication method of the power device can be realized by the following steps, as shown in Figure 1:

In step 201, a unit structure of a power device is formed on a substrate, and the power device is an IGBT.

The cellular structure of an IGBT device includes a drift region, a base region, a source region located in the base region, a gate structure and a collector region.

Optionally, a cell structure of one IGBT device, or a cell structure of two or more IGBT devices is formed in the substrate, and other devices may also be formed on the substrate.

The drift region of the IGBT is formed within the substrate. An epitaxial layer is arranged on the substrate, and a drift region is formed in the epitaxial layer through an ion implantation process.

Optionally, the substrate is a P-type substrate, and N-type ions are implanted to form an N-drift region.

The base region of the IGBT is formed in the drift region. A base region pattern is defined by a photolithography process, and ions are implanted into the drift region according to the base region pattern to form a base region.

Optionally, boron ions are implanted into the N-drift region according to the pattern of the base region to form the base region.

The gate structure of the IGBT is formed. The gate structure of the IGBT is a polysilicon gate or a trench gate located on the surface of the substrate.

When the gate structure of the IGBT is a polysilicon gate located on the surface of the substrate, a gate oxide layer is formed on the surface of the substrate, a polysilicon layer is deposited on the gate oxide layer, and the polysilicon layer is etched through photolithography and etching processes to obtain polysilicon grid.

When the gate structure of the IGBT is a trench gate structure, a trench is formed in the substrate through photolithography and etching processes, the bottom of the trench is located in the drift region, a gate oxide layer is formed in the trench, and the trench is filled with polysilicon trench to form a trench gate structure.

The source region of the IGBT is formed in the base region through an ion implantation process and annealing.

In step 202, a front side metal layer is formed.

An interlayer dielectric layer is deposited on the front side of the substrate, and contact holes are formed in the interlayer dielectric layer by photolithography and etching processes; metal sputtering is used to form a front side metal layer on the front side of the substrate by photolithography and etching processes to obtain Lead out the metal electrodes of the source and gate.

As shown in FIG. 2 , the front surface metal layer 12 is formed on the front surface of the substrate 11 , and the dielectric layer 13 is also formed on the front surface of the substrate 11 .

In step 203, TAIKO thinning is performed on the backside of the substrate.

The backside of the substrate is thinned using the TAIKO process.

As shown in FIG. 3 , after the backside of the substrate 11 is thinned, the thickness of the substrate 11 is reduced.

In step 204, a collector region is formed on the backside of the substrate.

A collector region is formed on the backside of the substrate through an ion implantation process and annealing.

In step 205, a film is coated on the backside of the substrate.

Optionally, when laminating the backside of the substrate, the wafer is transported to the corresponding laminating machine by using a wafer box. Align the circle with the ring cutting knife, transfer the protective film, stick the protective film on the back of the wafer, use the ring cutting knife to remove the excess part of the protective film, and then remove the wafer with the protective film on the back from the machine, into the transport box.

As shown in FIG. 4 , a protective film 14 is attached to the back of the substrate 11 , and the protective film 14 seals the back of the substrate 11 .

The film attached to the back of the substrate is a material resistant to high temperature, strong acid and alkali, and the temperature resistance range is at least 20°C to 150°C.

In step 206, a target metal is formed on the front side of the substrate using an electroless plating process.

The target metal is plated on the front side metal layer on the front side of the substrate using an electroless plating process.

Optionally, the target metal includes two layers, the first layer of target metal is nickel (Ni), and the second layer of target metal is gold (Au). Nickel and gold are sequentially plated on the metal electrode on the front side of the substrate by an electroless plating process.

Optionally, the target metal includes three layers, the first layer of target metal is (Ni), the second layer of target metal is palladium (Pd), and the third layer of target metal is gold (Au). Nickel, palladium and gold are sequentially plated on the metal electrode on the front side of the substrate by means of an electroless plating process.

The thickness of each layer of metal is determined according to the actual situation. For example, in the target metal layer, the thickness of gold ranges from 500A to 5000A; in the target metal layer, the thickness of palladium ranges from 500A to 5000A; in the target metal layer, the thickness of nickel ranges from 0.5um to 20um.

As shown in FIG. 5 , the front side of the substrate 11 is plated with a target metal 15 .

In step 207, the film attached to the backside of the substrate is removed.

The protective film attached to the backside of the substrate is removed by a backside peeling process.

In step 208, a metal layer is formed on the backside of the substrate.

A metallization process is performed on the backside of the substrate to form a metal layer, and the collector region is led out.

As shown in FIG. 6 , a metal layer 16 is formed on the back surface of the substrate 11 .

After the unit structure of the IGBT device is formed on the substrate, a front metal layer is formed on the front side of the substrate, the substrate is thinned, a collector region is formed on the back side of the substrate, and a film is coated on the back side of the substrate before electroless plating, using The protective film prevents the TAIKO ring on the back of the wafer from contacting the chemical agent used in the electroless plating process, and then uses the electroless plating process to form the target metal on the front of the substrate, then removes the film attached to the back of the wafer, and metallizes the back of the substrate. The technology solves the problem of using the chemical plating process to increase the thickness and hardness of the front metal, which is easy to cause wafer fragments; achieves the effect of improving the metal shedding after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process.

In another example, the protective material is photoresist. The manufacturing method of the power device can be realized by the following steps:

In step 301, a unit structure of a power device is formed on a substrate, and the power device is an IGBT.

The cellular structure of an IGBT device includes a drift region, a base region, a source region located in the base region, a gate structure and a collector region.

Optionally, a cell structure of one IGBT device, or a cell structure of two or more IGBT devices is formed in the substrate, and other devices may also be formed on the substrate.

The drift region of the IGBT is formed within the substrate. An epitaxial layer is arranged on the substrate, and a drift region is formed in the epitaxial layer through an ion implantation process.

Optionally, the substrate is a P-type substrate, and N-type ions are implanted to form an N-drift region.

The base region of the IGBT is formed in the drift region. A base region pattern is defined by a photolithography process, and ions are implanted into the drift region according to the base region pattern to form a base region.

Optionally, boron ions are implanted into the N-drift region according to the pattern of the base region to form the base region.

The gate structure of the IGBT is formed. The gate structure of the IGBT is a polysilicon gate or a trench gate located on the surface of the substrate.

When the gate structure of the IGBT is a polysilicon gate located on the surface of the substrate, a gate oxide layer is formed on the surface of the substrate, a polysilicon layer is deposited on the gate oxide layer, and the polysilicon layer is etched through photolithography and etching processes to obtain polysilicon grid.

When the gate structure of the IGBT is a trench gate structure, a trench is formed in the substrate through photolithography and etching processes, the bottom of the trench is located in the drift region, a gate oxide layer is formed in the trench, and the trench is filled with polysilicon trench to form a trench gate structure.

In step 302, a front side metal layer is formed.

An interlayer dielectric layer is deposited on the front side of the substrate, and contact holes are formed in the interlayer dielectric layer by photolithography and etching processes; metal sputtering is used to form a front side metal layer on the front side of the substrate by photolithography and etching processes to obtain Lead out the metal electrodes of the source and gate.

In step 303, TAIKO thinning is performed on the backside of the substrate.

The backside of the substrate is thinned using the TAIKO process.

In step 304, a collector region is formed on the backside of the substrate.

A collector region is formed on the backside of the substrate through an ion implantation process and annealing.

In step 305, a photoresist is coated on the backside of the substrate.

A photoresist is coated on the backside of the substrate and exposed to light, and the backside of the substrate is covered with the photoresist to prevent the TAIKO ring portion on the backside from contacting with the chemical solution in the electroless plating process.

In step 306, a target metal is formed on the front side of the substrate using an electroless plating process.

The target metal is plated on the front side metal layer on the front side of the substrate using an electroless plating process.

Optionally, the target metal includes two layers, the first layer of target metal is nickel (Ni), and the second layer of target metal is gold (Au). Nickel and gold are sequentially plated on the metal electrode on the front side of the substrate by an electroless plating process.

Optionally, the target metal includes three layers, the first layer of target metal is (Ni), the second layer of target metal is palladium (Pd), and the third layer of target metal is gold (Au). Nickel, palladium and gold are sequentially plated on the metal electrode on the front side of the substrate by means of an electroless plating process.

The thickness of each layer of metal is determined according to the actual situation. For example, in the target metal layer, the thickness of gold ranges from 500A to 5000A; in the target metal layer, the thickness of palladium ranges from 500A to 5000A; in the target metal layer, the thickness of nickel ranges from 0.5um to 20um.

In step 307, the photoresist on the backside of the substrate is removed.

In step 308, a metal layer is formed on the backside of the substrate.

A metallization process is performed on the backside of the substrate to form a metal layer, and the collector region is led out.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (9)

1. A method of fabricating a power device, the method comprising:

forming a unit structure of a power device on a substrate, wherein the power device is an IGBT;

forming a front metal layer;

carrying out TAIKO thinning on the back surface of the substrate;

forming a collector region on the back surface of the substrate;

coating a film on the back surface of the substrate;

forming a target metal on the front surface of the substrate by utilizing a chemical plating process;

removing the film attached to the back surface of the substrate;

and forming a metal layer on the back of the substrate.

2. The method of claim 1, wherein the film attached to the back of the substrate is a material that is resistant to high temperatures and strong acids and bases.

3. The method of claim 1, wherein forming a target metal on the front side of the substrate using an electroless plating process comprises:

and plating the target metal on the front metal layer by utilizing an electroless plating process.

4. A method according to claim 1 or 3, wherein the target metal comprises two layers, a first layer of target metal being nickel and a second layer of target metal being gold.

5. The method of claim 1 or 3, wherein the target metals comprise three layers, a first layer of target metal being nickel, a second layer of target metal being palladium, and a third layer of target metal being gold.

6. The method of claim 4 or 5, wherein the thickness of nickel in the target metal layer is in the range of 0.5um to 20 um.

7. The method of claim 4 or 5, wherein the thickness of gold in the target metal layer is in the range of 500A to 5000A.

8. The method of claim 5, wherein the thickness of the palladium in the target metal layer is in a range of 500A to 5000A.

9. The method of claim 1, wherein forming a cell structure of a power device in a substrate comprises:

forming a drift region of the IGBT in the substrate;

forming a base region of the IGBT in the drift region;

forming a gate structure of the IGBT;

and forming a source region in the base region of the IGBT.

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