CN111525030B - PPS capacitor and forming method thereof - Google Patents

Abstract

A PPS capacitor and its forming method provided by the present invention, the PPS capacitor comprises a semiconductor substrate, a first dielectric layer, a first polysilicon layer, a second dielectric layer, a second polysilicon layer and a groove, the semiconductor substrate A P-type doped well is formed inside, and the groove runs through the first dielectric layer, the first polysilicon layer, the second dielectric layer and the second polysilicon layer, and exposes the semiconductor substrate, and the semiconductor substrate at the groove An N-type well region is formed in the bottom. The present invention solves the problem of latch-up effect by replacing the existing N-type doped well with a P-type doped well, so that the distance between the formed PPS capacitor and its adjacent components is reduced, the use area is saved, and the improvement is improved. Effective utilization of the area of the subsequently formed memory. At the same time, an N-type well region is formed in the semiconductor substrate, so that when the first polysilicon layer is under positive pressure, the N-type well region is connected to the inversion channel, so that the inversion channel can be connected to the inversion channel through the N-type well region. Road connected to obtain a larger capacitance value.

Description

A kind of PPS capacitor and its forming method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a PPS capacitor and a forming method thereof.

Background technique

In the process of manufacturing memory (specifically flash memory), the gate polysilicon, memory polysilicon and substrate that must be used in the flash memory process can be used to form a capacitor with a relatively large capacitance value that can be called a PPS capacitor , so that the PPS capacitor can be formed without an additional photomask (mask). Among them, the PPS capacitor refers to a three-layer stacked capacitor structure composed of two layers of polysilicon and a substrate, where PPS is the combination of gate polysilicon (Gate Poly), memory polysilicon (memory Poly) and substrate (Substrate). Abbreviation.

FIG. 1 is a schematic structural diagram of a conventional PPS capacitor. As shown in FIG. 1 , the PPS capacitor includes a semiconductor substrate 100, and a high-voltage N-type doped well (ie, HNW) 110 is formed in the semiconductor substrate 100; a tunnel dielectric layer 120 located on the surface of the HNW 110; The storage polysilicon layer 130 on the tunneling dielectric layer 120, the dielectric layer 140 wrapping the storage polysilicon layer 130; the gate polysilicon 150 on the dielectric layer 140, the gate polysilicon 150 located on the storage polysilicon layer 130 , and covers part of the tunneling dielectric layer 120 ; an N-type source and drain are also formed in the semiconductor substrate 100 , which are located outside the gate polysilicon 150 . Wherein, the HNW 110, the memory polysilicon layer 130 and the gate polysilicon 150 are all connected through conductive plugs (not shown in the figure).

When the storage polysilicon layer 130 of the PPS capacitor is positively charged and the HNW 110 is grounded, a latch-up effect is likely to occur, causing damage to components adjacent to the PPS capacitor (such as NMOS transistors, PMOS transistors, etc.). In order to solve this problem, it is necessary to isolate the PPS capacitor and its adjacent components so that the distance between the PPS capacitor and its adjacent components is at least 30 microns, which wastes the area of the memory formed subsequently, that is, the subsequent The area effective utilization rate of the memory is low. At the same time, when the HNW110 of the PPS capacitor is positively charged, the HNW110 under the memory polysilicon layer 130 is in a depleted state, so that the capacitance of the PPS capacitor is very small.

Contents of the invention

The object of the present invention is to provide a PPS capacitor and its forming method, so as to improve the area effective utilization rate of the subsequently formed memory and increase the capacitance value of the PPS capacitor.

In order to solve the above technical problems, the present invention provides a PPS capacitor, comprising:

A semiconductor substrate, in which a P-type doped well is formed;

a first dielectric layer, the first dielectric layer covers the P-type doped well;

a first polysilicon layer located on part of the first dielectric layer;

a second dielectric layer, the second dielectric layer wrapping the first polysilicon layer;

a second polysilicon layer, where the second polysilicon layer wraps the second dielectric layer and covers at least part of the first dielectric layer;

A trench, the trench penetrates through the first dielectric layer, the first polysilicon layer, the second dielectric layer and the second polysilicon layer, and exposes the semiconductor substrate, at the trench An N-type well region is formed in the semiconductor substrate.

Optionally, a source/drain is further included, the source/drain is doped with P-type ions, and the source/drain is formed in the semiconductor substrate outside the second polysilicon layer.

Further, the doping concentration of the P-type doped well is 1×E ¹² /cm ² to 10×E ¹² /cm ² .

Furthermore, the doping concentration of the N-type well region is 1×E ¹⁵ /cm ² to 10×E ¹⁵ /cm ² .

Furthermore, the first dielectric layer is an oxide layer, and the second dielectric layer is an oxide layer.

The present invention also provides a method for forming a PPS capacitor, comprising the following steps:

Step S10: providing a semiconductor substrate, a P-type doped well is formed in the semiconductor substrate, and a first dielectric layer, a first polysilicon layer, a second dielectric layer and a second dielectric layer are sequentially formed on the semiconductor substrate Two polysilicon layers, the first dielectric layer covers the P-type doped well, the first polysilicon layer is located on part of the first dielectric layer, and the second dielectric layer wraps the first a polysilicon layer, the second polysilicon layer covers the second dielectric layer and the first dielectric layer;

Step S20: sequentially etching the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer, and exposing the semiconductor substrate to form trenches;

Step S30: forming an N-type well region in the semiconductor substrate at the trench, and forming a source/drain in the semiconductor substrate outside the second polysilicon layer, thereby forming a PPS capacitor.

Optionally, step S20 includes the following steps:

A patterned photoresist layer is formed on the semiconductor substrate, the photoresist forms an opening on the second polysilicon layer, and the opening exposes part of the second polysilicon layer surface;

Using the patterned photoresist layer as a mask, etching the second polysilicon layer and exposing the second dielectric layer to form a first part of the trench;

Through two etching processes, at the first part of the trench, the second dielectric layer, the first polysilicon layer and the first dielectric layer are sequentially etched, and the semiconductor substrate is exposed to form a second portion of the groove, the second portion of the groove being located directly below the first portion of the groove such that the first portion of the groove and the second portion of the groove together form the groove .

Further, the opening size of the second part of the groove is smaller than the opening size of the first part of the groove, so that the groove is in an inverted convex shape with a large top and a small bottom.

Optionally, step S30 includes the following steps:

performing P-type ion implantation in the semiconductor substrate outside the second polysilicon layer to form source/drain;

N-type ion implantation is performed in the semiconductor substrate at the trench to form an N-type well region.

Optionally, after step S30, also include:

A plug is formed in the trench, so as to access the N-type ions in the inversion channel through the N-type well region when the first polysilicon layer is under positive pressure.

Compared with the prior art, there are the following beneficial effects:

A PPS capacitor and its forming method provided by the present invention, the PPS capacitor includes a semiconductor substrate, a P-type doped well is formed in the semiconductor substrate; a first dielectric layer, the first dielectric layer covers the P-type doped well; the first polysilicon layer, located on part of the first dielectric layer; the second dielectric layer, the second dielectric layer wraps the first polysilicon layer; the second polysilicon layer , the second polysilicon layer wraps the second dielectric layer and covers at least part of the first dielectric layer; a trench, the trench penetrates the first dielectric layer, the first polysilicon layer, The second dielectric layer and the second polysilicon layer expose the semiconductor substrate, and an N-type well region is formed in the semiconductor substrate at the groove. The present invention solves the problem of latch-up effect by replacing the existing N-type doped well with a P-type doped well, so that the distance between the subsequently formed PPS capacitor and its adjacent components is reduced to 0.5 micron to 1 micron , which saves the used area and improves the effective utilization rate of the area of the memory formed subsequently. At the same time, an N-type well region is formed in the trench and the semiconductor substrate at the trench, so that when the first polysilicon layer is under positive pressure, the N-type well region is connected to the inversion channel, so that the N-type well region can be passed through the N-type channel subsequently. The N-type well region connects the N-type ions in the inversion channel, so that the PPS capacitor obtains a larger capacitance value.

Description of drawings

Fig. 1 is the structural representation of existing PPS capacitor;

Fig. 2 is the schematic flow sheet of the forming method of the PPS capacitor of an embodiment of the present invention;

3a-3e are structural schematic diagrams of the split-gate flash memory in various steps according to an embodiment of the present invention.

Explanation of reference signs:

In Figure 1:

100-semiconductor substrate; 110-HNW; 120-tunneling dielectric layer; 130-storage polysilicon layer; 140-dielectric layer; 150-gate polysilicon;

In Figure 3a-3e:

200-semiconductor substrate; 210-P-type doped well; 220-first dielectric layer; 230-first polysilicon layer; 240-second dielectric layer; 250-second polysilicon layer;-source/ Drain;

300 - groove;

400-N type well region.

Detailed ways

A PPS capacitor and its forming method provided by the present invention, the PPS capacitor includes a semiconductor substrate, a P-type doped well is formed in the semiconductor substrate; a first dielectric layer, the first dielectric layer covers the P-type doped well; the first polysilicon layer, located on part of the first dielectric layer; the second dielectric layer, the second dielectric layer wraps the first polysilicon layer; the second polysilicon layer , the second polysilicon layer wraps the second dielectric layer and covers at least part of the first dielectric layer; a trench, the trench penetrates the first dielectric layer, the first polysilicon layer, The second dielectric layer and the second polysilicon layer expose the semiconductor substrate, and an N-type well region is formed in the semiconductor substrate at the groove. The present invention solves the problem of latch-up effect by replacing the existing N-type doped well with a P-type doped well, so that the distance between the subsequently formed PPS capacitor and its adjacent components is reduced to 0.5 micron to 1 micron , which saves the used area and improves the effective utilization rate of the area of the memory formed subsequently. At the same time, an N-type well region is formed in the trench and the semiconductor substrate at the trench, so that when the first polysilicon layer is under positive pressure, the N-type well region is connected to the inversion channel, so that the N-type well region can be passed through the N-type channel subsequently. The N-type well region connects the N-type ions in the inversion channel, so that the PPS capacitor obtains a larger capacitance value.

A PPS capacitor of the present invention and its forming method will be further described in detail below. The invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that those skilled in the art may modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In order to make the purpose and features of the present invention more comprehensible, the specific implementation manners of the present invention will be further described below in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use imprecise ratios, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

FIG. 2 is a schematic flowchart of a method for forming a PPS capacitor in this embodiment. As shown in FIG. 2 , this embodiment provides a method for forming a PPS capacitor, the PPS capacitor is, for example, applied to a memory. The forming method of described PPS capacitor comprises the following steps:

Step S10: providing a semiconductor substrate, a P-type doped well is formed in the semiconductor substrate, and a first dielectric layer, a first polysilicon layer, a second dielectric layer and a second dielectric layer are sequentially formed on the semiconductor substrate Two polysilicon layers, the first dielectric layer covers the P-type doped well, the first polysilicon layer is located on part of the first dielectric layer, and the second dielectric layer wraps the first a polysilicon layer, the second polysilicon layer covers the second dielectric layer and the first dielectric layer;

Step S20: sequentially etching the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer, and exposing the semiconductor substrate to form trenches;

Step S30: forming an N-type well region in the semiconductor substrate at the trench, and forming a source/drain in the semiconductor substrate outside the second polysilicon layer, thereby forming a PPS capacitor.

A method for forming a PPS capacitor disclosed in this embodiment will be described in more detail below with reference to FIGS. 2-3e.

Fig. 3a is the semiconductor substrate provided by this embodiment, as shown in Fig. 3a, step S10 is first performed to provide a semiconductor substrate 200, a P-type doped well 210 is formed in the semiconductor substrate 200, and a P-type doped well 210 is formed in the semiconductor substrate A first dielectric layer 220, a first polysilicon layer 230, a second dielectric layer 240 and a second polysilicon layer 250 are sequentially formed on the bottom 200, and the first dielectric layer 220 covers the P-type doped well 210 , the first polysilicon layer 230 is located on part of the first dielectric layer 220, the second dielectric layer 240 wraps the first polysilicon layer 230, and the second polysilicon layer 250 covers the The second dielectric layer 240 and the first dielectric layer 220. The P-type doped well is isolated from other components of the semiconductor substrate 200 by a shallow isolation structure (not shown in the figure).

This step specifically includes the following steps:

First, a semiconductor substrate 200 is provided, which can provide an operating platform for subsequent processes, which can be any substrate known to those skilled in the art for carrying components of semiconductor integrated circuits, and can be a bare chip, It may also be a wafer processed by an epitaxial growth process. In detail, the semiconductor substrate 200 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. Silicon substrate, indium phosphide (InP) substrate, gallium arsenide (GaAs) substrate or germanium-on-insulator substrate, etc. A P-type doped well 210 is formed in the semiconductor substrate 200 , and the P-type doped well 210 is, for example, a high-voltage P-type doped well. The doping ions of the P-type doped well 210 include at least one of boron (B) ions, boron fluoride (BF ₂ ⁺ ) ions, gallium (Ga) ions and indium (In) ions. In this embodiment, the doping ions of the P-type doped well 210 include boron (B) ions, and the concentration of the doping ions of the P-type doped well 210 is, for example, 1×E12/cm2˜10×E12 /cm2. The P-type doped well 210 does not have a latch-up effect when the first polysilicon layer 230 is positively pressed, so that the distance between the subsequently formed PPS capacitor and its adjacent components is reduced to 0.5 microns to 1 micron, which saves the used area and improves the effective utilization rate of the area of the subsequently formed memory.

Next, a first dielectric layer 220 is formed on the semiconductor substrate 200. The first dielectric layer 220 is, for example, a tunneling dielectric layer. The first dielectric layer 220 is, for example, covered with the P-type doped Well 210 of semiconductor substrate 200 . The material of the first dielectric layer 220 is, for example, oxide, specifically silicon dioxide, and the formation process of the first dielectric layer 220 is a thermal oxidation process or a deposition process, preferably a thermal oxidation process. The thickness of the first dielectric layer 220 is, for example,

所述第一多晶硅层230的形成工艺为低压化学气相沉积工艺(LPCVD)。在本实施例中，所掺杂的离子为磷，则所述低压化学气相沉积工艺的反应气体为硅烷和磷烷。Next, a first polysilicon layer 230 is formed on the first dielectric layer 220 , and the first polysilicon layer 230 is, for example, a memory polysilicon layer. The material of the first polysilicon layer 230 is doped polysilicon, and the doped ions are phosphorus, arsenic, carbon or boron, so that the formed PPS capacitor is more stable. The thickness of the first polysilicon layer 230 is

The formation process of the first polysilicon layer 230 is a low pressure chemical vapor deposition process (LPCVD). In this embodiment, the doped ions are phosphorus, and the reaction gases of the low pressure chemical vapor deposition process are silane and phosphine.

所述第二介质层240可以与所述第一介质层220的形成工艺相同，在此不做赘述。Next, a second dielectric layer 240 is deposited on the surface of the first polysilicon layer 230 so that the second dielectric layer 220 wraps the surface of the first polysilicon layer 230 . The material of the second dielectric layer 240 is, for example, oxide, specifically silicon dioxide. The thickness of the second dielectric layer 240 is

The formation process of the second dielectric layer 240 may be the same as that of the first dielectric layer 220 , which will not be repeated here.

所述第二多晶硅层250的形成工艺与所述第一多晶硅层230的形成工艺相同，在此不做赘述。Next, a second polysilicon layer 250 is formed on the surface of the second dielectric layer 240, the second polysilicon layer 250 covers the second dielectric layer 240, and also covers part of the first dielectric layer 220 . The thickness of the second polysilicon layer 250 is

The formation process of the second polysilicon layer 250 is the same as the formation process of the first polysilicon layer 230 , and will not be repeated here.

In the above structure, after the positive pressure is applied to the first polysilicon layer 230, a channel inversion phenomenon occurs in the HPW210 directly below the first polysilicon layer 230 (that is, in the HPW210 N ion channels have appeared), and because the second polysilicon layer 250 and the semiconductor substrate 200 are equipotential, therefore, no channels have appeared in the HPW210 other than directly below the first polysilicon layer 230 The channel inversion phenomenon, which makes it impossible to conduct between the directly below the first polysilicon layer 230 and the subsequently formed N-type source/drain, resulting in that when the first polysilicon layer 230 is under positive pressure The capacitance value of the PPS capacitor is very small.

In order to solve this problem, the present embodiment then performs the following steps:

FIG. 3b is a schematic diagram of the PPS structure after the trench is formed. As shown in FIG. 3b, step S20 is then performed to sequentially etch the second polysilicon layer 250, the second dielectric layer 240, the first polysilicon layer 230 and The first dielectric layer 220 exposes the semiconductor substrate 200 to form a trench 300 .

This step specifically includes the following steps:

First, a patterned photoresist layer is formed on the semiconductor substrate 200, the photoresist forms an opening on the second polysilicon layer 250, and the opening exposes part of the second polysilicon layer. On the surface of the crystalline silicon layer 250 , preferably, the opening is located in the middle of the surface of the second polysilicon layer 250 .

Next, using the patterned photoresist layer as a mask, the second polysilicon layer 250 is etched to expose the second dielectric layer 240 to form the first part of the trench. This step is performed simultaneously with the process of forming the gate of the memory, so no special photomask is required to perform this step, thereby not increasing the process cost.

Next, through two etching processes, at the first part of the trench 300, the second dielectric layer 240, the first polysilicon layer 230 and the first dielectric layer 220 are sequentially etched to expose the semiconductor substrate 200 to form the second portion of the trench 300 . Wherein, the opening size of the second part of the groove 300 is smaller than the opening size of the first part of the groove 300, so that the groove 300 has an inverted convex shape with a large top and a small bottom. The second part of the trench 300 is located directly below the first part of the trench 300 , so that the first part of the trench 300 and the second part of the trench 300 together form the trench 300 . In this embodiment, the etching process of this step is performed simultaneously with the process of forming the sidewall of the word line of the memory, therefore, no special photomask is required to perform this step, thereby not increasing the process cost.

Fig. 3c is a schematic structural diagram of the PPS capacitor of this embodiment. As shown in FIG. 3c, step S30 is then performed to form an N-type well region in the semiconductor substrate 200 at the trench 300, and form a source in the semiconductor substrate 200 outside the second polysilicon layer 250. /drain, thus forming a PPS capacitor.

This step specifically includes:

Perform P-type ion implantation in the semiconductor substrate 200 outside the second polysilicon layer 250 to form source/drain electrodes; perform N-type ion implantation in the semiconductor substrate at the trench to form N type well region 400 . Wherein, the order of the two steps may not be limited, and the sequence is specifically performed according to the actual situation. At this time, when the positive pressure is applied to the first polysilicon layer 230, the N-type well region is connected to the inversion channel, so that the N-type ions in the inversion channel can be connected through the N-type well region, so that PPS capacitors get larger capacitance values. The N-type ions at the trench include one or more n-type ion implantations such as phosphorus ions, arsenic ions, nitrogen ions, and germanium ions. In this embodiment, the N-type ions at the trench include arsenic ions , and the implantation energy of the N-type ions is 30Kev˜50Kev, and the implantation dose is 4×10E15/cm ² ˜10×10E15/cm ² . The P-type ions forming the source/drain are, for example, the same as the HPW210 ions, the implantation energy is 5Kev-10Kev, and the implantation dose is 2x10E15/cm ² -5x 10E15/cm ² .

FIG. 3d is a capacitance-voltage curve diagram of a PPS capacitor without an N-type well region. As shown in Figure 3d, when the positive voltage is applied to the first polysilicon layer, since the PPS capacitor does not connect the N-type ions in the inversion channel through the N-type well region, the capacitance value at this time is 6.00E-12, At this time the capacitance value is low. Fig. 3e is a capacitance-voltage curve diagram of a PPS capacitor formed with an N-type well region. As shown in Figure 3e, when the positive voltage is applied to the first polysilicon layer, since the PPS capacitor connects the N-type ions in the inversion channel through the N-type well region, the capacitance value at this time is approximately 1.00E-11, The capacitance value at this time is much larger than the capacitance value of the PPS capacitor without forming the N-type well region.

The forming method further includes the step of forming a plug in the trench, so as to extract the N-type ions in the inversion channel through the N-type well region when the first polysilicon layer 230 is under positive pressure. .

Please refer to FIG. 3c, this embodiment also provides a PPS capacitor, including a semiconductor substrate 200, a P-type doped well 210 is formed in the semiconductor substrate 200, and a first A dielectric layer 220, a first polysilicon layer 230, a second dielectric layer 240 and a second polysilicon layer 250, the first dielectric layer 220 covers the P-type doped well 210, the first polysilicon layer The silicon layer 230 is located on part of the first dielectric layer 220, the second dielectric layer 240 wraps the first polysilicon layer 230, and the second polysilicon layer 250 wraps the second dielectric layer 240, And cover part of the first dielectric layer 220 . The PPS capacitor also includes a trench 300, the trench 300 runs through the first dielectric layer 220, the first polysilicon layer 230, the second dielectric layer 240 and the second polysilicon layer 250, and exposes the In the semiconductor substrate 200, an N-type well region 400 is formed in the semiconductor substrate 200 at the trench 300, and a P-type source is formed in the semiconductor substrate 200 outside the second polysilicon layer 250. /drain. The doping concentration of the P-type doped well 210 is 1×E ¹² /cm ² -10×E ¹² /cm ² ; the doping concentration of the N-type well region 400 is 1×E ¹⁵ /cm ² -10 ×E ¹⁵ /cm ² .

In summary, the present invention provides a PPS capacitor and its forming method, the PPS capacitor includes a semiconductor substrate, a P-type doped well is formed in the semiconductor substrate; a first dielectric layer, the first The dielectric layer covers the P-type doped well; the first polysilicon layer is located on part of the first dielectric layer; the second dielectric layer wraps the first polysilicon layer; Two polysilicon layers, the second polysilicon layer wraps the second dielectric layer and covers at least part of the first dielectric layer; a groove, the groove penetrates the first dielectric layer, the first The polysilicon layer, the second dielectric layer and the second polysilicon layer expose the semiconductor substrate, and an N-type well region is formed in the semiconductor substrate at the trench. The present invention solves the problem of latch-up effect by replacing the existing N-type doped well with a P-type doped well, so that the distance between the subsequently formed PPS capacitor and its adjacent components is reduced to 0.5 micron to 1 micron , which saves the used area and improves the effective utilization rate of the area of the memory formed subsequently. At the same time, an N-type well region is formed in the trench and the semiconductor substrate at the trench, so that when the first polysilicon layer is under positive pressure, the N-type well region is connected to the inversion channel, so that the N-type well region can be passed through the N-type channel subsequently. The N-type well region connects the N-type ions in the inversion channel, so that the PPS capacitor obtains a larger capacitance value.

In addition, it should be noted that unless otherwise specified or pointed out, the descriptions of the terms "first" and "second" in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent each Logical or sequential relationships among components, elements, and steps, etc.

It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. A PPS capacitor for use in a memory, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a P-type doped well is formed in the semiconductor substrate;

the first dielectric layer covers the P-type doped well;

the first polycrystalline silicon layer is positioned on part of the first dielectric layer;

the second dielectric layer wraps the first polycrystalline silicon layer;

the second polycrystalline silicon layer wraps the second dielectric layer and covers at least part of the first dielectric layer;

the groove penetrates through the first dielectric layer, the first polycrystalline silicon layer, the second dielectric layer and the second polycrystalline silicon layer and exposes out of the semiconductor substrate, and an N-type well region is formed in the semiconductor substrate at the groove;

and the source/drain is doped with P-type ions and is formed in the semiconductor substrate outside the second polycrystalline silicon layer.

2. The PPS capacitor of claim 1, wherein the doping concentration of the P-type doped well is 1 xE ¹² /cm ² ～10×E ¹² /cm ² 。

3. The PPS capacitor of claim 2 wherein the N-well region has a doping concentration of 1 xe ¹⁵ /cm ² ～10×E ¹⁵ /cm ² 。

4. The PPS capacitor of claim 3, wherein the first dielectric layer is an oxide layer and the second dielectric layer is an oxide layer.

5. A method for forming a PPS capacitor is characterized by comprising the following steps:

step S10: providing a semiconductor substrate, forming a P-type doped well in the semiconductor substrate, and sequentially forming a first dielectric layer, a first polycrystalline silicon layer, a second dielectric layer and a second polycrystalline silicon layer on the semiconductor substrate, wherein the first dielectric layer covers the P-type doped well, the first polycrystalline silicon layer is positioned on part of the first dielectric layer, the second dielectric layer wraps the first polycrystalline silicon layer, and the second polycrystalline silicon layer covers the second dielectric layer and the first dielectric layer;

step S20: etching the second polycrystalline silicon layer, the second dielectric layer, the first polycrystalline silicon layer and the first dielectric layer in sequence, and exposing the semiconductor substrate to form a groove;

step S30: and forming an N-type well region in the semiconductor substrate at the groove, and forming a source/drain in the semiconductor substrate outside the second polycrystalline silicon layer so as to form the PPS capacitor, wherein the source/drain is doped with P-type ions.

6. The forming method of claim 5, wherein the step S20 includes the steps of:

forming a patterned photoresist layer on the semiconductor substrate, wherein the photoresist layer is provided with an opening on the second polycrystalline silicon layer, and the opening exposes part of the surface of the second polycrystalline silicon layer;

etching the second polysilicon layer by taking the patterned photoresist layer as a mask, and exposing the second dielectric layer to form a first part of the groove;

and sequentially etching the second dielectric layer, the first polycrystalline silicon layer and the first dielectric layer at the first part of the groove by two etching processes, and exposing the semiconductor substrate to form a second part of the groove, wherein the second part of the groove is positioned right below the first part of the groove, so that the first part of the groove and the second part of the groove jointly form the groove.

7. The forming method according to claim 6, wherein an opening size of the second portion of the groove is smaller than an opening size of the first portion of the groove, so that the groove has an inverted convex shape with a large upper portion and a small lower portion.

8. The forming method of claim 5, wherein the step S30 includes the steps of:

performing P-type ion implantation in the semiconductor substrate at the outer side of the second polycrystalline silicon layer to form a source/drain;

and carrying out N-type ion implantation in the semiconductor substrate at the groove to form an N-type well region.

9. The forming method of claim 5, further comprising, after step S30:

and forming a plug in the groove so as to connect out N-type ions in the inversion channel through the N-type well region when positive pressure is applied to the first polysilicon layer.

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