CN109473435B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device, in a semiconductor substrate where a memory device is arranged, the semiconductor substrate can be thinned, so that an insulating ring penetrating through the substrate can be manufactured through processes of etching, filling and the like, the substrate in the insulating ring is isolated from the surrounding substrate, a diffusion layer is formed in the substrate in the insulating ring, a resistor structure with the resistance value adjusted by the diffusion layer is formed in the insulating ring, the diffusion layer of the resistor structure is led out through two leading-out structures, and the connection and the use of the resistor structure can be realized through the leading-out structures. The resistor structure can be formed in a thinned substrate where the memory device is located, the insulating rings can be manufactured in the substrate in the areas to form an independent resistor structure, the resistance of the resistor structure is adjusted by the diffusion layer, and then the resistor structure is led out through the leading-out structure of the diffusion layer, so that the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of a chip is improved.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present invention relates to the field of semiconductor devices and their manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the continuous development of semiconductor technology, the integration level of integrated circuits has been continuously improved. In the chip design of integrated circuits, active devices and passive devices are usually integrated at the same time, and passive devices such as resistors and capacitors also occupy the chip area, especially in the chip design of 3D NAND memory, the peripheral circuit is composed of The analog circuit composed of HVMOS (High Voltage Metal Oxide Semiconductor) devices and LVMOS (Low Voltage Metal Oxide Semiconductor) devices will use a large number of resistors in the peripheral circuits, which will occupy a large amount of The chip area is not conducive to improving the integration degree of the chip.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, in which the resistor is integrated into the substrate where the memory device is located, and the area of the substrate where the peripheral circuit is located is reduced.

For achieving the above object, the present invention has the following technical solutions:

A semiconductor device, comprising:

a first semiconductor substrate, the first semiconductor substrate has a first surface and a second surface opposite thereto, the semiconductor substrate includes a first region and a second region, the first region is formed on the first surface There are storage devices;

an insulating ring penetrating the semiconductor substrate in the second region;

a diffusion layer in the first surface substrate within the insulating ring;

a cover layer on the first surface of the second region;

The first lead-out structure and the second lead-out structure of the diffusion layer in the cover layer.

Optionally, the memory device includes a stack layer in which gate layers and insulating layers are alternately stacked, memory cell strings passing through the stack layer, and a memory cell interconnect structure in a dielectric layer above the memory cell strings;

The cover layer includes a first cover layer and a second cover layer, the first cover layer and the stacked layer have substantially the same height, and the second cover layer is the dielectric layer;

The first lead-out structure includes a first contact on the diffusion layer penetrating the first capping layer and a first interconnection structure in the second capping layer and on the first contact;

The second lead-out structure includes a second contact on the diffusion layer penetrating the first capping layer and a second interconnection structure in the second capping layer and on the second contact.

Optionally, the memory cell string includes a channel hole passing through the stacked layers, and a tunneling layer, a charge storage layer, a blocking layer and a channel layer sequentially formed on sidewalls of the channel hole.

Optionally, a passivation layer on the second surface is also included.

Optionally, the insulating ring is circular or polygonal.

Optionally, the thickness of the semiconductor substrate is less than 10um.

Optionally, it also includes a second semiconductor substrate on which MOS devices and an interconnection structure of the MOS devices are formed;

The first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed;

The first lead-out structure and the second lead-out structure are respectively electrically connected to the interconnection structure of the MOS device.

Optionally, the MOS device includes a low-voltage MOS device and a high-voltage MOS device.

A method of manufacturing a semiconductor device, comprising:

A first semiconductor substrate is provided, the first semiconductor substrate has a first surface and a second surface opposite thereto, the semiconductor substrate includes a first region and a second region, the first region on the first surface A memory device is formed; a diffusion layer is formed in the substrate on the first surface of the second region, a cover layer is formed on the first surface of the second region, and the diffusion layer is formed in the cover layer a first lead-out structure and a second lead-out structure;

thinning of the first semiconductor substrate from the second surface;

An insulating ring penetrating the semiconductor substrate is formed in the second area from the second surface, and an inner area of the insulating ring covers a diffusion layer area where the first lead-out structure and the second lead-out structure are connected.

Optionally, after forming the insulating ring, the method further includes:

A passivation layer is formed on the second surface.

Optionally, the memory device includes a stack layer in which gate layers and insulating layers are alternately stacked, memory cell strings passing through the stack layer, and a memory cell interconnect structure in a dielectric layer above the memory cell strings;

The cover layer includes a first cover layer and a second cover layer, the first cover layer and the stacked layer have substantially the same height, and the second cover layer is the dielectric layer;

The first lead-out structure includes a first contact on the diffusion layer penetrating the first capping layer and a first interconnection structure in the second capping layer and on the first contact;

The second lead-out structure includes a second contact on the diffusion layer penetrating the first capping layer and a second interconnection structure in the second capping layer and on the second contact.

Optionally, the memory cell string includes a channel hole passing through the stacked layers, and a tunneling layer, a charge storage layer, a blocking layer and a channel layer sequentially formed on sidewalls of the channel hole.

Optionally, the insulating ring is circular or polygonal.

Optionally, before thinning the first semiconductor substrate from the second surface, further comprising:

providing a second semiconductor substrate on which MOS devices and an interconnection structure of the MOS devices are formed;

Facing the first surface of the first semiconductor substrate toward the interconnection structure of the MOS device of the second semiconductor substrate, and fixing the first semiconductor substrate and the second semiconductor substrate, the first semiconductor substrate The lead-out structure and the second lead-out structure are respectively electrically connected with the interconnection structure of the MOS device.

Optionally, the MOS device includes a low-voltage MOS device and a high-voltage MOS device.

Optionally, forming an insulating ring through the semiconductor substrate in the second region from the second surface includes:

Transferring the pattern of the insulating ring into the mask layer by a photolithography process;

Under the masking of the mask layer, the first semiconductor substrate is etched from the second surface until the first semiconductor substrate is penetrated;

Filling with insulating material is performed to form an insulating ring.

In the semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention, in the thinned semiconductor substrate where the memory device is located, an insulating ring is formed by etching and filling processes, and the insulating ring separates the substrate and the surrounding substrate. isolated, and a diffusion layer is formed in the substrate in the insulating ring, thus, a resistance structure whose resistance value is adjusted by the diffusion layer is formed in the insulating ring. The structure can realize the connection and use of the resistance structure. The resistance structure is formed in the substrate where the memory device is located, the substrate will be packaged with another substrate containing peripheral circuits, and there will be some non-device blank areas around the memory device area, which can be used in these A resistance structure is formed in the substrate of the area, and the resistance value of the resistance structure is adjusted by the diffusion layer, and then the resistance structure is drawn out through the extraction structure of the diffusion layer, so as to facilitate the connection and use of the peripheral circuit devices. The effective area of the bottom is improved, and the integration degree of the chip is improved.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a schematic structural diagram of a semiconductor device according to another embodiment of the present invention;

FIG. 3 shows a schematic top-view structure of an insulating ring in a semiconductor device from a first surface according to an embodiment of the present invention;

4-8 are schematic diagrams showing the cross-sectional structure of the device in the process of forming the semiconductor device according to the manufacturing method according to the embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.

Next, the present invention is described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not be limited here. The scope of protection of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

As described in the background art, in the chip of the integrated circuit, a large number of passive devices such as resistors are also used, and these devices also occupy the area of the chip. In the application of memory devices, with the requirements for integration With the continuous improvement, in order to further increase the storage capacity and reduce the storage cost per bit, a storage device with a three-dimensional structure is proposed. In one application of the three-dimensional memory device, the 3D NAND memory device can be a MOS (Metal Oxide Semiconductor) device for peripheral circuits formed on different substrates, and then the two can be connected by packaging technology on different substrates. At the same time, the peripheral circuit is an analog circuit composed of HVMOS devices and LVMOS devices. A large number of resistors will be used in the peripheral circuit, and these resistors will occupy a large amount of chip area, which makes it difficult to reduce the chip area of the peripheral circuit, which is not conducive to improving the integration of the chip. .

Based on this, the present application proposes a semiconductor device, as shown in FIG. 1 , including:

A first semiconductor substrate 100 having a first surface 101 and a second surface 102 opposite thereto, the semiconductor substrate including a first region 1001 and a second region 1002, the first region A storage device is formed on the first surface 101 of 1001;

the insulating ring 150 passing through the semiconductor substrate 100 in the second region 1002;

the diffusion layer 104 in the substrate 100 on the first surface 101 in the insulating ring 150;

a cover layer 120 on the first surface 101 of the second region 1002;

The first lead-out structure 130 and the second lead-out structure 140 of the diffusion layer 104 in the cover layer 120 .

In the embodiments of the present application, the storage device and the MOS devices of the peripheral circuits of the storage device are formed on different substrates respectively, and the resistance structure is formed on the substrate where the storage device is located. The substrate is separated from the substrate outside the ring, and a diffusion layer is formed in the substrate inside the insulating ring. In this way, a resistance structure is formed in the insulating ring to adjust the resistance value through the diffusion layer. The diffusion layer is drawn out, and the connection and use of the resistance structure can be realized through the lead-out structure. The resistive structure is formed in the substrate where the storage device is located. Around the storage device region, especially around the 3D NAND storage device, there will be some non-device blank areas. Using these blank areas to form the resistive structure will not The area of the chip is additionally increased, and at the same time, the resistance value of the resistance structure is adjusted by the diffusion layer, and then the resistance structure is drawn out through the extraction structure of the diffusion layer, so as to facilitate the connection and use of the devices of the peripheral circuit, thus reducing the resistance of the substrate where the peripheral circuit is located. Effective area, improve the integration of the chip.

In the embodiment of the present application, the storage device may be a three-dimensional storage device, that is, in addition to the horizontal two-dimensional direction of the substrate, there are also a plurality of storage cells distributed in the vertical direction of the substrate. The three-dimensional memory device is a 3D NAND memory device, which is formed on the first surface of the substrate 100. The 3D NAND memory device at least includes a stack layer 110 in which gate layers and insulating layers are alternately stacked, and memory cells passing through the stack layer 110. The string 112 and the memory cell interconnection structure 114 on the memory cell string 112, the interconnection structure 114 is formed in the dielectric layer 124 and is used for the extraction of the memory cell string, which may include one or more metal layers and contacts connecting the metal layers , vias, pads, etc.

In the 3D NAND memory device, the stacked layers 110 are formed by alternately stacking gate layers and insulating layers, and the gate layer of each layer and the memory cell string 112 constitute a memory cell, so as to form a memory cell in the direction perpendicular to the substrate. multiple storage units. The end of the stacked layer 110 may be a stepped structure (not shown in the figure), so that the gate layer of each layer has a part not covered by the upper gate layer, so that it can be used to form the contact of the gate layer. , so that each gate layer can be drawn out. The memory cell string 120 may be formed in a channel hole penetrating the stacked layer 110, along the sidewall of the channel hole to the center of the channel hole, the memory cell string 112 sequentially includes a memory function layer and a channel layer, and the memory function layer plays a charge. The function of storage usually includes a tunneling layer, a charge storage layer and a blocking layer. The storage function layer can be basically L-shaped, and the channel layer is formed on the sidewall of the storage function layer and the bottom of the channel hole, between the channel layers. A filling layer of insulating material may also be formed. It can be understood that, in a specific application, on the first surface 101 of the semiconductor substrate 100, other necessary components may also be included, such as conductive pads on top of the memory cell strings 114, strobe devices, etc.

In this embodiment of the present application, as shown in FIG. 1 and FIG. 3 , the insulating ring 150 is formed in the substrate 100 . The substrate 100 may be a thinned substrate, and its thickness is usually less than 10um, which can be Conventional semiconductor processes, such as photolithography, etching, and filling processes, are used to form the through insulating ring 150 .

The insulating ring 150 is formed of a material capable of isolating the substrate into different parts, and the material of the insulating ring 150 may be, for example, one or more of dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating ring 150 is a closed annular structure, and the insulating ring plays the role of insulating isolation, so that the substrate in the ring is isolated from the substrate outside the ring, and the substrate in the insulating ring is used to form a resistance structure. The shape of the insulating ring 150 can be set as required. The shape of the insulating ring 150 is also the shape of the resistance structure. For example, the shape of the insulating ring 150 can be a polygon or a circle. The polygon can include a square or other polygons, and the square includes a square and a rectangle. Referring to FIG. 3 , in this specific example, the shape of the insulating ring 150 is a square.

In the present application, a diffusion layer 104 is provided in the first surface 101 of the substrate in the insulating ring 150, that is, a silicon diffusion type resistance structure is formed in the insulating ring 150, and the diffusion layer 104 is a dopant in the substrate. The impurity layer, the diffusion layer 104 can have p-type doping or n-type doping, the n-type doping dopant ions can be, for example, N, P, As, S, etc., and the p-type doping dopant particles can be B, for example , Al, Ga or In etc. In a specific application, a resistance structure with a desired resistance value can be obtained by controlling process parameters such as doping particles, doping concentration, and doping depth of the diffusion layer 104 , and combining the area within the insulating ring 150 .

The resistance structure is formed on the substrate 100 where the memory device is located, and is formed on the blank area of the memory device that is not the device. For the convenience of description, in this application, this area is denoted as the second area 1002 , which is in the second area 1002 A cover layer 120 is formed on a first surface 101 of lead out. The first lead-out structure 130 and the second lead-out structure 140 serve as two connection terminals of the resistor, so that circuits in other substrates, such as peripheral circuits, use the resistor structure.

In a specific embodiment, the cover layer 120 may have different structures, and may be a laminated structure of dielectric materials. The first lead-out structure 130 and the second lead-out structure 140 are used for electrical lead-out of the diffusion layer 104 , and may include contacts, one or more metal layers, and vias, pads, and the like for connecting the metal layers. In the embodiment in which the memory device is a 3D NAND memory device, the capping layer 120 includes a first capping layer 122 and a second capping layer 124. The first capping layer 122 is substantially the same height as the stacking layer 110 of the 3D NAND memory device, and the second capping layer 122 is substantially the same height as the stacking layer 110 of the 3D NAND memory device. The cover layer 124 is the dielectric layer 124 of the memory cells in the first region 1001 ; the first lead-out structure 130 includes a first contact 132 on the diffusion layer 104 penetrating the first cover layer 122 and in the second cover layer 124 , the first contact A first interconnect structure 134 on the contact 132 , the second lead-out structure 140 includes a second contact 142 on the diffusion layer 104 penetrating the first capping layer 122 and in the second capping layer 124 on the second contact 142 the second interconnect structure 144 . The first interconnection structure 134 and the second interconnection structure 144 may include one or more metal layers and vias, pads, etc. connecting the metal layers, and may be interconnected with the memory device interconnection structures 114 on the memory cell strings 112 in the first region 1001 have the same structure, that is, can be formed simultaneously in the same process.

A passivation layer 160 may be further provided on the second surface 102 of the substrate 100, and the passivation layer 160 plays a protective role. The passivation layer 160 may be a one-layer or multi-layer structure. For example, the passivation layer 160 may for the silicon oxide layer.

The above semiconductor device may be a device on a wafer after the wafer fabrication is completed, or a device in a package structure after being packaged with other wafers. In the embodiment of the package structure, referring to FIG. It further includes a second semiconductor substrate 200 on which the MOS device 210 and the interconnection structure 220 of the MOS device are formed; the first surface 101 of the first semiconductor substrate 100 faces the MOS of the second semiconductor substrate 200 In the interconnection structure 220 of the device, the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed. In a specific application, the corresponding interconnection structures on the two substrates can be fixed together by packaging technology, and the first lead-out structure 130 and the second lead-out structure 140 are respectively electrically connected to the interconnection structure 220 of the MOS device.

The first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed together by packaging technology, and the resistance structure is formed in the substrate where the memory device is located, and is connected to the second semiconductor through the first lead-out structure 130 and the second lead-out structure 140 The interconnect structures 220 of the MOS devices on the substrate 200 are electrically connected, so that, without occupying the area of the second semiconductor substrate 200 , the idle area of the first semiconductor substrate 100 other than the memory device can be used to realize the first semiconductor substrate 100 . The layout of the resistor structure required by the circuit in the semiconductor substrate 200 reduces the effective area of the substrate where the peripheral circuits are located, and improves the integration degree of the chip.

According to different design requirements, the second semiconductor substrate 200 may have different source-drain operating voltages and device types. In the application of 3D NAND memory devices, the 3D NAND memory device requires a higher driving voltage, and its peripheral circuits usually include The high voltage MOS device and the low voltage MOS device, ie HVMOS and LVMOS, may be of PMOS and/or NMOS type. Among them, the high-voltage MOS device is relative to the source-drain working voltage of the standard MOS device. For example, in the 0.18um CMOS device process, the source-drain working voltage of the standard MOS device is 1.8V, which is higher than the working voltage of the standard MOS device. voltage, it is a high-voltage MOS device. In the application of 3D NAND, the source-drain operating voltage of the high-voltage MOS device can be higher than 20V, typically 25V.

In a specific embodiment, the MOS device at least includes a gate on the second semiconductor substrate 200, spacers on the sidewall of the gate, and source and drain regions in the substrates on both sides of the gate, and the interconnect structure 220 of the MOS device includes a Layer or multiple metal layers, as well as vias, pads, etc. connecting the metal layers, the interconnect structure 220 may be disposed on the source and drain regions and/or the gate.

The structure of the semiconductor device of the embodiments of the present application is described in detail above. In order to better understand the technical solutions and technical effects of the present application, the specific embodiments will be described in detail below with reference to the flowcharts and the accompanying drawings.

Referring to FIG. 4 , in step S01 , a first semiconductor substrate 100 is provided, the first semiconductor substrate 100 has a first surface 101 and a second surface 102 opposite thereto, the semiconductor substrate 100 includes a first region 1001 and a second region 1002, a memory device is formed on the first surface 101 of the first region 1001; a diffusion layer 104 is formed in the substrate 100 on the first surface 101 of the second region 1002, the second A capping layer 120 is formed on the first surface 102 of the region 1002 , and the capping layer 120 is formed with a first lead-out structure 130 and a second lead-out structure 140 of the diffusion layer 104 , as shown in FIG. 5 .

In a preferred embodiment of the present application, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, Such as SGOI (silicon germanium on insulator) and so on. In this embodiment, the semiconductor substrate 100 may be a silicon substrate.

In this embodiment of the present application, the above-mentioned storage device, diffusion layer, and first and second lead-out structures have been formed on the first substrate 100. The present application does not specifically limit the methods for forming these devices and structures. For ease of understanding, the following will describe these devices and structures with a specific example.

The diffusion layer 104 may be formed in the substrate 100 from the second surface 102 of the second region 1002 after or before the memory cell strings 112 are formed on the first region 1001 . Specifically, desired types of impurities can be implanted into the substrate through ion implantation, and then thermal annealing is performed to activate the doping, thereby forming the diffusion layer 104 , as shown in FIG. 5 . Specifically, the diffusion layer 104 may have p-type doping or n-type doping, the n-type doping dopant ions may be N, P, As, S, etc., and the p-type doping dopant particles may be B, for example , Al, Ga or In, etc., parameters such as doping particles and doping concentration and depth can be selected according to the resistance value of the resistance structure to be formed.

In this embodiment, the memory device is a three-dimensional NAND memory device. In a specific implementation, firstly, a stacked layer may be formed by alternately stacking sacrificial layers and insulating layers in the first region 1001 , and the sacrificial layers and insulating layers have different The etching selectivity, the sacrificial layer will be removed and replaced by the gate layer, the sacrificial layer can be silicon nitride, for example, the insulating layer can be silicon oxide, the number of layers of the sacrificial layer and the insulating layer in the stack is determined by the vertical direction. The number of memory cells to be formed is determined. The number of sacrificial layers and insulating layers can be, for example, 32 layers, 64 layers, 128 layers, etc. The number of layers determines the number of memory cells in the vertical direction. Therefore, stacking layers The more layers there are, the better the integration can be.

Then, an etching process can be used to make the end of the stack layer 110 a stepped structure, the stepped structure is used for subsequent formation of contacts on the gate layer, and the central area of the stacked layer is a storage area for forming a memory device.

In the process of forming the memory device, first, a channel hole is formed in the stacked layer, the channel hole can be a through hole in the stacked layer, and an etching technique can be used to etch the stacked layer until the substrate 100 is exposed. A surface 101 is formed with channel holes. Then, an epitaxial structure can be grown in-situ at the bottom of the channel hole by selective epitaxial growth (Selective Epitaxial Growth), and the epitaxial structure is the channel layer of the gate device. In the substrate under the channel hole, a doped region may be formed in advance as the active region of the gate device. Then, a memory cell string is formed in the channel hole. Specifically, a memory function layer is now formed on the sidewall of the channel hole. The memory function layer may include a tunneling layer, a charge storage layer, and a blocking layer, and may specifically be an ONO stack. , ONO (Oxide-Ntride-Oxide) is oxide, nitride and oxide, the storage function layer can be L-type, and the channel layer of the gate device is exposed. Then, a channel layer is deposited, and the channel layer may be polysilicon, so that the channel layer of the memory device is formed on the memory function layer and the channel layer of the gate device. Finally, the channel hole is filled with an insulating material, such as silicon oxide.

After that, the stacked layer 110 may be etched to form a gate line seam, the sacrificial layer in the stacked layer may be removed through the gate line seam, and at the same time, the gate material may be filled, for example, the gate material may be metal tungsten, A gate layer is formed in the area of the original sacrificial layer, and the gate line gap is filled. In this way, a stacked layer 110 in which gate layers and insulating layers are alternately stacked is formed, and the gate layer in the stacked layer serves as the control gate of each memory cell of the memory cell string 112 and the control gate of the gate device.

Then, the above-mentioned device may be covered with a dielectric material, and the first surface 101 of the second region 1002 and the stepped structure of the stacked layers (not shown in the figure) will be covered with a first cover layer 122. After the planarization process, The first capping layer 122 on the second area will have a thickness that is substantially the same as the stacked layers.

After that, etching and filling of the first capping layer 122 may be performed, the first contact 132 and the second contact 142 may be formed on the diffusion layer 104 of the second region 1002 , and the stepped structure of the stacked layers of the first region 1001 may be formed Gate contact (not shown).

After that, continuing to cover the second cover layer 124 of the dielectric material, the first interconnect structure 134 , the second interconnect structure 144 , and the first region 1001 may be formed on the first contact 132 and the second contact 142 in the second region 1002 at the same time. The interconnection structure 114 of the memory device is formed on the memory cell strings 112 of the storage device, and the interconnection structure may include one or more metal layers, vias connecting the metal layers, and pads.

So far, the memory device and the diffusion layer 104 of the resistance structure and the lead-out structure of the diffusion layer 104 are formed on the front surface of the first semiconductor substrate 100 .

In step S02 , thinning of the first semiconductor substrate 100 is performed from the second surface 102 , as shown in FIG. 6 .

When the first semiconductor substrate and another semiconductor substrate need to be packaged together, the wafer level packaging technology can be used, the first semiconductor substrate and the other semiconductor substrate are packaged first, and then the The backside of a semiconductor substrate 100 is subjected to a thinning process.

In this embodiment, before thinning, as shown in FIG. 6 , the method further includes: providing a second semiconductor substrate 200 on which the MOS device 210 and the interconnection structure 220 of the MOS device are formed ; The first surface 101 of the first semiconductor substrate 100 faces the interconnection structure 114 of the MOS device of the second semiconductor substrate 200, and the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, and the first lead-out The structure 130 and the second extraction structure 140 are respectively electrically connected to the interconnect structure 114 of the MOS device.

A MOS device has been formed on the second semiconductor substrate 200. The MOS device is used to form the peripheral circuit of the memory device. According to different design requirements, the MOS device can have different source-drain operating voltages and device types. In the 3D NAND memory device In applications, a 3D NAND memory device requires a higher driving voltage, and its peripheral circuits usually include high-voltage MOS devices and low-voltage MOS devices, namely HVMOS and LVMOS, and the device types can be PMOS and/or NMOS.

In a specific application, the MOS device includes a gate dielectric layer on the second semiconductor substrate 200, a gate, spacers on the sidewalls of the gate, and source and drain regions in the substrate on both sides of the gate, and the interconnect structure 220 of the MOS device includes One or more metal layers and vias, pads, etc. connecting the metal layers, and the interconnect structure 220 may be disposed on the source and drain regions and/or the gate. The gate dielectric layer 1 can be, for example, a thermal oxide layer or other suitable dielectric materials, such as silicon oxide or high-k dielectric materials, and high-k dielectric gate materials such as hafnium-based oxide, HFO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, etc. one or a combination of several. The gate electrode can be, for example, polysilicon, amorphous silicon, or metal electrode material or a combination thereof, and the metal electrode material can be one or more combinations of TiN, TiAl, Al, TaN, TaC, and W. The spacers may have a single-layer or multi-layer structure, and may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silica glass, low-k dielectric materials, combinations thereof, and/or other suitable materials . The source and drain regions have a first doping type, which may be n-type or p-type. The MOS device on the second semiconductor substrate 200 may be formed by any method, which is not specifically limited in this application.

When the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, packaging techniques, such as metal bonding or solder ball connection, may be used to connect the first lead-out structure 130 and the second lead-out structure 140 to the The interconnect structure 114 of the MOS device is fixed and electrically connected.

In this way, the first semiconductor substrate 100 and the second semiconductor substrate are electrically connected together, the resistance structure is formed in the substrate where the memory device is located, and the first lead-out structure 130 and the second lead-out structure 140 are connected with the second lead-out structure The interconnection structures 220 of the MOS devices on the semiconductor substrate 200 are electrically connected, so that, without occupying the area of the second semiconductor substrate 200 , the idle area of the first semiconductor substrate 100 other than the memory device can be used to realize the The layout of the resistor structure required by the circuit in the second semiconductor substrate 200 reduces the effective area of the substrate where the peripheral circuits are located, and improves the integration degree of the chip.

Afterwards, as shown in FIG. 6 , the reverse side of the first semiconductor substrate 100 may be thinned, so that the substrate 100 has an appropriate thickness, which facilitates subsequent processes. Specifically, the second surface 102 of the first semiconductor substrate 100 can be thinned by chemical mechanical polishing until a desired thickness is achieved. Generally, the thickness of the first semiconductor substrate 100 after thinning is less than 10um.

In step S03 , an insulating ring 150 penetrating the semiconductor substrate 100 is formed from the second surface 102 in the second region 1002 , and the inner region of the insulating ring 150 covers the first lead-out structure 130 and the first lead-out structure 130 and the second region 1002 . The area of the diffusion layer 104 to which the two extraction structures 140 are connected is shown with reference to FIG. 7 .

Since the thickness of the first semiconductor substrate 100 is greatly reduced after thinning, an insulating ring penetrating the semiconductor substrate can be formed by using the existing semiconductor technology. Specifically, the pattern of the insulating ring can be transferred to the mask through a photolithography process. Then, under the masking of the mask layer, through the etching process, the substrate 100 is first etched from the second surface 102 until the substrate 100 is etched through, and a through insulating ring is etched. That is, a closed annular groove, and then, filling with insulating material, such as one or more of silicon oxide, silicon nitride, or silicon oxynitride, is performed to form the insulating ring 150 . By controlling the position of the insulating ring 150 , the inner area of the insulating ring 150 covers the area of the diffusion layer 104 where the first lead-out structure 130 and the second lead-out structure 140 are connected, thus forming a resistance structure in the insulating ring 150 .

The shape of the insulating ring 150 can be set as required. The shape of the insulating ring 150 is also the shape of the resistance structure. The shape of the insulating ring 150 can be, for example, a polygon or a circle. 3, in this specific example, the shape of the insulating ring 150 is a square. Finally, the resistance value of the resistance structure is determined according to the substrate area in the insulating ring 150 and the doping condition of the diffusion layer 104 in the insulating ring 150 .

In this way, the resistance structure is integrated in the substrate where the memory device is located, the resistance structure is formed in the insulating ring in the substrate, the resistance structure is adjusted by the diffusion layer, and the resistance structure is diffused through the two lead-out structures Layer lead-out, these two lead-out structures serve as two connection terminals of the resistor, so that circuits in other substrates, such as peripheral circuits, use the resistor structure.

Afterwards, as shown in FIG. 8 , a passivation layer 160 may be further formed on the second surface 102 . The passivation layer may be formed by deposition of a passivation layer, such as a silicon oxide material, and planarization.

So far, the processing of the semiconductor device of the embodiment of the present application is completed.

The above descriptions are only preferred embodiments of the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify them into equivalents of equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Claims (14)

1. a semiconductor device, is characterized in that, comprises: a first semiconductor substrate, the first semiconductor substrate has a first surface and a second surface opposite thereto, the semiconductor substrate includes a first region and a second region, the first region is formed on the first surface There are storage devices; an insulating ring passing through the semiconductor substrate in the second region, and the substrate in the insulating ring is used to form a resistance structure; a diffusion layer in the first surface substrate within the insulating ring; a cover layer on the first surface of the second region; a first lead-out structure and a second lead-out structure of the diffusion layer in the cover layer; a second semiconductor substrate, on which a MOS device and an interconnection structure of the MOS device are formed; The first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed; The first lead-out structure and the second lead-out structure are respectively electrically connected to the interconnection structure of the MOS device. 2 . The semiconductor device according to claim 1 , wherein the memory device comprises a stack layer in which gate layers and insulating layers are alternately stacked, memory cell strings passing through the stack layer, and memory cell strings above the memory cell strings. 3 . The interconnect structure of memory cells in the media layer; The cover layer includes a first cover layer and a second cover layer, the first cover layer and the stacked layer have substantially the same height, and the second cover layer is the dielectric layer; The first lead-out structure includes a first contact on the diffusion layer penetrating the first capping layer and a first interconnection structure in the second capping layer and on the first contact; The second lead-out structure includes a second contact on the diffusion layer penetrating the first capping layer and a second interconnection structure in the second capping layer and on the second contact. 3 . The semiconductor device according to claim 2 , wherein the memory cell string comprises a channel hole passing through the stacked layers, and a tunneling layer, a charge storage layer, and a blocking layer sequentially formed on sidewalls of the channel hole. 4 . and channel layer. 4. The semiconductor device of claim 1, further comprising a passivation layer on the second surface. 5. The semiconductor device according to claim 1, wherein the insulating ring is circular or polygonal. 6 . The semiconductor device according to claim 1 , wherein the thickness of the semiconductor substrate is less than 10 μm. 7 . 7. The semiconductor device according to claim 6, wherein the MOS device comprises a low voltage MOS device and a high voltage MOS device. 8. A method of manufacturing a semiconductor device, comprising: A first semiconductor substrate is provided, the first semiconductor substrate has a first surface and a second surface opposite thereto, the semiconductor substrate includes a first region and a second region, the first region on the first surface A memory device is formed; a diffusion layer is formed in the substrate on the first surface of the second region, a cover layer is formed on the first surface of the second region, and the diffusion layer is formed in the cover layer a first lead-out structure and a second lead-out structure; providing a second semiconductor substrate on which MOS devices and an interconnection structure of the MOS devices are formed; Facing the first surface of the first semiconductor substrate toward the interconnection structure of the MOS device of the second semiconductor substrate, and fixing the first semiconductor substrate and the second semiconductor substrate, the first semiconductor substrate The lead-out structure and the second lead-out structure are respectively electrically connected to the interconnection structure of the MOS device; thinning of the first semiconductor substrate from the second surface; An insulating ring is formed through the semiconductor substrate from the second surface in the second region, the substrate within the insulating ring is used to form a resistive structure, and the inner region of the insulating ring covers the first The diffusion layer region to which the lead-out structure and the second lead-out structure are connected. 9. The manufacturing method according to claim 8, wherein after forming the insulating ring, further comprising: A passivation layer is formed on the second surface. 10 . The manufacturing method according to claim 8 , wherein the memory device comprises stacked layers in which gate layers and insulating layers are alternately stacked, memory cell strings passing through the stacked layers, and memory cell strings above the memory cell strings. 11 . The interconnect structure of memory cells in the media layer; The cover layer includes a first cover layer and a second cover layer, the first cover layer and the stacked layer have substantially the same height, and the second cover layer is the dielectric layer; The first lead-out structure includes a first contact on the diffusion layer penetrating the first capping layer and a first interconnection structure in the second capping layer and on the first contact; The second lead-out structure includes a second contact on the diffusion layer penetrating the first capping layer and a second interconnection structure in the second capping layer and on the second contact. 11 . The manufacturing method according to claim 10 , wherein the memory cell string comprises a channel hole passing through the stacked layer, and a tunneling layer, a charge storage layer and a charge storage layer formed in sequence on the sidewall of the channel hole. 12 . layer, barrier layer and channel layer. 12. The manufacturing method according to claim 10, wherein the insulating ring is circular or polygonal. 13. The manufacturing method according to claim 8, wherein the MOS device comprises a low-voltage MOS device and a high-voltage MOS device. 14. The method of claim 8, wherein forming an insulating ring through the semiconductor substrate in the second region from the second surface comprises: Transferring the pattern of the insulating ring into the mask layer by a photolithography process; Under the masking of the mask layer, the first semiconductor substrate is etched from the second surface until the first semiconductor substrate is penetrated; Filling with insulating material is performed to form an insulating ring.

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