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CN111354780A - A super junction terminal with inversion implanted sidewalls and method of making the same - Google Patents

A super junction terminal with inversion implanted sidewalls and method of making the same Download PDF

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CN111354780A
CN111354780A CN202010196037.1A CN202010196037A CN111354780A CN 111354780 A CN111354780 A CN 111354780A CN 202010196037 A CN202010196037 A CN 202010196037A CN 111354780 A CN111354780 A CN 111354780A
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epitaxial
active region
inversion
super
sidewalls
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盛况
郭清
任娜
王策
王珩宇
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Zhejiang University ZJU
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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Abstract

公开了一种带有反型注入的超级结终端及其制作方法。所述侧壁注入形成的超级结终端包括外延柱、反型注入侧壁和沟槽,外延柱和沟槽是在衬底上通过外延生长形成的具有掺杂的半导体区域,通过刻蚀形成,反型注入侧壁通过在沟槽侧壁进行离子注入形成,沟槽与外延柱区相间排列,位于两个相邻外延柱区之间。该带有反型注入的超级结终端可以在器件阻断电压时使有源区边缘电场分布比较均匀,从而提高边缘区域耐压,充分发挥有源区的耐压能力。

Figure 202010196037

A super junction terminal with inversion injection and a fabrication method thereof are disclosed. The super junction terminal formed by the sidewall implantation includes an epitaxial column, an inversion implanted sidewall and a trench, and the epitaxial column and the trench are doped semiconductor regions formed by epitaxial growth on the substrate, and formed by etching, The inversion implanted sidewalls are formed by ion implantation on the sidewalls of the trenches, the trenches and the epitaxial pillar regions are arranged alternately, and are located between two adjacent epitaxial pillar regions. The super junction terminal with inversion injection can make the edge electric field distribution of the active region relatively uniform when the device blocks the voltage, thereby improving the withstand voltage of the edge region and giving full play to the withstand voltage capability of the active region.

Figure 202010196037

Description

一种带有反型注入侧壁的超级结终端及其制作方法A super junction terminal with inversion implanted sidewalls and method of making the same

技术领域technical field

本发明涉及一种半导体器件,尤其涉及一种带有反型注入侧壁的超级结终端及其制作方法。The present invention relates to a semiconductor device, in particular to a super junction terminal with inversion implanted sidewalls and a fabrication method thereof.

背景技术Background technique

几年来国际上对节能减排越来越重视,这对大型电力电子设备的损耗控制和效率提升提出了更高的要求。作为电力电子设备的重要组成部分,半导体功率器件受到了业界的广泛关注。In recent years, more and more attention has been paid to energy conservation and emission reduction in the world, which puts forward higher requirements for loss control and efficiency improvement of large power electronic equipment. As an important part of power electronic equipment, semiconductor power devices have received extensive attention in the industry.

击穿电压是半导体功率器件的重要指标,表示器件能够耐受的最大电压。功率器件的有源区通过合理的设计可以获得几千伏的击穿电压,从而适用于更高功率的应用场合。然而有源区并不是无限延展的,在有源区的边缘处,即半导体功率器件的终端,如果没有合理的设计,将会极大地限制有源区耐压的实现。为了在尽可能小的面积上形成耐压尽可能高的终端,业界提出了多种类型的设计方案。其中包括沟槽终端、倾斜终端、结终端、场限环终端、复合浮空结终端、空间调制结终端等多种类型。Breakdown voltage is an important indicator of semiconductor power devices, indicating the maximum voltage that the device can withstand. The active area of the power device can obtain a breakdown voltage of several thousand volts through reasonable design, so it is suitable for higher power applications. However, the active region is not infinitely extended. At the edge of the active region, that is, the terminal of the semiconductor power device, if there is no reasonable design, the realization of the withstand voltage of the active region will be greatly limited. In order to form a terminal with the highest possible withstand voltage in the smallest area possible, various types of design solutions have been proposed in the industry. These include trench termination, tilt termination, junction termination, field limiting ring termination, composite floating junction termination, spatial modulation junction termination and many other types.

现有终端技术可以实现较大的击穿电压,但是因为在阻断大电压时终端区域的电场分布不够均匀,所以不能最大程度发挥有源区设计的最大耐压,而且所需的终端面积较大。The existing terminal technology can achieve a large breakdown voltage, but because the electric field distribution in the terminal area is not uniform enough when blocking large voltages, the maximum withstand voltage of the active area design cannot be maximized, and the required terminal area is relatively large. big.

发明内容SUMMARY OF THE INVENTION

为了解决背景技术中提出的问题,本专利提出了一种带有反型注入侧壁的超级结终端及其制作方法。In order to solve the problems raised in the background art, this patent proposes a super junction terminal with inversion implanted sidewalls and a fabrication method thereof.

根据本发明实施例的一种带有反型注入侧壁的超级结终端,所述超级结终端位于有源区的边缘,包括:衬底;多个外延柱区,位于所述衬底上方,且位于所述有源区的周围,将所述有源区包围起来,每个外延柱区包括外延柱和反型注入侧壁,所述反型注入侧壁位于所述外延柱的侧壁上;以及多个沟槽,与所述多个外延柱区交替排列,每个沟槽位于两个相邻的外延柱区之间。According to an embodiment of the present invention, a super junction terminal with inversion implanted sidewalls, the super junction terminal is located at an edge of an active region, including: a substrate; a plurality of epitaxial pillar regions located above the substrate, and is located around the active region and surrounds the active region, each epitaxial column region includes an epitaxial column and an inversion implanted sidewall, and the inversion implanted sidewall is located on the sidewall of the epitaxial column ; and a plurality of trenches alternately arranged with the plurality of epitaxial pillar regions, each trench being located between two adjacent epitaxial pillar regions.

根据本发明实施例的一种带有反型注入侧壁的超级结终端的制作方法,带有反型注入侧壁的超级结终端位于有源区的边缘,所述制作方法包括:在衬底上生长一层外延层;利用掩膜在外延层上刻蚀出多个外延柱,所述多个外延柱位于所述有源区的周围,将所述有源区包围起来;以及在每个外延柱的一个或两个侧壁上进行离子注入形成反型注入侧壁;其中两个相邻外延柱之间形成沟槽,所述沟槽与所述外延柱交替排列。According to an embodiment of the present invention, a method for fabricating a super junction terminal with inversion implanted sidewalls, wherein the superjunction terminal with inversion implanted sidewalls is located at the edge of an active region, the fabricating method includes: on a substrate growing an epitaxial layer on top; etching a plurality of epitaxial pillars on the epitaxial layer by using a mask, the plurality of epitaxial pillars are located around the active region and enclose the active region; and in each Ion implantation is performed on one or both sidewalls of the epitaxial pillars to form inverse implantation sidewalls; a trench is formed between two adjacent epitaxial pillars, and the trenches and the epitaxial pillars are alternately arranged.

本发明提出的一种带有反型注入侧壁的超级结终端及其制作方法,基于超级结原理,在尽可能小的面积上形成耐压尽可能高的终端,可以广泛应用于半导体功率器件,设置反型注入侧壁的掺杂类型与外延柱的掺杂类型相反实现相间分布的P型和N型掺杂区域,形成电荷平衡,从而使电场分布更均匀,从而在相同尺寸和外延掺杂的情况下,可以耐受更高的电压。A super junction terminal with an inversion injection sidewall and a manufacturing method thereof proposed by the present invention, based on the super junction principle, can form a terminal with the highest possible withstand voltage in the smallest area possible, and can be widely used in semiconductor power devices , set the doping type of the inversion implant sidewall to be opposite to the doping type of the epitaxial column to achieve alternately distributed P-type and N-type doping regions, form charge balance, and make the electric field distribution more uniform, so that the same size and epitaxial doping can be achieved. In the case of miscellaneous conditions, it can withstand higher voltages.

附图说明Description of drawings

图1为本发明实施例的带有反型注入侧壁的超级结终端的三维立体图;FIG. 1 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls according to an embodiment of the present invention;

图2为本发明实施例的PN二极管某个方向上带有反型注入侧壁的超级结终端的三维立体图;2 is a three-dimensional perspective view of a super junction terminal with an inversion injection sidewall in a certain direction of a PN diode according to an embodiment of the present invention;

图3为本发明实施例的超级结肖特基二极管平行于柱区方向的带有反型注入侧壁的超级结终端的三维立体图;3 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls of a super junction Schottky diode parallel to a pillar region direction according to an embodiment of the present invention;

图4为本发明实施例的超级结肖特基二极管垂直于外延柱区方向的带有反型注入侧壁的超级结终端的三维立体图。4 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls of a super junction Schottky diode perpendicular to the direction of the epitaxial pillar region according to an embodiment of the present invention.

具体实施方式Detailed ways

下面将结合附图详细描述本发明的具体实施例,应当注意,这里描述的实施例只用于举例说明,并不用于限制本发明。在以下描述中,为了便于对本发明的透彻理解,阐述了大量特定细节。然而,本领域普通技术人员可以理解,这些特定细节并非为实施本发明所必需。此外,在一些实施例中,为了避免混淆本发明,未对公知的电路、材料或方法做具体描述。The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described herein are only used for illustration and are not used to limit the present invention. In the following description, numerous specific details are set forth in order to facilitate a thorough understanding of the present invention. However, one of ordinary skill in the art will understand that these specific details are not required to practice the present invention. Furthermore, in some embodiments, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.

在整个说明书中,对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着:结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此,在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外,可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外,本领域普通技术人员应当理解,在此提供的附图均是为了说明的目的,其中相同的附图标记指示相同的元件。应当理解,当称元件“连接到”或“耦接”到另一元件时,它可以是直接连接或耦接到另一元件或者可以存在中间元件。相反,当称元件“直接连接到”或“直接耦接到”另一元件时,不存在中间元件。在说明书或权利要求书中出现的“左”、“右”、“内”、“外”、“前”、“后”、“上”、“下”、“顶部”、“底部”、“之上”、“之下”或类似的描述,均仅是为了说明的目的,而非用于描述固定的相对位置。应当理解,以上术语在适当的情况下是可以互换的,从而使得相应的实施例可以在其它方向上正常工作。此外,在说明书或权利要求书中出现的“接触”可以是直接接触,也可以是间接接触,例如通过引线连接接触。Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in the present invention in at least one embodiment. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combination and/or subcombination in one or more embodiments or examples. Furthermore, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes, wherein like reference numerals refer to like elements. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. "Left", "right", "inner", "outer", "front", "rear", "upper", "lower", "top", "bottom", "outer", "left", "right", "inside", "outside", "front", "rear", "upper", "lower" "Above," "under," or similar descriptions are for illustrative purposes only, and are not used to describe fixed relative positions. It is to be understood that the above terms are interchangeable under appropriate circumstances so that corresponding embodiments may function properly in other orientations. In addition, "contact" appearing in the specification or claims may be direct contact or indirect contact, such as contact through wire connection.

超级结技术是通过交替排列的N型和P型掺杂区域,使相邻区域互相补偿,实现电荷平衡,从而逼近零掺杂的电荷分布的技术,可以表现为多种类型;具体实施方式也有杂质扩散、重复进行外延生长与离子注入等。Super junction technology is a technology that uses alternately arranged N-type and P-type doping regions to make adjacent regions compensate each other and achieve charge balance, thereby approximating the charge distribution of zero doping, which can be expressed in various types; Impurity diffusion, repeated epitaxial growth and ion implantation, etc.

图1为本发明实施例的带有反型注入侧壁的超级结终端的三维立体图。所述带有反型注入侧壁的超级结终端包括:衬底6;外延柱区4,位于所述衬底6上方,包括外延柱2和反型注入侧壁3,所述外延柱2位于有源区1的周围,其延伸方向垂直于所述有源区1的边缘7,将有源区1包围起来,可以与有源区1接触或者不接触,其中所述有源区1即功率器件中实现主体功能的区域,所述反型注入侧壁3位于所述外延柱2的两侧或一侧的侧壁上;沟槽5,与外延柱区4相间排列,位于两个相邻外延柱区4之间。FIG. 1 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls according to an embodiment of the present invention. The super junction terminal with inversion implanted sidewalls includes: a substrate 6; an epitaxial pillar region 4 located above the substrate 6, including an epitaxial pillar 2 and an inversion implanted sidewall 3, and the epitaxial pillar 2 is located at the top of the substrate 6. Around the active area 1, its extending direction is perpendicular to the edge 7 of the active area 1, surrounding the active area 1, and may or may not be in contact with the active area 1, wherein the active area 1 is the power In the area where the main function is realized in the device, the inversion implanted sidewalls 3 are located on both sides or sidewalls of the epitaxial pillar 2; the trenches 5 are arranged alternately with the epitaxial pillar region 4 and are located in two adjacent between the epitaxial pillar regions 4 .

在一个实施例中,所述反型注入侧壁3的掺杂类型与所述外延柱2的掺杂类型相反。在一个实施例中,所述反型注入侧壁3通过在所述外延柱2的侧壁进行离子注入形成。在一个实施例中,宽度是指平行于有源区边缘方向的尺寸,所述外延柱区2的宽度小于10μm,所述沟槽5的宽度小于10μm,因为更大的外延柱区4和沟槽宽度5无法实现N型区和P型区电荷的互相耗尽或者能够互相耗尽但是造成外延柱2与反型注入侧壁3的交界处电场过大,使耐压下降。在一个实施例中,所述外延柱区4的厚度大于1μm,因为更小的外延柱区4的厚度不能很好地对其下方区域的电场进行调制,造成耐压下降。In one embodiment, the doping type of the inversion implant sidewall 3 is opposite to that of the epitaxial pillar 2 . In one embodiment, the inversion implanted sidewalls 3 are formed by ion implantation on the sidewalls of the epitaxial pillars 2 . In one embodiment, the width refers to the dimension parallel to the edge of the active region, the width of the epitaxial pillar region 2 is less than 10 μm, and the width of the trench 5 is less than 10 μm, because the larger epitaxial pillar region 4 and trench The groove width 5 cannot realize the mutual depletion of the N-type region and the P-type region charge or can deplete each other, but the electric field at the junction of the epitaxial column 2 and the inversion sidewall 3 is too large, which reduces the withstand voltage. In one embodiment, the thickness of the epitaxial column region 4 is greater than 1 μm, because the smaller thickness of the epitaxial column region 4 cannot well modulate the electric field in the region below it, resulting in a drop in withstand voltage.

在一个实施例中,实际制作过程包括:In one embodiment, the actual manufacturing process includes:

第一步,在N型半导体衬底上生长一层半导体外延层,其掺杂仍然是N型掺杂,掺杂浓度为1×1015cm-3~1×1017cm-3,然后通过一系列工艺形成有源区;The first step is to grow a semiconductor epitaxial layer on the N-type semiconductor substrate, and its doping is still N-type doping, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 , and then pass through A series of processes form the active area;

第二步,将有源区保护起来,使用干法刻蚀在终端区域按照一定间距刻蚀条状的沟槽,间距小于10μm,刻蚀深度大于5μm。In the second step, the active area is protected, and strip-shaped trenches are etched in the terminal area by dry etching at a certain distance, the distance is less than 10 μm, and the etching depth is greater than 5 μm.

第三步,通过倾斜侧壁离子注入,在沟槽的侧壁注入P型杂质,掺杂浓度为1×1015cm-3~1×1019cm-3,注入深度小于3μm,并控制注入量使得P型杂质和N型外延柱区中的杂质总量大致相同,形成电荷平衡。In the third step, P-type impurities are implanted on the sidewall of the trench by ion implantation on the inclined sidewall, the doping concentration is 1×10 15 cm -3 -1×10 19 cm -3 , the implantation depth is less than 3 μm, and the implantation is controlled. The amount makes the total amount of impurities in the P-type impurity and N-type epitaxial pillar regions approximately the same, forming a charge balance.

由此形成的带有反型注入侧壁的超级结终端,通过交替排列的N型和P型掺杂区域,即交替排列的反型注入侧壁3和外延柱2,使器件阻断电压时,相邻的外延柱2和反型注入侧壁3中的电荷互相补偿,实现电荷平衡,从而逼近零掺杂的电荷分布,可以使终端的电场分布非常均匀,即在终端各点的电场强度大小相差较小,从而在较小的面积中实现较大的击穿电压。注意本实施例中的所述的N型和P型掺杂可以互换,同样可以产生类似的效果。The super junction terminal with inversion implanted sidewalls thus formed, through the alternately arranged N-type and P-type doped regions, that is, the alternately arranged inversion implanted sidewalls 3 and epitaxial pillars 2, makes the device block when the voltage is , the charges in the adjacent epitaxial column 2 and the inversion injection sidewall 3 compensate each other to achieve charge balance, thereby approaching the charge distribution of zero doping, which can make the electric field distribution of the terminal very uniform, that is, the electric field strength at each point of the terminal The magnitude difference is smaller, resulting in a larger breakdown voltage in a smaller area. Note that the N-type and P-type doping described in this embodiment can be interchanged, and similar effects can also be produced.

图2为本发明实施例的PN二极管某个方向上带有反型注入侧壁的的超级结终端的三维立体图。所述带有反型注入侧壁的超级结终端包括:衬底6;有源区1,包括P型注入区8和N型漂移区9;外延柱区4,位于所述衬底6上方,包括外延柱2和反型注入侧壁3,所述外延柱2位于有源区1的周围,其延伸方向垂直于所述有源区1的边缘7,将有源区1包围起来,可以与有源区1接触或者不接触,其中所述有源区1即功率器件中实现主体功能的区域,所述反型注入侧壁3位于所述外延柱2的两侧或一侧的侧壁上;沟槽5,与外延柱区4相间排列,位于两个相邻外延柱区4之间。FIG. 2 is a three-dimensional perspective view of a super junction terminal with an inversion injection sidewall in a certain direction of a PN diode according to an embodiment of the present invention. The super junction terminal with inversion implanted sidewalls includes: a substrate 6; an active region 1 including a P-type implanted region 8 and an N-type drift region 9; an epitaxial column region 4 located above the substrate 6, It includes an epitaxial pillar 2 and an inversion implanted sidewall 3. The epitaxial pillar 2 is located around the active region 1, and its extension direction is perpendicular to the edge 7 of the active region 1, and surrounds the active region 1. The active area 1 is in contact or not, wherein the active area 1 is the area in the power device that realizes the main function, and the inversion implanted sidewalls 3 are located on both sides or sidewalls of the epitaxial pillar 2 ; The trenches 5 are arranged alternately with the epitaxial column regions 4 and are located between two adjacent epitaxial column regions 4 .

在一个实施例中,P型注入区8和N型漂移区9相互接触,形成共同组成有源区1,形成PN二极管的PN结。在一个实施例中,所述反型注入侧壁3的掺杂类型与所述外延柱2的掺杂类型相反。在一个实施例中,所述反型注入侧壁3通过在所述外延柱2的侧壁进行离子注入形成。在一个实施例中,所述外延柱2垂直于所述有源区1。在一个实施例中,宽度是指平行于有源区边缘方向的尺寸,所述外延柱区2的宽度小于10μm,所述沟槽5的宽度小于10μm,因为更大的外延柱区4和沟槽宽度5无法实现N型区和P型区电荷的互相耗尽或者能够互相耗尽但是造成外延柱2与反型注入侧壁3的交界处电场过大,使耐压下降。在一个实施例中,所述外延柱区4的厚度大于1μm,因为更小的外延柱区4的厚度不能很好地对其下方区域的电场进行调制,造成耐压下降。在一个实施例中,所述的P型注入区8是在衬底6上通过外延生长具有N型掺杂的半导体区域之后,通过P型离子注入形成的P型掺杂区。在一个实施例中,外延柱区4的顶部比有源区1的顶部低,以便将终端区域与有源区1顶部隔离开来。In one embodiment, the P-type implanted region 8 and the N-type drift region 9 are in contact with each other to form the active region 1 together, and form the PN junction of the PN diode. In one embodiment, the doping type of the inversion implant sidewall 3 is opposite to that of the epitaxial pillar 2 . In one embodiment, the inversion implanted sidewalls 3 are formed by ion implantation on the sidewalls of the epitaxial pillars 2 . In one embodiment, the epitaxial pillar 2 is perpendicular to the active region 1 . In one embodiment, the width refers to the dimension parallel to the edge of the active region, the width of the epitaxial pillar region 2 is less than 10 μm, and the width of the trench 5 is less than 10 μm, because the larger epitaxial pillar region 4 and trench The groove width 5 cannot realize the mutual depletion of the N-type region and the P-type region charge or can deplete each other, but the electric field at the junction of the epitaxial column 2 and the inversion sidewall 3 is too large, which reduces the withstand voltage. In one embodiment, the thickness of the epitaxial column region 4 is greater than 1 μm, because the smaller thickness of the epitaxial column region 4 cannot well modulate the electric field in the region below it, resulting in a drop in withstand voltage. In one embodiment, the P-type implanted region 8 is a P-type doped region formed by P-type ion implantation after epitaxially growing a semiconductor region with N-type doping on the substrate 6 . In one embodiment, the top of epitaxial pillar region 4 is lower than the top of active region 1 in order to isolate the termination region from the top of active region 1 .

在一个实施例中,实际制作过程包括:In one embodiment, the actual manufacturing process includes:

第一步,在N型半导体衬底上生长一层半导体外延层,其掺杂仍然是N型掺杂,掺杂浓度为1×1015cm-3~1×1017cm-3,然后通过离子注入形成P型注入区,掺杂浓度大于1×1017cm-3The first step is to grow a semiconductor epitaxial layer on the N-type semiconductor substrate, and its doping is still N-type doping, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 , and then pass through Ion implantation forms a P-type implantation region, and the doping concentration is greater than 1×10 17 cm -3 ;

第二步,将有源区保护起来,使用干法刻蚀在终端区域将P型注入区刻掉,再按照一定间距刻蚀条状的沟槽,间距小于10μm,刻蚀深度大于5μm。The second step is to protect the active area, use dry etching to etch away the P-type implanted area in the terminal area, and then etch strip-shaped trenches at a certain distance, the distance is less than 10μm, and the etching depth is greater than 5μm.

第三步,通过倾斜侧壁离子注入,在沟槽的侧壁注入P型杂质,掺杂浓度为1×1015cm-3~1×1019cm-3,注入深度小于3μm,并控制注入量使得P型杂质和N型外延柱区中的杂质总量大致相同,形成电荷平衡。In the third step, P-type impurities are implanted on the sidewall of the trench by ion implantation on the inclined sidewall, the doping concentration is 1×10 15 cm -3 -1×10 19 cm -3 , the implantation depth is less than 3 μm, and the implantation is controlled. The amount makes the total amount of impurities in the P-type impurity and N-type epitaxial pillar regions approximately the same, forming a charge balance.

在表面四个方向都具有此带有反型注入侧壁的超级结终端的PN二极管,在阴极加正电压,阳极接地时,可以在终端区域获得均匀的电场分布,从而在较小的面积中实现较大的击穿电压,使终端的击穿电压大于有源区的击穿电压。注意本实施例中的所述的N型和P型掺杂可以互换,同样可以产生类似的效果。A PN diode with this super junction terminal with inverse injection sidewalls in all four directions on the surface, when a positive voltage is applied to the cathode and the anode is grounded, a uniform electric field distribution can be obtained in the terminal area, so that in a smaller area A larger breakdown voltage is achieved, so that the breakdown voltage of the terminal is greater than that of the active region. Note that the N-type and P-type doping described in this embodiment can be interchanged, and similar effects can also be produced.

图3为本发明实施例的超级结肖特基二极管平行于柱区方向的带有反型注入侧壁的超级结终端的三维立体图,所述侧壁注入形成的超级结终端包括:衬底6;有源区外延柱10和有源区沟槽11,相间排列,组成有源区的超级结结构;外延柱区4,位于所述衬底6上方,包括外延柱2和反型注入侧壁3,所述外延柱2位于有源区1的周围,其延伸方向垂直于所述有源区1的边缘7,平行于所述有源区外延柱10的延伸方向,将有源区1包围起来,可以与有源区1接触或者不接触,其中所述有源区1即功率器件中实现主体功能的区域,所述反型注入侧壁3位于所述外延柱2的两侧或一侧的侧壁上;沟槽5,与外延柱区4相间排列,位于两个相邻外延柱区4之间。3 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls of a super junction Schottky diode parallel to the direction of the pillar region according to an embodiment of the present invention. The super junction terminal formed by the sidewall implantation includes: a substrate 6 ; Active region epitaxial pillars 10 and active region trenches 11, arranged alternately to form a super junction structure in the active region; Epitaxial pillar region 4, located above the substrate 6, including epitaxial pillars 2 and inversion implanted sidewalls 3. The epitaxial pillar 2 is located around the active region 1, and its extension direction is perpendicular to the edge 7 of the active region 1, parallel to the extension direction of the active region epitaxial pillar 10, and surrounds the active region 1 It can be in contact with or not in contact with the active region 1 , wherein the active region 1 is the region in the power device that realizes the main function, and the inversion implanted sidewalls 3 are located on both sides or one side of the epitaxial pillar 2 The trenches 5 are arranged alternately with the epitaxial column regions 4 and are located between two adjacent epitaxial column regions 4 .

图4为本发明实施例的超级结肖特基二极管垂直于外延柱区方向的带有反型注入侧壁的超级结终端的三维立体图。所述侧壁注入形成的超级结终端包括:衬底6;有源区外延柱10和有源区沟槽11,相间排列,组成有源区的超级结结构;外延柱区4,位于所述衬底6上方,包括外延柱2和反型注入侧壁3,所述外延柱2位于有源区1的周围,其延伸方向垂直于所述有源区1的边缘7,垂直于所述有源区外延柱8的延伸方向,将有源区1包围起来,可以与有源区1接触或者不接触,其中所述有源区1即功率器件中实现主体功能的区域,所述反型注入侧壁3位于所述外延柱2的两侧或一侧的侧壁上;沟槽5,与外延柱区4相间排列,位于两个相邻外延柱区4之间。4 is a three-dimensional perspective view of a super junction terminal with inversion implanted sidewalls of a super junction Schottky diode perpendicular to the direction of the epitaxial pillar region according to an embodiment of the present invention. The super junction terminal formed by the sidewall implantation includes: substrate 6; active region epitaxial pillars 10 and active region trenches 11, which are arranged alternately to form a super junction structure of the active region; epitaxial pillar region 4, located in the Above the substrate 6, including epitaxial pillars 2 and inversion implanted sidewalls 3, the epitaxial pillars 2 are located around the active region 1, and its extension direction is perpendicular to the edge 7 of the active region 1 and perpendicular to the active region 1. The extension direction of the active region epitaxial pillar 8 surrounds the active region 1 and may or may not be in contact with the active region 1, wherein the active region 1 is the region in the power device that realizes the main function, and the inversion implantation The sidewalls 3 are located on two sides or one sidewall of the epitaxial pillar 2 ; the trenches 5 are arranged alternately with the epitaxial pillar regions 4 and are located between two adjacent epitaxial pillar regions 4 .

参照图3和图4,在一个实施例中,所述有源区外延柱10的侧壁有反型注入层12,以便形成有源区的超级结结构。在一个实施例中,所述反型注入侧壁3的掺杂类型与所述外延柱2的掺杂类型相反。在一个实施例中,所述反型注入侧壁3通过在所述外延柱2的侧壁进行离子注入形成。在一个实施例中,所述外延柱2垂直于所述有源区1。在一个实施例中,宽度是指平行于有源区边缘方向的尺寸,所述外延柱区2的宽度小于10μm,所述沟槽5的宽度小于10μm,因为更大的外延柱区4和沟槽宽度5无法实现N型区和P型区电荷的互相耗尽或者能够互相耗尽但是造成外延柱2与反型注入侧壁3的交界处电场过大,使耐压下降。在一个实施例中,所述外延柱区4的厚度大于1μm,因为更小的外延柱区4的厚度不能很好地对其下方区域的电场进行调制,造成耐压下降。在一个实施例中,外延柱区4的顶部比有源区1的顶部低,以便将终端区域与有源区1顶部隔离开来。Referring to FIGS. 3 and 4 , in one embodiment, the sidewalls of the active region epitaxial pillars 10 are provided with an inversion injection layer 12 , so as to form a super junction structure in the active region. In one embodiment, the doping type of the inversion implant sidewall 3 is opposite to that of the epitaxial pillar 2 . In one embodiment, the inversion implanted sidewalls 3 are formed by ion implantation on the sidewalls of the epitaxial pillars 2 . In one embodiment, the epitaxial pillar 2 is perpendicular to the active region 1 . In one embodiment, the width refers to the dimension parallel to the edge of the active region, the width of the epitaxial pillar region 2 is less than 10 μm, and the width of the trench 5 is less than 10 μm, because the larger epitaxial pillar region 4 and trench The groove width 5 cannot realize the mutual depletion of the N-type region and the P-type region charge or can deplete each other, but the electric field at the junction of the epitaxial column 2 and the inversion sidewall 3 is too large, which reduces the withstand voltage. In one embodiment, the thickness of the epitaxial column region 4 is greater than 1 μm, because the smaller thickness of the epitaxial column region 4 cannot well modulate the electric field in the region below it, resulting in a drop in withstand voltage. In one embodiment, the top of epitaxial pillar region 4 is lower than the top of active region 1 in order to isolate the termination region from the top of active region 1 .

在一个实施例中,实际制作过程包括:In one embodiment, the actual manufacturing process includes:

第一步,在N型半导体衬底上生长一层半导体外延层,其掺杂仍然是N型掺杂,掺杂浓度为1×1015cm-3~1×1017cm-3In the first step, a semiconductor epitaxial layer is grown on the N-type semiconductor substrate, and its doping is still N-type doping, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 ;

第二步,将有源区保护起来,使用干法刻蚀在终端区域将P型注入区刻掉;The second step is to protect the active area, and use dry etching to etch away the P-type implanted area in the terminal area;

第三步,去掉有源区的保护材料,按照图3和图4所示通过光刻在外延层表面绘制有源区超级结条纹和终端超级结条纹图案,条纹间距小于10μm,刻蚀深度大于5μm。The third step is to remove the protective material in the active area, and draw the active area super junction stripes and terminal super junction stripe patterns on the surface of the epitaxial layer by photolithography as shown in Figure 3 and Figure 4. The stripe spacing is less than 10μm, and the etching depth is greater than 5μm.

第三步,通过两次倾斜侧壁离子注入,在有源区沟槽和终端沟槽的侧壁均注入P型杂质,掺杂浓度为1×1015cm-3~1×1019cm-3,注入深度小于3μm,并控制注入量使得P型杂质和N型外延柱区中的杂质总量大致相同,形成电荷平衡。In the third step, through two inclined sidewall ion implantation, P-type impurities are implanted into the sidewalls of the active region trench and the terminal trench, and the doping concentration is 1×10 15 cm -3 -1×10 19 cm - 3. The implantation depth is less than 3 μm, and the implantation amount is controlled so that the total amount of impurities in the P-type impurity and N-type epitaxial pillar regions is approximately the same to form a charge balance.

由此形成的在有源区周围均为带有反型注入侧壁的超级结终端的超级结肖特基二极管,在阴极加正电压,阳极接地时,可以在终端区域获得均匀的电场分布,从而在较小的面积中实现较大的击穿电压,使终端的击穿电压大于有源区的击穿电压。注意本实施例中的所述的N型和P型掺杂可以互换,同样可以产生类似的效果。The resulting super junction Schottky diodes are super junction terminals with inversion sidewalls around the active region. When a positive voltage is applied to the cathode and the anode is grounded, a uniform electric field distribution can be obtained in the terminal region. Thus, a larger breakdown voltage is achieved in a smaller area, so that the breakdown voltage of the terminal is greater than that of the active region. Note that the N-type and P-type doping described in this embodiment can be interchanged, and similar effects can also be produced.

虽然已参照几个典型实施例描述了本发明,但应当理解,所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质,所以应当理解,上述实施例不限于任何前述的细节,而应在随附权利要求所限定的精神和范围内广泛地解释,因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。While the present invention has been described with reference to several exemplary embodiments, it is to be understood that the terms used are of description and illustration, and not of limitation. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it is to be understood that the above-described embodiments are not limited to any of the foregoing details, but are to be construed broadly within the spirit and scope defined by the appended claims Therefore, all changes and modifications that come within the scope of the claims or their equivalents should be covered by the appended claims.

Claims (11)

1. A super junction termination with inversion implanted sidewalls, the super junction termination at an edge of an active region, comprising:
a substrate;
the epitaxial column regions are positioned above the substrate and around the active region to surround the active region, each epitaxial column region comprises an epitaxial column and an inversion injection side wall, the inversion injection side wall is positioned on the side wall of the epitaxial column, and the doping type of the inversion injection side wall is opposite to that of the epitaxial column; and
and a plurality of trenches alternately arranged with the plurality of epitaxial pillar regions, each trench being located between two adjacent epitaxial pillar regions.
2. The super-junction termination of claim 1 wherein the inversion implant sidewalls are formed by ion implantation at sidewalls of the epitaxial pillar.
3. The super junction termination of claim 1, wherein an extension direction of the epitaxial pillar of the super junction termination is perpendicular to an edge of the active region.
4. The super-junction termination of claim 1 wherein the active region comprises an active region epitaxial pillar, the extension direction of the epitaxial pillar of the super-junction termination being parallel or perpendicular to the extension direction of the active region epitaxial pillar.
5. The super-junction termination of claim 4 wherein sidewalls of the active region epitaxial pillar comprise an inversion implant layer, the inversion implant layer being of the same doping type as the inversion implant sidewalls of the super-junction termination.
6. The super junction termination of claim 1, wherein a top of the epitaxial pillar region is lower than a top of the active region.
7. The super-junction termination of claim 1 wherein the width of the epitaxial pillar is less than 10 μ ι η, the width of the trench is less than 10 μ ι η, and the thickness of the epitaxial pillar is greater than 1 μ ι η.
8. A method of fabricating a super junction termination with inversion implantation sidewalls at the edge of an active region, the method comprising:
growing an epitaxial layer on a substrate;
etching a plurality of epitaxial columns on the epitaxial layer by using a mask, etching the epitaxial columns to the substrate or etching the epitaxial columns to a distance above the substrate, wherein the plurality of epitaxial columns are positioned around the active region and surround the active region; and
performing ion implantation on one or two side walls of each epitaxial column to form inversion implantation side walls, wherein the doping type of the inversion implantation side walls is opposite to that of the epitaxial columns; wherein
And a groove is formed between two adjacent epitaxial columns and is alternately arranged with the epitaxial columns.
9. The method of claim 8, wherein the extension direction of the epitaxial pillar of the super junction termination is perpendicular to the edge of the active region.
10. The method of manufacturing of claim 8, further comprising:
drawing patterns of active region super junction stripes and terminal super junction stripes on the surface of the epitaxial layer through photoetching;
forming an active region groove; and
and injecting P-type impurities into the side walls of the active region groove and the terminal groove by two times of inclined side wall ion injection.
11. The method of manufacturing of claim 8, further comprising: the total amount of impurities in the implanted sidewall and the total amount of impurities in the epitaxial column are controlled to be approximately the same.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070052061A1 (en) * 1998-07-17 2007-03-08 Infineon Technologies Ag Semiconductor layer with laterally variable doping, and method for producing it
CN101241933A (en) * 2007-02-06 2008-08-13 半导体元件工业有限责任公司 Semiconductor device with trench edge termination structure
CN102214582A (en) * 2011-05-26 2011-10-12 上海先进半导体制造股份有限公司 Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device
CN102623504A (en) * 2012-03-29 2012-08-01 无锡新洁能功率半导体有限公司 Super junction semiconductor device with novel terminal structure and method for manufacturing same
CN103050535A (en) * 2012-08-22 2013-04-17 上海华虹Nec电子有限公司 Super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure having groove type terminal structure and preparation method thereof
CN103165670A (en) * 2011-12-09 2013-06-19 上海华虹Nec电子有限公司 Terminal protection structure of super junction component
CN104332489A (en) * 2014-10-23 2015-02-04 吉林华微电子股份有限公司 Terminal with surface super-structure and of semiconductor device
CN104465391A (en) * 2013-09-13 2015-03-25 株式会社东芝 Method of manufacturing semiconductor device
US20150206966A1 (en) * 2014-01-17 2015-07-23 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
CN106129119A (en) * 2016-08-31 2016-11-16 西安龙腾新能源科技发展有限公司 Domain structure of superjunction power VDMOSFET of integrated schottky diode and preparation method thereof
CN107507857A (en) * 2017-08-10 2017-12-22 中航(重庆)微电子有限公司 Autoregistration super-junction structure and preparation method thereof
CN110429130A (en) * 2019-08-31 2019-11-08 电子科技大学 The groove profile device terminal structure of charge balance
CN110649096A (en) * 2019-10-08 2020-01-03 电子科技大学 High-voltage n-channel HEMT device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070052061A1 (en) * 1998-07-17 2007-03-08 Infineon Technologies Ag Semiconductor layer with laterally variable doping, and method for producing it
CN101241933A (en) * 2007-02-06 2008-08-13 半导体元件工业有限责任公司 Semiconductor device with trench edge termination structure
CN102214582A (en) * 2011-05-26 2011-10-12 上海先进半导体制造股份有限公司 Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device
CN103165670A (en) * 2011-12-09 2013-06-19 上海华虹Nec电子有限公司 Terminal protection structure of super junction component
CN102623504A (en) * 2012-03-29 2012-08-01 无锡新洁能功率半导体有限公司 Super junction semiconductor device with novel terminal structure and method for manufacturing same
CN103050535A (en) * 2012-08-22 2013-04-17 上海华虹Nec电子有限公司 Super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure having groove type terminal structure and preparation method thereof
CN104465391A (en) * 2013-09-13 2015-03-25 株式会社东芝 Method of manufacturing semiconductor device
US20150206966A1 (en) * 2014-01-17 2015-07-23 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
CN104332489A (en) * 2014-10-23 2015-02-04 吉林华微电子股份有限公司 Terminal with surface super-structure and of semiconductor device
CN106129119A (en) * 2016-08-31 2016-11-16 西安龙腾新能源科技发展有限公司 Domain structure of superjunction power VDMOSFET of integrated schottky diode and preparation method thereof
CN107507857A (en) * 2017-08-10 2017-12-22 中航(重庆)微电子有限公司 Autoregistration super-junction structure and preparation method thereof
CN110429130A (en) * 2019-08-31 2019-11-08 电子科技大学 The groove profile device terminal structure of charge balance
CN110649096A (en) * 2019-10-08 2020-01-03 电子科技大学 High-voltage n-channel HEMT device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112420807A (en) * 2020-11-04 2021-02-26 浙江大学 A super junction device and its terminal

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