CN104332489A - Terminal with surface super-structure and of semiconductor device - Google Patents

Abstract

A terminal with a surface super junction structure of a semiconductor device enables the semiconductor device to have good withstand voltage and stability, and belongs to the technical field of semiconductor devices. The manufacturing process of the prior art device needs to be simplified, and the withstand voltage performance of the device needs to be improved. In the terminal with the surface super junction structure of the semiconductor device of the present invention, the surface super junction structure is composed of a plurality of P-type impurity regions and N-type impurity regions arranged alternately, and it is characterized in that the surface super junction structure is located in the device On the chip terminal surface, each P-type impurity region and N-type impurity region extends from the boundary of the active region to the edge of the chip. The invention can reduce the surface electric field strength of the chip terminal of the semiconductor device, significantly improve the withstand voltage level per unit width of the chip terminal, and the withstand voltage capability can even be equivalent to that of an insulator. At the same time, the process of fabricating the surface superjunction structure is very conventional and simple.

Description

Termination of semiconductor devices with surface superjunction structures

technical field

The invention relates to a terminal with a surface super junction structure of a semiconductor device, in particular to the terminal structure of the semiconductor device, which enables the semiconductor device to have good withstand voltage and stability, and belongs to the technical field of semiconductor devices.

Background technique

In the terminal structure of the device chip, as the reverse bias voltage of the device increases, the depletion region expands to both sides of the PN junction, and a high electric field appears on the terminal surface, which reduces the withstand voltage of the device. As the number of PN junctions on the terminal surface increases and With the increase of the withstand voltage of the PN junction, the surface electric field distribution becomes more complicated. In the prior art, the terminal structure design is used to reduce the electric field intensity on the surface of the device chip terminal and increase the breakdown voltage close to the parallel PN junction inside the device, thereby improving the withstand voltage performance of the device. Existing semiconductor device termination technologies related to this include field plate termination technology, JTE (Junction Termination Extension) termination technology, VLD (Variable Lateral Doping) termination technology and Field Limiting Ring termination technology.

The resistance field plate technology in the field plate termination technology uses oxygen-doped polysilicon (SIPOS) as the resistance field plate of the device. When the device is reverse biased, the potential distribution in the polysilicon from the active area to the edge of the device chip increases approximately linearly, while the device chip The potential distribution rises faster at the terminal silicon interface. In this way, two favorable results are obtained: (1) the electric field intensity distribution on the surface of the device chip becomes flat; (2) the field plate potential is lower than the Si surface at any place, which increases the depletion of the PN junction at the surface. Zone width is advantageous. Therefore, the breakdown voltage is improved. However, the manufacturing process of the oxygen-doped polysilicon resistance field plate is complicated, for example, it is necessary to increase the deposition process of the polysilicon layer, and the process parameters in the production are not easy to control, such as the ratio of oxygen doping.

In JTE terminal technology and VLD terminal technology, due to the relatively low surface concentration, they are sensitive to surface charges, are easily affected by interface charges, and device stability is affected.

In the field limiting ring termination technology, in order to improve the withstand voltage of the semiconductor device, the termination structure of the existing semiconductor device is usually a combination of a field limiting ring and a floating field plate.

Therefore, it is necessary to find a more effective terminal technology to improve the withstand voltage performance of the device.

Contents of the invention

In order to simplify the manufacturing process of the device and improve the withstand voltage performance of the device, we invented a terminal of a semiconductor device with a surface super junction structure.

In the terminal with the surface super junction structure of the semiconductor device of the present invention, the surface super junction structure is composed of a plurality of P-type impurity regions and N-type impurity regions arranged alternately, and it is characterized in that the surface super junction structure is located in the device On the surface of the chip terminal 1, each P-type impurity region 2 and N-type impurity region 3 extends from the boundary 4 of the active region to the edge 5 of the chip, as shown in FIGS. 1-4 .

The technical effect of the present invention is that since the withstand voltage mechanism of the surface super junction structure (Surface Super Junction, referred to as SCSJ) is different from that of the usual PN junction, after the surface super junction structure is reverse biased, the peak value of the electric field moves to the two sides of the surface super junction structure. In the surface super junction structure, the electric field distribution on the surface of the super junction region is uniform. In fact, a voltage-resistant layer with uniform electric field distribution is formed on the terminal surface of the device chip from the boundary of the active region to the edge of the chip. Since the two ends of the voltage-resistant layer are At the edge of the chip at the boundary of the active area of the chip, the surface electric field is expanded to the greatest extent, reducing the intensity of the surface electric field. The potential of the semiconductor under the surface of the terminal is smaller than that of the surface layer of the terminal surface. Therefore, the depletion region of the chip is also stretched under the pulling of the surface of the terminal, so that the surface electric field intensity distribution is further smoothed, the intensity is further reduced, and the withstand voltage level of the unit width of the chip terminal is obtained. Significantly improved, the withstand voltage capability can even be equivalent to that of an insulator. Since the impurity concentration of the P-type impurity region and the N-type impurity region constituting the super junction structure can reach a very high level, the surface super junction structure is not sensitive to surface charges, and the device withstand voltage is stable. Moreover, by changing the width of the chip terminal, that is, the length of the super junction, the withstand voltage of the device can be adjusted, which is convenient and simple. At the same time, the process of fabricating the surface superjunction structure is very conventional and simple.

Viewed from another perspective, the present invention can also reduce the chip terminal size, reduce the sensitivity to interface charge and improve the withstand voltage stability of the device without reducing the withstand voltage level of the device.

Description of drawings

Fig. 1 is a schematic top view of a terminal structure with a surface super junction structure according to the present invention, which is also used as a summary drawing. Fig. 2 is a schematic plan view of the structure of the four corners of the terminal chip with a surface super junction structure according to the present invention, which simultaneously shows each P-type impurity region and N-type impurity region in the four corners of the rectangular chip in a radial form from the boundary of the active region extending to the chip edge. Fig. 3 is a partial perspective view of a structure with a surface super junction of the present invention. Fig. 4 is a schematic partial cross-sectional view of a structure with a surface super junction of the present invention. Fig. 5 is a schematic plan view of the four corners of the chip of the terminal with a surface super junction structure according to the present invention, which also shows a P-type impurity region extending from the boundary of the active region to the chip along the diagonal of the rectangular chip at the four corners of the rectangular chip edge.

Detailed ways

In the terminal with the surface super junction structure of the semiconductor device of the present invention, the surface super junction structure is composed of a plurality of P-type impurity regions and N-type impurity regions arranged alternately. The surface super junction structure is located on the surface of the device chip terminal 1, and each P-type impurity region 2 and N-type impurity region 3 extends from the active region boundary 4 to the chip edge 5, as shown in FIGS. 1-4 . The fabrication method of the surface super junction structure is one of three methods of photolithography selective diffusion, groove doping and groove epitaxy. The impurity concentration, width and depth of each P-type impurity region 2 and N-type impurity region 3 of the surface super junction structure are optimized and adjusted according to the RESURF method. The widths of the P-type impurity region 2 and the N-type impurity region 3 are equal or unequal. When the widths of the P-type impurity region 2 and the N-type impurity region 3 are not equal, the width of the P-type impurity region 2 is larger or smaller than the width of the N-type impurity region 3 . The depths of the P-type impurity region 2 and the N-type impurity region 3 are equal or unequal. When the depths of the P-type impurity region 2 and the N-type impurity region 3 are not equal, the depth of the P-type impurity region 2 is larger or smaller than the depth of the N-type impurity region 3 .

At the four corners of the rectangular chip, each P-type impurity region 2 and N-type impurity region 3 in the surface super junction structure extends from the active region boundary 4 to the chip edge 5 in one of the following two forms:

1. Extend radially around the geometric center of the rectangular chip, as shown in Figure 2. If the distance from the active region boundary 4 to the chip edge 5 is defined as the width of the surface super junction structure, then the width of the part of the surface super junction structure located at the four corners of the rectangular chip is greater than or equal to the surface super junction structure. The width of the portion of the structure located on the four sides of the rectangular chip. Since the electric field intensity at the four corners of the rectangular chip is relatively large, when the width relationship is larger than that, it is beneficial to reduce the electric field intensity, thereby improving the withstand voltage level of the chip.

2. A P-type impurity region 2 extends along the diagonal of the rectangular chip. As shown in FIG. The direction is parallel to the direction of other P-type impurity regions 2 on this side. Such a regular distribution is conducive to realizing charge balance and improving the withstand voltage performance of the chip terminal of the device.

Claims (8)

1. A terminal with a surface super junction structure of a semiconductor device, the surface super junction structure is composed of a plurality of P-type impurity regions and N-type impurity regions alternately arranged, it is characterized in that the surface super junction structure is located on the device chip On the surface of the terminal (1), each P-type impurity region (2) and N-type impurity region (3) extends from the boundary of the active region (4) to the edge of the chip (5). 2. The terminal with the surface super junction structure of the semiconductor device according to claim 1, characterized in that, the fabrication methods of the surface super junction structure are photolithographic selective diffusion, groove doping and groove epitaxy. one of the ways. 3. The terminal with the surface super junction structure of the semiconductor device according to claim 1, characterized in that the impurities of each P-type impurity region (2) and N-type impurity region (3) of the surface super junction structure Concentration, width and depth are optimized and adjusted according to the RESURF method. 4. The terminal of a semiconductor device having a surface super junction structure according to claim 1, characterized in that the widths of the P-type impurity region (2) and the N-type impurity region (3) are equal or unequal. 5. The terminal with a surface super junction structure of a semiconductor device according to claim 4, characterized in that, when the widths of the P-type impurity region (2) and the N-type impurity region (3) are not equal, the P-type impurity region The width of (2) is larger or smaller than the width of the N-type impurity region (3). 6. The terminal of a semiconductor device having a surface super junction structure according to claim 1, characterized in that the depths of the P-type impurity region (2) and the N-type impurity region (3) are equal or unequal. 7. The terminal with a surface super junction structure of a semiconductor device according to claim 6, characterized in that, when the depths of the P-type impurity region (2) and the N-type impurity region (3) are not equal, the P-type impurity region The depth of (2) is larger or smaller than the depth of the N-type impurity region (3). 8. The terminal with the surface super junction structure of the semiconductor device according to claim 1, characterized in that, at the four corners of the rectangular chip, each P-type impurity region (2) and N-type impurity region (2) in the surface super junction structure The extension form of the impurity region (3) from the boundary of the active region (4) to the edge of the chip (5) is one of the following two types: A. Extending radially from the geometric center of the rectangular chip, the distance from the active region boundary (4) to the edge of the chip (5) is the width of the surface super junction structure, and the surface super junction structure is located at the four corners of the rectangular chip The width of the part is greater than or equal to the width of the part of the surface super junction structure located at the four sides of the rectangular chip; B. A P-type impurity region (2) extends along the diagonal of the rectangular chip, and there is a group of P-type impurity regions (2) branches on both sides of the P-type impurity region (2), each group of P-type impurity regions (2) The direction of the branch is parallel to the direction of other P-type impurity regions (2) on this side.