CN104576730A - Superjunction device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a super junction device. The current flow region includes a plurality of alternately arranged N-type thin layers and P-type thin layers, and a plurality of grooves are formed on a silicon substrate, and each N-type thin layer is formed by a first N-type thin layer respectively. An N-type thin layer and a second N-type thin layer; the first N-type thin layer is composed of a silicon substrate thin layer between the trenches, the second N-type thin layer has a lower resistivity, and at least the second N-type The charge balance of the thin layer and its adjacent P-type thin layer, the charge imbalance between at least part of the N-type thin layer and its adjacent P-type thin layer, and the bottom of the N-type thin layer and the P-type thin layer are formed by back ion implantation region composed of N-type regions. The invention also discloses a manufacturing method of the super junction device. The invention can minimize the manufacturing cost, and at the same time optimize the specific on-resistance of the device and the softness coefficient of the reverse recovery of the device in the turn-off process.

Description

Superjunction device and method of manufacturing the same

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device.

Background technique

The super junction MOSFET adopts a new voltage-resistant layer structure, and uses a series of alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers to combine the P-type semiconductor thin layers and N-type semiconductor thin layers at a lower voltage in the off state. The thin layer of semiconductor is depleted to achieve mutual compensation of charges, so that the thin layer of P-type semiconductor and thin layer of N-type semiconductor can achieve high breakdown voltage under high doping concentration, so as to obtain low on-resistance and high breakdown at the same time voltage, breaking the theoretical limit of traditional power MOSFETs. In U.S. Patent US5216275, the above alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers are connected to the N+ substrate; in U.S. Patent US6630698B1, the middle P-type semiconductor thin layer and N-type semiconductor thin layer are connected to N+ substrates can have a spacing greater than zero.

In the prior art, the formation of P-type semiconductor thin layer and N-type semiconductor thin layer is through epitaxial growth, followed by photolithography and implantation, and this process is repeated many times to obtain the required thickness of P-type semiconductor thin layer and N-type semiconductor Thin layer, this process generally needs to be repeated more than 5 times in MOSFETs above 600V, and the production cost and production cycle are long. The other is to etch the trench after growing one type of epitaxy with the required thickness at a time, and then fill the trench with silicon of the opposite type; although this method is difficult, it has the advantages of simplifying the process flow and improving The effect of stability; after adopting the trench structure, due to the doping of the P-type semiconductor thin layer and the N-type semiconductor thin layer in the longitudinal direction in the P/N thin layer, that is, the alternately arranged P-type semiconductor thin layer and the N-type semiconductor thin layer The impurity concentration is easy to control, and there is no change in the doping concentration of the P-type semiconductor thin layer and the N-type semiconductor thin layer or one of them in the vertical direction caused by multiple epitaxy processes, which brings additional vertical electric fields, ensuring The device can obtain good leakage characteristics and high breakdown voltage.

In the super junction process, due to the use of alternate P/N thin layers, the body diode of the super junction device, that is, the diode formed between the P-type semiconductor thin layer and the N-type semiconductor thin layer, can operate at a lower reverse bias voltage such as 50 Vds will completely deplete the P-type semiconductor thin layer and the N-type semiconductor thin layer, which makes the diode have a very hard reverse recovery characteristic. This hard reverse recovery characteristic causes the recovery current of the device to change sharply. Severe fluctuations in reverse recovery cause electromagnetic noise (EMI NOISE) in the circuit, which affects the work of other devices in the circuit. In this regard, super junction devices are not as good as conventional MOSFET devices, because conventional MOSFET devices The depletion of the N-drift region always expands with the increase of the voltage (Vds), and the reverse recovery characteristic is soft.

In terms of process selection, multiple epitaxial growth and lithography and implantation processes have complex, long manufacturing cycle and high cost problems. In the trench filling process, it is necessary to deposit on a highly doped substrate before the trench process. The epitaxial layer with a thickness of tens of microns also increases the cost of the process.

Contents of the invention

The technical problem to be solved by the present invention is to provide a super junction device, which can minimize the manufacturing cost, and at the same time optimize the specific on-resistance of the device and the softness coefficient (SOFTNESS) of the reverse recovery of the device during the turn-off process . To this end, the invention also provides a method for manufacturing a super junction device.

In order to solve the above-mentioned technical problems, the super junction device provided by the present invention is formed on an N-type silicon substrate, the middle region of the super junction device is a current flow region, and the terminal protection structure surrounds the periphery of the current flow region; the current flow The region includes a plurality of alternately arranged N-type thin layers and P-type thin layers.

A plurality of grooves are formed on the silicon substrate, and each of the N-type thin layers is composed of a first N-type thin layer and a second N-type thin layer; the first N-type thin layer is composed of the The silicon substrate thin layer between the grooves, the second N-type thin layer is composed of the first N-type silicon epitaxial layer filled in the groove and located on both sides of the first N-type thin layer, The P-type thin layer is composed of a second P-type silicon epitaxial layer filled in the groove, each of the P-type thin layers is in contact with the second N-type thin layer on both sides thereof, and the corresponding The trenches are completely filled.

The resistivity of the second N-type thin layer is lower than the resistivity of the silicon substrate, and the N-type doping of the first N-type thin layer is composed of the N-type impurities of the silicon substrate plus the The second N-type thin layer is composed of N-type impurities diffused into it.

The first N-type thin layer of all or part of the N-type thin layer includes a high-resistivity part, and the N-type thin layer including the high-resistivity part has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer does not spread over the entire width of the first N-type thin layer, and the resistivity of the silicon substrate is the same as that of the second N-type thin layer. The resistivity of the layer is more than 10 times, the resistivity of the middle region of the first N-type thin layer is equal to the resistivity of the silicon substrate, and the middle region of the first N-type thin layer forms the high Resistivity part.

At least the charge balance of the second N-type thin layer and its adjacent P-type thin layer, including the unbalance of the N-type thin layer and its adjacent P-type thin layer of the high-resistivity portion , when a reverse bias voltage is connected between the N-type thin layer and the P-type thin layer, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not blocked by the P-type thin layer Layers are fully depleted laterally.

An N-type region composed of a rear ion implantation region is formed at the bottom of the N-type thin layer and the P-type thin layer.

A further improvement is that the widths of the N-type thin layers in the current flow region are all the same, and the first N-type thin layer of all the N-type thin layers includes the high-resistivity portion.

Alternatively, the N-type thin layer in the current flow region includes more than two kinds of widths, the N-type thin layer with the largest width includes the high-resistivity portion, and the N-type thin layer with a width smaller than the largest width The N-type thin layer includes or does not include the high-resistivity portion; the N-type thin layer that does not include the high-resistivity portion has a feature: diffused from the second N-type thin layer into the first N-type thin layer The N-type impurities in the thin layer spread throughout the width of the first N-type thin layer, and the resistivity of the middle region of the first N-type thin layer is lower than that of the silicon substrate.

A further improvement is that the N-type region is composed of a first-layer N-type region and a second-layer N-type region, and the first-layer N-type region is close to the bottom of the N-type thin layer and the P-type thin layer, The N-type region of the second layer is close to the back side of the silicon substrate, the doping concentration of the N-type region of the second layer is greater than the doping concentration of the N-type region of the first layer, and the N-type region of the second layer The doping concentration of the region satisfies the condition of forming an ohmic contact with the metal formed on the back side of the silicon substrate, and the first N-type region serves as a buffer layer of the super junction device.

A further improvement is that the thickness of the N-type region is 0.5 microns to 5 microns.

A further improvement is that the thickness of the N-type region of the first layer is 3 microns to 50 microns, and the thickness of the N-type region of the second layer is 0.5 microns to 3 microns.

A further improvement is that a P-type region composed of a rear ion implantation region is also formed on the back of the N-type region.

A further improvement is that the N-type thin layer including the high-resistivity portion in the current flow region is distributed in one or more regions of the current flow region.

A further improvement is that, in the current flow region, the distribution region of the N-type thin layer including the high-resistivity portion is not adjacent to the region of the terminal protection structure.

A further improvement is that the distribution area of the N-type thin layer including the high-resistivity part in the current flow area is not adjacent to the area of the gate metal electrode pattern of the super junction device.

In order to solve the above-mentioned technical problems, the super junction device of the manufacturing method of the super junction device provided by the present invention is a super junction trench gate MOSFET device, comprising the following steps:

Step 1, sequentially depositing a first silicon dioxide layer, a second silicon nitride layer and a third silicon dioxide layer on the surface of an N-type silicon substrate; , the second silicon nitride layer and the first silicon dioxide layer form a trench pattern mask.

Step 2, using the trench pattern mask as a mask to etch the silicon substrate to form a plurality of trenches; the middle area of the super junction device is the current flow area, and the terminal protection structure surrounds the current flow area. The periphery of the flow area; in the current flow area, the silicon substrate between each of the grooves has a thin layer structure and is composed of a thin layer of silicon substrate between each of the grooves. type thin layer; sequentially remove the third silicon dioxide layer and the second silicon nitride layer of the trench pattern mask, and keep the first silicon dioxide layer.

Step 3, depositing and forming a first N-type silicon epitaxial layer on the front side of the silicon substrate, the first N-type silicon epitaxial layer is formed on the bottom surface and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the layer forms a second N-type thin layer, and each of the first N-type thin layers plus the second N-type thin layer on both sides constitutes a corresponding N-type thin layer. layer.

The resistivity of the second N-type thin layer is lower than the resistivity of the silicon substrate, and the N-type doping of the first N-type thin layer is composed of the N-type impurities of the silicon substrate plus the The second N-type thin layer is composed of N-type impurities diffused into it.

The first N-type thin layer of all or part of the N-type thin layer includes a high-resistivity part, and the N-type thin layer including the high-resistivity part has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer does not spread over the entire width of the first N-type thin layer, and the resistivity of the silicon substrate is the same as that of the second N-type thin layer. The resistivity of the layer is more than 10 times, the resistivity of the middle region of the first N-type thin layer is equal to the resistivity of the silicon substrate, and the middle region of the first N-type thin layer forms the high Resistivity part.

Step 4, depositing and forming a second P-type silicon epitaxial layer on the front side of the silicon substrate, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and completely fills the trench ; removing both silicon and silicon oxide from the top surface of the trench.

In the current flow region, the P-type thin layer is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer and the N-type thin layer in the current flow region The thin layers are arranged alternately.

At least the charge balance of the second N-type thin layer and its adjacent P-type thin layer, including the unbalance of the N-type thin layer and its adjacent P-type thin layer of the high-resistivity portion , when a reverse bias voltage is connected between the N-type thin layer and the P-type thin layer, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not blocked by the P-type thin layer Layers are fully depleted laterally.

Step 5, forming a gate trench on the top of the N-type thin layer in the current flow region by using a photolithography process.

Step 6, depositing a gate dielectric layer and a polysilicon gate in sequence, the gate dielectric layer covers the bottom surface, side surfaces and outside of the gate trench, the polysilicon gate is formed on the surface of the gate dielectric layer and the gate The trench is completely filled, the gate dielectric layer and the polysilicon gate outside the gate trench are removed, and the super junction trench is formed by the gate dielectric layer and the polysilicon gate filled inside the gate trench Gate structure of a trench-gate MOSFET device.

Step 7, forming a P well on the top of the N-type thin layer and the P-type thin layer; the depth of the gate trench is greater than the depth of the P well, and the polysilicon gate covers the P well from the side, And the side of the P well covered by the polysilicon gate is used to form a vertical channel.

Step 8: performing N+ ion implantation to form a source region; the source region is formed on the top of the P well on both sides of the gate trench on the top of the N-type thin layer.

Step 9, forming an interlayer film on the front side of the silicon substrate on which the source region is formed; using a photolithography process to form a contact hole, the contact hole passing through the interlayer film and connecting with the source region or The polysilicon gate contact; performing P+ ion implantation to form a P well lead-out region, the P well lead-out region is located at the bottom of the contact hole in contact with the source region, and the P well lead-out region is in contact with the P well .

Step 10, depositing front metal and performing photolithography on the front metal to form source and gate respectively.

Step eleven, thinning the silicon substrate from the back side.

Step 12: performing backside ion implantation to form an N-type region, the N-type region is located at the bottom of the N-type thin layer and the P-type thin layer.

Step thirteen, activating the ions in the N-type region.

Step 14, performing back metallization to form a drain.

A further improvement is that the distance between the back surface of the silicon substrate thinned in step 11 and the bottom surface of the trench formed in step 2 is 0.5 microns to 40 microns.

A further improvement is that the activation process in step 13 includes at least one laser annealing.

A further improvement is that the process of forming the P well in step 7 is carried out before the deposition of the first silicon dioxide layer in step 1.

In order to solve the above technical problems, the super junction device of the manufacturing method of the super junction device provided by the present invention is a super junction planar gate MOSFET device, comprising the following steps:

Step 1, sequentially depositing a first silicon dioxide layer, a second silicon nitride layer and a third silicon dioxide layer on the surface of an N-type silicon substrate; , the second silicon nitride layer and the first silicon dioxide layer form a trench pattern mask.

Step 2, using the trench pattern mask as a mask to etch the silicon substrate to form a plurality of trenches; the middle area of the super junction device is the current flow area, and the terminal protection structure surrounds the current flow area. The periphery of the flow area; in the current flow area, the silicon substrate between each of the grooves has a thin layer structure and is composed of a thin layer of silicon substrate between each of the grooves. type thin layer; sequentially remove the third silicon dioxide layer and the second silicon nitride layer of the trench pattern mask, and keep the first silicon dioxide layer.

Step 3, depositing and forming a first N-type silicon epitaxial layer on the front side of the silicon substrate, the first N-type silicon epitaxial layer is formed on the bottom surface and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the layer forms a second N-type thin layer, and each of the first N-type thin layers plus the second N-type thin layer on both sides constitutes a corresponding N-type thin layer. layer.

The resistivity of the second N-type thin layer is lower than the resistivity of the silicon substrate, and the N-type doping of the first N-type thin layer is composed of the N-type impurities of the silicon substrate plus the The second N-type thin layer is composed of N-type impurities diffused into it.

The first N-type thin layer of all or part of the N-type thin layer includes a high-resistivity part, and the N-type thin layer including the high-resistivity part has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer does not spread over the entire width of the first N-type thin layer, and the resistivity of the silicon substrate is the same as that of the second N-type thin layer. The resistivity of the layer is more than 10 times, the resistivity of the middle region of the first N-type thin layer is equal to the resistivity of the silicon substrate, and the middle region of the first N-type thin layer forms the high Resistivity part.

Step 4, depositing and forming a second P-type silicon epitaxial layer on the front side of the silicon substrate, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and completely fills the trench ; removing both silicon and silicon oxide from the top surface of the trench.

In the current flow region, the P-type thin layer is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer and the N-type thin layer in the current flow region The thin layers are arranged alternately.

At least the charge balance of the second N-type thin layer and its adjacent P-type thin layer, including the unbalance of the N-type thin layer and its adjacent P-type thin layer of the high-resistivity portion , when a reverse bias voltage is connected between the N-type thin layer and the P-type thin layer, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not blocked by the P-type thin layer Layers are fully depleted laterally.

Step 5, forming a P well on the top of each of the P-type thin layers, and each of the P wells also extends to a part of the top of the N-type thin layer; the top region of the N-type thin layer between each of the P wells It is an N-type conduction region.

Step 6, sequentially depositing a gate dielectric layer and a polysilicon gate, and sequentially etching the polysilicon gate and the gate dielectric layer by using a photolithography etching process, the etched gate dielectric layer and the polysilicon gate Composing the gate structure of the super junction planar gate MOSFET device; the polysilicon gate covers the N-type thin layer and part of the P well from the top, and the P well covered by the polysilicon gate is used to form lateral channel.

Step 7, performing N+ ion implantation to form a source region; the source region is formed on the top of the P well and self-aligned with the polysilicon gate.

Step 8, forming an interlayer film on the front side of the silicon substrate on which the source region is formed; forming a contact hole by using a photolithography process, the contact hole passing through the interlayer film and connecting with the source region or The polysilicon gate contact; performing P+ ion implantation to form a P well lead-out region, the P well lead-out region is located at the bottom of the contact hole in contact with the source region, and the P well lead-out region is in contact with the P well .

Step 9, depositing front metal and performing photolithography on the front metal to form source and gate respectively.

Step 10, thinning the silicon substrate from the back side.

Step 11. Perform backside ion implantation to form an N-type region, the N-type region is located at the bottom of the N-type thin layer and the P-type thin layer.

Step twelve, activating the ions in the N-type region.

Step thirteen, performing back metallization to form a drain.

A further improvement is that the distance between the back surface of the silicon substrate thinned in step ten and the bottom surface of the groove formed in step two is 0.5 microns to 40 microns.

A further improvement is that the activation process in step 12 includes at least one laser annealing.

A further improvement is that the process of forming the P well in step 5 is performed before the deposition of the first silicon dioxide layer in step 1.

A further improvement is that, after the formation of the P well in step five and before the deposition of the gate dielectric layer in step six, a step of performing N-type ion implantation in the N-type conduction region is also included.

In order to solve the above technical problems, the super junction device of the manufacturing method of the super junction device provided by the present invention is a super junction trench gate IGBT device, comprising the following steps:

Step 1, sequentially depositing a first silicon dioxide layer, a second silicon nitride layer and a third silicon dioxide layer on the surface of an N-type silicon substrate; , the second silicon nitride layer and the first silicon dioxide layer form a trench pattern mask.

Step 2, using the trench pattern mask as a mask to etch the silicon substrate to form a plurality of trenches; the middle area of the super junction device is the current flow area, and the terminal protection structure surrounds the current flow area. The periphery of the flow area; in the current flow area, the silicon substrate between each of the grooves has a thin layer structure and is composed of a thin layer of silicon substrate between each of the grooves. type thin layer; sequentially remove the third silicon dioxide layer and the second silicon nitride layer of the trench pattern mask, and keep the first silicon dioxide layer.

Step 3, depositing and forming a first N-type silicon epitaxial layer on the front side of the silicon substrate, the first N-type silicon epitaxial layer is formed on the bottom surface and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the layer forms a second N-type thin layer, and each of the first N-type thin layers plus the second N-type thin layer on both sides constitutes a corresponding N-type thin layer. layer.

The resistivity of the second N-type thin layer is lower than the resistivity of the silicon substrate, and the N-type doping of the first N-type thin layer is composed of the N-type impurities of the silicon substrate plus the The second N-type thin layer is composed of N-type impurities diffused into it.

The first N-type thin layer of all or part of the N-type thin layer includes a high-resistivity part, and the N-type thin layer including the high-resistivity part has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer does not spread over the entire width of the first N-type thin layer, and the resistivity of the silicon substrate is the same as that of the second N-type thin layer. The resistivity of the layer is more than 10 times, the resistivity of the middle region of the first N-type thin layer is equal to the resistivity of the silicon substrate, and the middle region of the first N-type thin layer forms the high Resistivity part.

Step 4, depositing and forming a second P-type silicon epitaxial layer on the front side of the silicon substrate, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and completely fills the trench ; removing both silicon and silicon oxide from the top surface of the trench.

In the current flow region, the P-type thin layer is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer and the N-type thin layer in the current flow region The thin layers are arranged alternately.

At least the charge balance between the second N-type thin layer and its adjacent P-type thin layer, the charge balance or imbalance between the N-type thin layer and its adjacent P-type thin layer, the N-type thin layer When the reverse bias voltage is connected between the thin layer and the P-type thin layer, the entire N-type thin layer is completely depleted laterally, or the first N-type thin layer of the N-type thin layer is not blocked by the P-type thin layer Layers are fully depleted laterally.

Step 5, forming a gate trench on the top of the N-type thin layer in the current flow region by using a photolithography process.

Step 6, depositing a gate dielectric layer and a polysilicon gate in sequence, the gate dielectric layer covers the bottom surface, side surfaces and outside of the gate trench, the polysilicon gate is formed on the surface of the gate dielectric layer and the gate The trench is completely filled, the gate dielectric layer and the polysilicon gate outside the gate trench are removed, and the super junction trench is formed by the gate dielectric layer and the polysilicon gate filled inside the gate trench Gate structure of a trench-gate MOSFET device.

Step 7, forming a P well on the top of the N-type thin layer and the P-type thin layer; the depth of the gate trench is greater than the depth of the P well, and the polysilicon gate covers the P well from the side, And the side of the P well covered by the polysilicon gate is used to form a vertical channel.

Step 8: performing N+ ion implantation to form a source region; the source region is formed on the top of the P well on both sides of the gate trench on the top of the N-type thin layer.

Step 9, forming an interlayer film on the front side of the silicon substrate on which the source region is formed; using a photolithography process to form a contact hole, the contact hole passing through the interlayer film and connecting with the source region or The polysilicon gate contact; performing P+ ion implantation to form a P well lead-out region, the P well lead-out region is located at the bottom of the contact hole in contact with the source region, and the P well lead-out region is in contact with the P well .

Step 10, depositing front metal and performing photolithography on the front metal to form source and gate respectively.

Step eleven, thinning the silicon substrate from the back side.

Step 12, perform back ion implantation to form an N-type region, the N-type region is located at the bottom of the N-type thin layer and the P-type thin layer; perform back ion implantation to form a P-type region on the back of the N-type region .

Step thirteen, activating the ions in the N-type region and the P-type region.

Step 14, performing back metallization to form a drain.

In order to solve the above technical problems, the super junction device of the manufacturing method of the super junction device provided by the present invention is a super junction planar gate MOSFET device, comprising the following steps:

Step 1, sequentially depositing a first silicon dioxide layer, a second silicon nitride layer and a third silicon dioxide layer on the surface of an N-type silicon substrate; , the second silicon nitride layer and the first silicon dioxide layer form a trench pattern mask.

Step 2, using the trench pattern mask as a mask to etch the silicon substrate to form a plurality of trenches; the middle area of the super junction device is the current flow area, and the terminal protection structure surrounds the current flow area. The periphery of the flow area; in the current flow area, the silicon substrate between each of the grooves has a thin layer structure and is composed of a thin layer of silicon substrate between each of the grooves. type thin layer; sequentially remove the third silicon dioxide layer and the second silicon nitride layer of the trench pattern mask, and keep the first silicon dioxide layer.

Step 3, depositing and forming a first N-type silicon epitaxial layer on the front side of the silicon substrate, the first N-type silicon epitaxial layer is formed on the bottom surface and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the layer forms a second N-type thin layer, and each of the first N-type thin layers plus the second N-type thin layer on both sides constitutes a corresponding N-type thin layer. layer.

The resistivity of the second N-type thin layer is lower than the resistivity of the silicon substrate, and the N-type doping of the first N-type thin layer is composed of the N-type impurities of the silicon substrate plus the The second N-type thin layer is composed of N-type impurities diffused into it.

The first N-type thin layer of all or part of the N-type thin layer includes a high-resistivity part, and the N-type thin layer including the high-resistivity part has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer does not spread over the entire width of the first N-type thin layer, and the resistivity of the silicon substrate is the same as that of the second N-type thin layer. The resistivity of the layer is more than 10 times, the resistivity of the middle region of the first N-type thin layer is equal to the resistivity of the silicon substrate, and the middle region of the first N-type thin layer forms the high Resistivity part.

Step 4, depositing and forming a second P-type silicon epitaxial layer on the front side of the silicon substrate, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and completely fills the trench ; removing both silicon and silicon oxide from the top surface of the trench.

In the current flow region, the P-type thin layer is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer and the N-type thin layer in the current flow region The thin layers are arranged alternately.

At least the charge balance of the second N-type thin layer and its adjacent P-type thin layer, including the unbalance of the N-type thin layer and its adjacent P-type thin layer of the high-resistivity portion , when a reverse bias voltage is connected between the N-type thin layer and the P-type thin layer, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not blocked by the P-type thin layer Layers are fully depleted laterally.

Step 5, forming a P well on the top of each of the P-type thin layers, and each of the P wells also extends to a part of the top of the N-type thin layer; the top region of the N-type thin layer between each of the P wells It is an N-type conduction region.

Step 6, sequentially depositing a gate dielectric layer and a polysilicon gate, and sequentially etching the polysilicon gate and the gate dielectric layer by using a photolithography etching process, the etched gate dielectric layer and the polysilicon gate Composing the gate structure of the super junction planar gate MOSFET device; the polysilicon gate covers the N-type thin layer and part of the P well from the top, and the P well covered by the polysilicon gate is used to form lateral channel.

Step 7, performing N+ ion implantation to form a source region; the source region is formed on the top of the P well and self-aligned with the polysilicon gate.

Step 8, forming an interlayer film on the front side of the silicon substrate on which the source region is formed; forming a contact hole by using a photolithography process, the contact hole passing through the interlayer film and connecting with the source region or The polysilicon gate contact; performing P+ ion implantation to form a P well lead-out region, the P well lead-out region is located at the bottom of the contact hole in contact with the source region, and the P well lead-out region is in contact with the P well .

Step 9, depositing front metal and performing photolithography on the front metal to form source and gate respectively.

Step 10, thinning the silicon substrate from the back side.

Step 11, perform back ion implantation to form an N-type region, the N-type region is located at the bottom of the N-type thin layer and the P-type thin layer; perform back ion implantation to form a P-type region on the back of the N-type region .

Step twelve, activating ions in the N-type region and the P-type region.

Step thirteen, performing back metallization to form a drain.

The groove of the P/N thin layer of the super junction device of the present invention is directly formed on the silicon substrate, and no epitaxial layer needs to be formed on the silicon substrate, so the present invention can minimize the manufacturing cost of the device. The super junction device of the present invention adopts a thinner silicon substrate and forms a very thin N-type region at the bottom of the P/N thin layer, which can reduce the specific on-resistance of the device and reduce the thermal resistance of the device, thereby improving reliability. The N-type thin layer of the P/N thin layer of the superjunction device of the present invention is composed of two parts, the silicon substrate thin layer part, that is, the first N-type thin layer, and the epitaxial filling part, that is, the second N-type thin layer, wherein the silicon substrate thin layer The layer part has a higher resistivity, the epitaxial filling part has a lower resistivity, and the thin layer part of the silicon substrate can not be completely depleted laterally by the P-type thin layer when the reverse bias is applied, so that when the reverse bias voltage increases The thin layer of the silicon substrate can be partially depleted vertically through the P well located on the top of the N-type thin layer, and the depth of the vertical depletion region increases with the increase of the reverse bias voltage, which can make the hard reverse recovery characteristics of the device change. Soft, which can improve the reverse recovery characteristics of the device and reduce the recovery current impact. Therefore, the present invention can better optimize the low specific on-resistance and the SOFTNESS of the device in the turn-off process, and can realize the best balance between the specific on-resistance and the resistance to current impact.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Figure 1 is a top view of an existing super junction device;

Fig. 2 is the second top view of the existing super junction device;

3 is a top view of a current flow region of a super junction device according to an embodiment of the present invention;

4 is a cross-sectional view of a super junction device according to an embodiment of the present invention;

5-9 are cross-sectional views of devices in each step of a manufacturing method of a super junction device according to an embodiment of the present invention;

10A-10B are vertical distribution diagrams of the impurity concentration of the N-type region of the super junction device according to Embodiment 1 of the present invention;

Fig. 11 is a cross-sectional view of a super junction device according to Embodiment 2 of the present invention;

12A-12C are longitudinal distribution diagrams of the impurity concentration of the N-type region of the super junction device according to the second embodiment of the present invention;

13 is a cross-sectional view of a super junction device according to Embodiment 3 of the present invention;

14 is a vertical distribution diagram of the impurity concentration from the bottom of the P/N thin layer to the back of the silicon substrate of the super junction device according to the third embodiment of the present invention;

15 is a top view of the current flow region of the super junction device according to Embodiment 4 of the present invention;

Fig. 16 is a cross-sectional view of a super junction device according to Embodiment 4 of the present invention;

FIG. 17 is a cross-sectional view of a fifth superjunction device according to Embodiment 5 of the present invention;

Fig. 18 is a top view of the current flow region of the sixth super junction device of the present invention;

Fig. 19 is a cross-sectional view of a super junction device according to Embodiment 7 of the present invention.

detailed description

As shown in FIG. 1 , it is a first top view of an existing super junction device. In the top view, the embodiment of the present invention can be divided into zone 1, zone 2 and zone 3. Region 1 is the middle region of the super junction device, which is the current flow region, and the current flow region includes alternately arranged P-type regions 25 and N-type regions, and the P-type regions 25 are also P-type regions formed in the current flow region. The N-type thin layer, the N-type region is also the N-type thin layer formed in the current flow region; in the current flow region, the current will pass through the N-type region from the source to the drain through the channel, and the The P-type region 25 is in the reverse cut-off state and forms a depletion region together with the N-type region to withstand voltage. Zones 2 and 3 are the terminal protection structure regions of the super junction device. The terminal protection structure does not provide current when the device is turned on, and is used to bear the power from the peripheral unit of zone 1, that is, the peripheral P-type region 25, in the reverse bias state. The voltage from the surface to the substrate on the outermost surface of the device is the lateral voltage and the voltage from the surface of the peripheral cell in region 1 to the substrate is the vertical voltage. There is at least one P-type ring 24 in the 2nd area, and it is a P-type ring 24 in FIG. The field plate dielectric film in zone 2 also has a polycrystalline field plate and a metal field plate for slowing down the sharp change of the surface electric field, and a P-type column 23; the metal field plate may not be provided in zone 2. Region 3 is a voltage bearing region formed alternately by P-type pillars 23 and N-type pillars composed of N-type silicon epitaxial layers, with a dielectric film on it, and the P-type pillars 23 are also formed in the terminal protection structure. The P-type thin layer and the N-type column are also the N-type thin layer formed in the terminal protection structure; there is a metal field plate in the 3rd area, and the metal field plate may not be set in the 3rd area; There may or may not be a P-type ring 24. When there is a P-type ring 24, the P-type ring here is not connected to the P-type back gate connection of the current flow area (suspended); there is a groove at the outermost end of the 3rd area The channel stop ring 21, the channel stop ring 21 is composed of N+ implanted region or N+ implanted region plus a dielectric formed thereon or a dielectric plus metal; there may be additional The small P-type pillars 22 are used to achieve better charge balance. It can be seen from FIG. 1 that the unit structure of the current flow region, that is, the P-type region 25 and the N-type region are strip structures; the terminal protection structure surrounds the periphery of the current flow region and the P The type ring 24 , the P-type pillar 23 and the channel stop ring 21 all have a square ring structure, or a square ring structure with rounded corners.

As shown in FIG. 2, it is a top view 2 of an existing super junction device. The difference from the structure shown in FIG. It is a quadrangular structure, that is, the quadrangular P-type regions 25 and N-type regions are neatly arranged in the two-dimensional direction to form the unit array of the current flow region. The P-type region 25 and the N-type region can also be hexagonal, octagonal and other shapes, and the arrangement of the P-type region 25 and the N-type region can also be misaligned in the X and Y directions; Just ensure that the entire arrangement is repeated according to certain rules.

The additional small P-type pillars 22 at the four corners in Figs. The distance between the P-shaped pillars 23 is also a, so the small P-shaped pillars 22 can adopt square P-shaped holes with a side length of 0.3-0.5a.

In existing super junction MOSFET devices, MOSFET device units are formed above the N-type thin layer in the current flow region, and the N-type thin layer, P-type thin layer and MOSFET device unit in the current flow region are completely repeated, for example, for a breakdown Take a device with a voltage of 600V, that is, BVds-600V, as an example: the N+ silicon substrate of the device is uniform, with a resistivity of 0.001-0.003 ohm·cm, and a deposition thickness of 45 microns on the N+ substrate, with a resistivity of 1 ohm·cm A uniformly doped N-type epitaxial silicon layer of cm to 5 ohm cm or an N-type epitaxial silicon layer whose impurity concentration varies along the vertical direction; after that, a trench is formed, and a P-type epitaxial silicon layer is filled in the trench, and the P-type epitaxial silicon layer It can be doped uniformly along the vertical direction, or it can be doped variablely along the vertical direction, so that after the trench is etched, the N-type thin layer and the epitaxially filled P-type thin layer constitute the alternating P-N thin layer of the super junction device. The layer will be P-type thin layer and N-type thin layer; in the current flow area, except for the area close to the device terminal, which may be different due to terminal design and process, all device units are consistent. In the lateral direction, P-N thin The layer structure is completely repeated.

As shown in FIG. 3 , it is a top view of the current flow region of a super junction device according to an embodiment of the present invention; as shown in FIG. 4 , it is a cross-sectional view of a super junction device according to an embodiment of the present invention. Embodiment 1 of the present invention The super junction device is formed on the N-type silicon substrate 1, the middle region of the super junction device is the current flow region, and the terminal protection structure surrounds the outer periphery of the current flow region; the current flow region includes multiple Alternately arranged N-type thin layers and P-type thin layers 4 . It can be seen from Figure 3 that the P-type thin layer 4 corresponds to the thin layer between B1B2, B3B4, B5B6, B7B8, etc., and the N-type thin layer corresponds to the thin layer between B0B1, B2B3, B4B5, B6B7, B8B9, etc. It can be seen that the P-type thin layers 4 and the N-type thin layers are strip-shaped and arranged alternately.

The silicon substrate 1 is an N-type doped substrate with a relatively high resistivity.

A plurality of grooves are formed on the silicon substrate 1 .

Each of the N-type thin layers is composed of a first N-type thin layer 3 and a second N-type thin layer 3a; the first N-type thin layer 3 is composed of a silicon substrate thin layer between the grooves , the second N-type thin layer 3a is composed of first N-type silicon epitaxial layers filled in the groove and located on both sides of the first N-type thin layer 3, and the P-type thin layer 4 is filled with The second P-type silicon epitaxial layer in the trench, each of the P-type thin layers 4 is in contact with the second N-type thin layer 3a on both sides and completely fills the corresponding trench .

The resistivity of the second N-type thin layer 3a is lower than the resistivity of the silicon substrate 1, and the N-type doping of the first N-type thin layer 3 is formed by the N-type doping of the silicon substrate 1 itself. Impurities plus N-type impurities diffused in from the second N-type thin layer 3a.

Part or all of the first N-type thin layer 3 of the N-type thin layer includes a high-resistivity portion, and the N-type thin layer including the high-resistivity portion has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer 3 by the N-type thin layer 3a does not spread over the entire width of the first N-type thin layer 3, and the resistivity of the silicon substrate 1 is as described above. The resistivity of the second N-type thin layer 3a is more than 10 times, the resistivity of the middle region of the first N-type thin layer 3 is equal to the resistivity of the silicon substrate 1, and the resistivity of the first N-type thin layer 3a is The middle region of layer 3 constitutes said high-resistivity portion.

Preferably, the widths of the N-type thin layers in the current flow region are all the same, and the first N-type thin layer 3 of all the N-type thin layers includes the high-resistivity portion. Alternatively, the N-type thin layer in the current flow region includes more than two kinds of widths, the N-type thin layer with the largest width includes the high-resistivity portion, and the N-type thin layer with a width smaller than the largest width The N-type thin layer includes or does not include the high-resistivity portion; the N-type thin layer that does not include the high-resistivity portion has a feature: Diffusion from the second N-type thin layer 3a into the first N-type thin layer N-type impurities in the thin layer 3 spread throughout the width of the first N-type thin layer 3, and the resistivity of the middle region of the first N-type thin layer 3 is lower than the resistance of the silicon substrate 1 Rate.

Charge balance of at least the second N-type thin layer 3a and its adjacent P-type thin layer 4, including the N-type thin layer of the high-resistivity portion and its adjacent P-type thin layer 4 When the reverse bias voltage is connected between the N-type thin layer and the P-type thin layer 4, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not The P-type thin layer 4 is completely depleted laterally. For the N-type thin layer that does not include the high-resistivity portion, the part of the N-type thin layer and its adjacent P-type thin layer 4 can be balanced, and the N-type thin layer and the P-type thin layer When the reverse bias voltage is connected between the thin layers 4 , the N-type thin layer excluding the high-resistivity part can be completely depleted laterally by the P-type thin layer 4 .

An N-type region 2 composed of a rear ion implantation region is formed at the bottom of the N-type thin layer and the P-type thin layer 4 .

When the device in Embodiment 1 of the present invention is turned on, the N-type thin layer, that is, the first N-type thin layer 3 and the second N-type thin layer 3a provide the current flow region of the device; when the device is turned off At this time, part of the N-type impurities in the N-type thin layer are depleted by the impurities in the P-type thin layer 4; or at least part of the N-type impurities in the second N-type thin layer 3a are all depleted by the impurities The impurities in the P-type thin layer 4 are depleted, and the sum of the N-type partial impurities in the second N-type thin layer 3a on both sides of the first N-type thin layer 3 is equal to that of the P-type thin layer 4 The absolute value of the difference of the sum of impurities in can not be greater than 20% of the sum of any one of them.

In Embodiment 1 of the present invention, an N-type layer with a thickness of t1 is formed at the bottom of the groove, that is, an N-type layer with a thickness of t1 is formed under the P-type thin layer 4, and the N-type layer may not be depleted by the P-type impurities of the P-type thin layer 4 when the device is turned off, which can improve the turn-off characteristics of the device.

Embodiment 1 of the present invention The super junction device is a super junction trench gate MOSFET device, a MOSFET device unit is formed on the top of each of the N-type thin layers, and a P well is formed on the top of each of the N-type thin layers 7, a gate dielectric layer 5 is formed on the bottom surface and side surfaces of the gate trench, and a polysilicon gate 6 filling the gate trench is formed on the surface of the gate dielectric layer 5, and the gate dielectric layer 5 is gate oxide layer. The side of the P well 7 covered by the polysilicon gate 6 is used to form a vertical channel. A source region 8 composed of an N+ region is formed on the top of the P well 7 on both sides of the gate trench on the top of the N-type thin layer.

An interlayer film 10 is formed on the front side of the silicon substrate 1; a contact hole 11 passes through the interlayer film 10 and is in contact with the source region 8 or the polysilicon gate 6; A P well lead-out region 9 composed of a P+ region is formed at the bottom of the contact hole 11 , and the P well lead-out region 9 is in contact with the P well 7 .

A front metal 12 is formed on the front of the silicon substrate 1 , and the front metal 12 respectively leads to a source and a gate. A back metal 13 is formed on the back of the silicon substrate 1 , and the back metal 13 respectively leads to a drain.

A further improvement of Embodiment 1 of the present invention includes: the depth of the grooves is 40 micrometers to 50 micrometers, the width of the grooves is 6 micrometers, and the distance between adjacent grooves is 1 micrometer.

The resistivity of the silicon substrate 1 is 20 ohm·cm to 40 ohm·cm. The resistivity of the second N-type thin layer 3a is 0.97 ohm·cm, and the impurity concentration is 5e15cm ^-3 , the two second N-type thin layers 3a located on both sides of each of the first N-type thin layers 3 The widths were all 1.5 µm. The resistivity of the P-type thin layer 4 is 2.74 ohm·cm, and the impurity concentration is 5e15cm ^-3 ; the width of the P-type thin layer 4 is 3 microns, which is composed of two second P layers with a width of 1.5 microns. A silicon epitaxial layer is formed after bonding in the middle of the trench.

The impurities in the N-type region 2 need to be activated, such as laser annealing, furnace tube annealing, or a combination of laser annealing and furnace tube annealing; the thickness of the N-type region 2 is 0.5 microns to 5 microns, and the thickness is controlled by The thinned thickness of the back side of the silicon substrate 1 is obtained. In the double arrow line EDC in FIG. layer, because the thickness of the N-type region 2 is small, the doping of the N-type region 2 is achieved by one-time ion implantation such as phosphorus implantation, the implantation energy is 50-500KEV, and the dose is higher than 5E14CM ^-2 , as shown in Figure 10a As shown, it is the first vertical distribution diagram of the impurity concentration of the N-type region 2 of the super junction device according to the embodiment of the present invention. At the upper boundary; as shown in Figure 10b, it is the second longitudinal distribution diagram of the impurity concentration of the N-type region 2 of the super junction device according to the embodiment of the present invention, and the doping impurities of the N-type region 2 have not diffused to the boundary D That is, at the upper boundary of the N-type region 2, that is, under the trench, there is also a region with the same resistivity as the silicon substrate 1, and the first vertical distribution as shown in FIG. 10a can obtain a lower of on-resistance.

As shown in Figures 5 to 9, it is a cross-sectional view of the device in each step of the manufacturing method of a super junction device in the embodiment of the present invention; the super junction device in the manufacturing method of the super junction device in the embodiment of the present invention is a super junction trench A trench gate MOSFET device, comprising the steps of:

Step 1, as shown in FIG. 5 , deposit a first silicon dioxide layer 31 , a second silicon nitride layer 32 and a third silicon dioxide layer 33 on the surface of an N-type silicon substrate 1 with higher resistivity in sequence; A photolithographic etching process sequentially forms a trench pattern mask on the third silicon dioxide layer 33 , the second silicon nitride layer 32 and the first silicon dioxide layer 31 . Preferably, the silicon substrate 1 has a resistivity of 20 ohm·cm to 40 ohm·cm, and a thickness of the silicon substrate 1 of 8 inches is 700 microns to 725 microns.

Step 2. As shown in FIG. 6, the silicon substrate 1 is etched to form a plurality of grooves by using the groove pattern mask as a mask; the middle region of the super junction device is the current flow region, and the terminal A protective structure surrounds the periphery of the current flow region; in the current flow region, the silicon substrate 1 between the trenches is in a thin layer structure and is made of silicon between the trenches. The substrate thin layer constitutes the first N-type thin layer 3; the third silicon dioxide layer 33 and the second silicon nitride layer 32 of the trench pattern mask are removed in sequence, and the first silicon dioxide layer The silicon layer 31 remains. Preferably, the depth of the grooves is 40 microns to 50 microns, the width of the grooves is 6 microns, and the distance between adjacent grooves is 1 micron.

Step 3, as shown in FIG. 7 , deposit and form a first N-type silicon epitaxial layer on the front side of the silicon substrate 1, and the first N-type silicon epitaxial layer is formed on the bottom and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the first N-type thin layer 3 forms a second N-type thin layer 3a, each of the first N-type thin layers 3 plus the second N-type epitaxial layers on both sides thereof N-type thin layers 3a constitute corresponding N-type thin layers.

The resistivity of the second N-type thin layer 3a is lower than the resistivity of the silicon substrate 1, and the N-type doping of the first N-type thin layer 3 is formed by the N-type doping of the silicon substrate 1 itself. Impurities plus N-type impurities diffused in from the second N-type thin layer 3a.

Part or all of the first N-type thin layer 3 of the N-type thin layer includes a high-resistivity portion, and the N-type thin layer including the high-resistivity portion has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer 3 by the N-type thin layer 3a does not spread over the entire width of the first N-type thin layer 3, and the resistivity of the silicon substrate 1 is as described above. The resistivity of the second N-type thin layer 3a is more than 10 times, the resistivity of the middle region of the first N-type thin layer 3 is equal to the resistivity of the silicon substrate 1, and the resistivity of the first N-type thin layer 3a is The middle region of layer 3 constitutes said high-resistivity portion.

Preferably, the widths of the N-type thin layers in the current flow region are all the same, and the first N-type thin layer 3 of all the N-type thin layers includes the high-resistivity portion. Alternatively, the N-type thin layer in the current flow region includes more than two kinds of widths, the N-type thin layer with the largest width includes the high-resistivity portion, and the N-type thin layer with a width smaller than the largest width The N-type thin layer includes or does not include the high-resistivity portion; the N-type thin layer that does not include the high-resistivity portion has a feature: Diffusion from the second N-type thin layer 3a into the first N-type thin layer N-type impurities in the thin layer 3 spread throughout the width of the first N-type thin layer 3, and the resistivity of the middle region of the first N-type thin layer 3 is lower than the resistance of the silicon substrate 1 Rate.

Preferably, the resistivity of the second N-type thin layer 3a is 0.97 ohm·cm, the impurity concentration is 5e15cm ^-3 , and the two second N-type thin layers located on both sides of each first N-type thin layer 3 The widths of the molded thin layers 3a are each 1.5 micrometers.

Step 4, as shown in FIG. 7 , deposit and form a second P-type silicon epitaxial layer on the front side of the silicon substrate 1, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and The trench is completely filled; both silicon and silicon oxide are removed from the top surface of the trench.

In the current flow region, the P-type thin layer 4 is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer 4 and the The N-type thin layers are arranged alternately.

Charge balance of at least the second N-type thin layer 3a and its adjacent P-type thin layer 4, including the N-type thin layer of the high-resistivity portion and its adjacent P-type thin layer 4 When the reverse bias voltage is connected between the N-type thin layer and the P-type thin layer 4, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not The P-type thin layer 4 is completely depleted laterally. For the N-type thin layer that does not include the high-resistivity portion, the part of the N-type thin layer and its adjacent P-type thin layer 4 can be balanced, and the N-type thin layer and the P-type thin layer When the reverse bias voltage is connected between the thin layers 4 , the N-type thin layer excluding the high-resistivity part can be completely depleted laterally by the P-type thin layer 4 .

When the device in Embodiment 1 of the present invention is turned on, the N-type thin layer, that is, the first N-type thin layer 3 and the second N-type thin layer 3a provide the current flow region of the device; when the device is turned off At this time, part of the N-type impurities in the N-type thin layer are depleted by the impurities in the P-type thin layer 4; or at least part of the N-type impurities in the second N-type thin layer 3a are all depleted by the impurities The impurities in the P-type thin layer 4 are depleted, and the sum of the N-type partial impurities in the second N-type thin layer 3a on both sides of the first N-type thin layer 3 is equal to that of the P-type thin layer 4 The absolute value of the difference of the sum of impurities in can not be greater than 20% of the sum of any one of them.

Preferably, the resistivity of the P-type thin layer 4 is 2.74 ohm·cm, and the impurity concentration is 5e15cm ^-3 ; the width of the P-type thin layer 4 is 3 microns, which is composed of two 1.5 micron The second P-type silicon epitaxial layer is formed after bonding in the middle of the trench.

Step 5, as shown in FIG. 8 , a gate trench is formed on the top of the N-type thin layer in the current flow region by photolithography.

Step 6, as shown in FIG. 8 , deposit a gate dielectric layer 5 and a polysilicon gate 6 in sequence. Preferably, the gate dielectric layer 5 is a gate oxide layer. The gate dielectric layer 5 covers the bottom surface, sides and outside of the gate trench, the polysilicon gate 6 is formed on the surface of the gate dielectric layer 5 and completely fills the gate trench, and the gate trench is removed The gate dielectric layer 5 and the polysilicon gate 6 outside the groove, the gate dielectric layer 5 and the polysilicon gate 6 filled in the gate trench constitute the gate of the super junction trench gate MOSFET device pole structure.

Step 7, as shown in Figure 8, form a P well 7 on the top of the N-type thin layer and the P-type thin layer 4; the depth of the gate trench is greater than the depth of the P well 7, and the polysilicon The gate 6 covers the P well 7 from the side, and the side of the P well 7 covered by the polysilicon gate 6 is used to form a vertical channel.

Step 8, as shown in FIG. 8 , perform N+ ion implantation to form a source region 8; the source region 8 is formed on the top of the P well 7 on both sides of the gate trench at the top of the N-type thin layer .

Step 9. As shown in FIG. 8 , an interlayer film 10 is formed on the front surface of the silicon substrate 1 on which the source region 8 is formed; a contact hole 11 is formed by photolithography, and the contact hole 11 passes through the The interlayer film 10 is in contact with the source region 8 or the polysilicon gate 6; P+ ion implantation is performed to form a P-well lead-out region 9, and the P-well lead-out region 9 is located on the source region 8 in contact with the The bottom of the contact hole 11 , the P well lead-out region 9 is in contact with the P well 7 .

Step ten, as shown in FIG. 9 , depositing the front metal 12 and performing photolithography on the front metal 12 to form the source and the gate respectively;

Step eleven, as shown in FIG. 4 , thinning the silicon substrate 1 from the back side.

Step 12, as shown in FIG. 4 , perform back ion implantation to form an N-type region 2 , and the N-type region 2 is located at the bottom of the N-type thin layer and the P-type thin layer 4 . Preferably, the thickness of the N-type region 2 is 0.5 microns to 5 microns, which is obtained by controlling the thickness of the thinned back side of the silicon substrate 1. In the double arrow line EDC in FIG. 4, the boundary E , D are respectively the back and upper boundaries of the N-type region 2, and the boundary C is in the N-type thin layer. Since the thickness of the N-type region 2 is small, the doping of the N-type region 2 is achieved by one-time ion implantation such as phosphorus implantation, the implantation energy is 50KEV-500KEV, and the dose is higher than 5E14CM ^-2 .

Step thirteen, as shown in FIG. 4 , activating the ions in the N-type region 2 . Preferably, the impurity in the N-type region 2 is activated by one laser annealing, one furnace tube annealing, or a combination of one laser annealing and one furnace tube annealing. After activation, the longitudinal distribution of the impurity concentration of the N-type region 2 is shown in Fig. 10a and Fig. 10b.

Step fourteen, as shown in FIG. 4 , perform back metallization to form the drain 13 .

In the method of Embodiment 1 of the present invention, the process of forming the P-well 7 in step 7 can be advanced before step 1, that is, before the trench formation process. This can reduce the impact of the thermal process required by the push-well process during the formation of the P well 7 on the impurity diffusion in the P-N thin layer, and improve the specific on-resistance of the device.

As shown in Figure 11, it is a cross-sectional view of the super junction device of the second embodiment of the present invention; the difference between the super junction device of the second embodiment of the present invention and the super junction device of the first embodiment of the present invention is that the N-type region 2 is formed by the first A layer of N-type region 21 and a second layer of N-type region 22, the first layer of N-type region 21 is close to the bottom of the N-type thin layer and the P-type thin layer 4, and the second layer of N-type region 22 is close to the back of the silicon substrate 1, the doping concentration of the N-type region 22 of the second layer is greater than the doping concentration of the N-type region 21 of the first layer, and the doping concentration of the N-type region 22 of the second layer is The impurity concentration satisfies the condition of forming an ohmic contact with the backside metal 13 formed on the silicon substrate 1, and the implanted ions of the first N-type region 21 are respectively wider and serve as a buffer layer of the super junction device. The thickness of the N-type region 2 of the second embodiment of the present invention is thicker than that of the first embodiment of the present invention. Preferably, the thickness of the N-type region 2 is 3 microns to 50 microns, and the first layer of N-type The thickness of the region 21 is 3 microns to 50 microns, and the thickness of the N-type region 22 of the second layer is 0.5 microns to 3 microns.

Preferably, the vertical distribution of impurity concentration in the N-type region 2 includes three situations:

12A is a vertical distribution diagram of the first type of impurity concentration in the N-type region 2 of the super junction device according to the second embodiment of the present invention; in the case of the vertical distribution of the first type of impurity concentration, the thickness of the N-type region 2 is 3 Micron to 5 micron, the first N-type region 21 and the second-layer N-type region 22 can be respectively obtained by two backside ion implantations. The impurity for the first back ion implantation is phosphorus, the implantation energy is 1000KEV-4000KEV, and the dose is higher than 5E13CM ^-2 ; the implantation impurity for the second back ion implantation is phosphorus, arsenic, etc., the energy is less than 80KEV, and the dose is greater than 1e15cm ^-2 , the N-type impurity concentration distribution between the boundaries D and E obtained in this way is shown in Figure 12A, the concentration closest to the back surface is very high, and the contact resistance between the N+ region and the metal is very low; the subsequent activation can be performed at a low temperature. Anneal in a furnace tube at 500°C, or use laser annealing.

Fig. 12B is a vertical distribution diagram of the second impurity concentration of the N-type region 2 of the super junction device according to the second embodiment of the present invention; in the case of the vertical distribution of the second impurity concentration, the thickness of the N-type region 2 is 3 Micron to 50 micron, the first N-type region 21 and the second-layer N-type region 22 can be respectively obtained by two backside ion implantations. The implantation impurity of the first back ion implantation is H+, the implantation energy is 50KEV～4000KEV, and the dose is higher than 5E13CM ^-2 ; the implantation impurity of the second back ion implantation is phosphorus, arsenic, etc., the energy is less than 80KEV, and the dose is greater than 1e15cm ^-2 , Subsequent activation can be annealed in a furnace at a temperature below 500°C. In the case of the second vertical distribution of impurity concentration, the implantation dose of the first backside ion implantation is relatively high, and the impurity concentration of the N-type region 2 at the interface D after activation is greater than that of the N-type thin layer or the P-type thin layer. The impurity concentration of layer 4, and thus obtained N-type impurity concentration distribution between the boundaries D and E are shown in FIG. 12B.

Fig. 12C is a vertical distribution diagram of the third impurity concentration in the N-type region 2 of the super junction device according to the second embodiment of the present invention; the vertical distribution of the third impurity concentration is the same as that shown in Fig. 12B The difference in the case of vertical distribution is that in the case of the third vertical distribution of impurity concentration, the implantation dose of the first backside ion implantation is relatively low, and the impurity concentration of the N-type region 2 at the interface D after activation is lower than that of the N-type region 2. The impurity concentration of the thin layer or the P-type thin layer 4, and the N-type impurity concentration distribution between the boundaries D and E thus obtained are shown in FIG. 12C.

The difference between the manufacturing method of the super junction device in the second embodiment of the present invention and the manufacturing method of the super junction device in the first embodiment of the present invention is that in the process of thinning the silicon substrate 1 from the back side in step eleven, it is required to ensure The thickness of the N-type region 2 formed subsequently is 3 micrometers to 50 micrometers. In the process of forming the N-type region 2 by performing backside ion implantation in step 12, the second method of the present invention includes two backside ion implantations to form the first N-type region 21 and the second layer N-type region 2 respectively. District 22. Preferably, the impurity concentrations of the first N-type region 21 and the second-layer N-type region 22 can have three vertical distribution situations:

The vertical distribution of the first type of impurity concentration corresponds to that shown in FIG. 12A. The thickness of the N-type region 2 is 3 microns to 5 microns. The implanted impurity for the first backside ion implantation is phosphorus, and the implantation energy is 1000KEV to 4000KEV. higher than 5E13cm ^-2 ; the impurity implanted in the second backside ion implantation is phosphorus, arsenic, etc., the energy is less than 80KEV, and the dose is greater than 1e15cm ^-2 ; at this time, the ions in the N-type region 2 in the subsequent step thirteen Activation adopts furnace tube annealing at a temperature lower than 500°C, or laser annealing.

The vertical distribution of the second impurity concentration corresponds to that shown in FIG. 12B. In the case of the second vertical distribution of the impurity concentration, the thickness of the N-type region 2 is 3 micrometers to 50 micrometers, and the first backside ion implantation The implanted impurity is H+, the implantation energy is 50KEV～4000KEV, and the dose is higher than 5E13CM ^-2 ; the implanted impurities of the second backside ion implantation are phosphorus, arsenic, etc., the energy is less than 80KEV, and the dose is greater than 1e15cm ^-2 . The activation in thirteen can be annealed in a furnace with a temperature lower than 500°C. In the case of the second vertical distribution of impurity concentration, the implantation dose of the first backside ion implantation is relatively high, and the impurity concentration of the N-type region 2 at the interface D after activation is greater than that of the N-type thin layer or the P-type thin layer. The impurity concentration of layer 4.

The vertical distribution of the second impurity concentration corresponds to that shown in FIG. 12C. The difference between the third vertical distribution of the impurity concentration and the third vertical distribution of the impurity concentration shown in FIG. 12B is that the third In the case of the vertical distribution of impurity concentration, the implantation dose of the first backside ion implantation is relatively low, and the impurity concentration of the N-type region 2 at the interface D after activation is lower than that of the N-type thin layer or the P-type thin layer 4 concentration.

As shown in Figure 13, it is a cross-sectional view of the super junction device of the third embodiment of the present invention; the difference between the super junction device of the third embodiment of the present invention and the super junction device of the first embodiment of the present invention is: the super junction device of the third embodiment of the present invention For a super junction trench gate IGBT device, a P-type region 14 is also formed at the bottom of the N-type region 2, and the P-type region 14 is composed of a P+ region formed by backside ion implantation. The N-type region 2 becomes a field stop layer, and the P-type region 14 becomes a collector region of the device; the whole forms an IGBT device. As shown in FIG. 14 , it is a longitudinal distribution diagram of the impurity concentration from the bottom of the P/N thin layer to the back of the silicon substrate 1 of the super junction device of the third embodiment of the present invention; wherein the P+ region near the back constitutes the P-type region 4 .

The difference between the manufacturing method of the super junction device of the third embodiment of the present invention and the manufacturing method of the super junction device of the first embodiment of the present invention is that in step 12, after the back ion implantation is performed to form the N-type region 2, the back ion implantation is also included. The P-type region 14 is formed. The vertical distribution of the doping concentration of the formed P-type region 14 is shown in FIG. 14 .

As shown in FIG. 15 , it is a top view of the current flow region of the super junction device of the fourth embodiment of the present invention; as shown in FIG. 16 , it is a cross-sectional view of the super junction device of the fourth embodiment of the present invention. The difference between the super junction device in Embodiment 4 of the present invention and the super junction device in Embodiment 1 of the present invention is that the device in Embodiment 4 of the present invention includes at least one N-type thin layer 3W with a wider width. type thin layer, the first N-type thin layer 3W in FIG. Due to the wide width of the first N-type thin layer 3W, the N-type impurities diffused from the second N-type thin layer 3a into the first N-type thin layer 3W do not spread throughout the entire first N-type thin layer 3a. Type thin layer 3W within the width range, so there is always a high-resistivity part in the middle of the first N-type thin layer 3W, when the reverse bias voltage is connected between the N-type thin layer and the P-type thin layer 4 The high-resistivity part is not completely laterally depleted by the P-type thin layer 4; the part not laterally depleted by the P-type thin layer 4 will form a P-N junction with the P-well 7, with the device With the increase of the source-drain voltage, that is, Vds, the depletion region in the first N-type thin layer 3W gradually expands, which is different from the lower voltage in the second N-type thin layer 3a and the P-type thin layer 4 If it is completely depleted below 50V, due to this characteristic of the first N-type thin layer 3W, the reverse recovery characteristic and switching characteristic of the device are improved. Preferably, the width of the first N-type thin layer 3W is 50 microns.

The difference between the method for manufacturing a super junction device in Embodiment 4 of the present invention and the method for manufacturing a super junction device in Embodiment 1 of the present invention is that when trenches are formed in step 2, the distance between the trenches in some regions is set to the specified Describe the required width of the first N-type thin layer 3W. Preferably, the width of the first N-type thin layer 3W is 50 microns.

As shown in Figure 17, it is a cross-sectional view of the super junction device of the fifth embodiment of the present invention. The difference between the super junction device of the fifth embodiment of the present invention and the device of the fourth embodiment of the present invention is: the N The N-type region 2 is composed of a first N-type region 21 and a second N-type region 22. The structural features of the first N-type region 21 and the second N-type region 22 of the fifth device of the present invention are the same as those of the second N-type device of the present invention. same.

The difference between the manufacturing method of the super junction device in the fifth embodiment of the present invention and the manufacturing method of the super junction device in the second embodiment of the present invention is that when the trenches are formed in step 2, the distance between the trenches in some regions is set to the specified Describe the required width of the first N-type thin layer 3W. Preferably, the width of the first N-type thin layer 3W is 50 microns.

The difference between the sixth super junction device of the present invention and the fourth embodiment of the present invention is that the super junction device of the sixth embodiment of the present invention is a super junction trench gate IGBT device, and the N-type region of the device of the sixth embodiment of the present invention The P-type region 14 is also formed on the back of the device 2, and the structural features of the P-type region 14 are the same as those of the third device of the present invention shown in FIG. 13 .

The difference between the manufacturing method of the super-junction device in Embodiment 6 of the present invention and the manufacturing method of the super-junction device in Embodiment 2 of the present invention is that when trenches are formed in step 2, the distance between the trenches in some regions is set to the specified Describe the required width of the first N-type thin layer 3W. Preferably, the width of the first N-type thin layer 3W is 50 microns.

As shown in Figure 18, it is a top view of the current flow region of the super junction device of the seventh embodiment of the present invention; the difference between the super junction device of the seventh embodiment of the present invention and the device of the fourth embodiment of the present invention is: The first N-type thin layer 3W with a wider width only exists in a part of the region, and does not run through the entire current flow region of a device, and the first N-type thin layer 3W is not adjacent to the terminal region of the device, In order not to cause differences in device consistency due to differences in adjacent terminal regions, or increase the complexity of terminal design. At the same time, the first N-type thin layer 3W is not adjacent to the device gate electrode, that is, the metal pad (PAD) of the front metal 12 connected to the polysilicon gate 6, which can improve the consistency of the device and reduce the complexity of device design.

The above-mentioned super junction devices in Embodiments 1 to 7 of the present invention are devices with a trench gate structure, and the present invention is also applicable to devices with a planar gate structure, and only the trench gate is converted into a planar gate.

As shown in FIG. 19 , it is a cross-sectional view of the eighth super junction device of the present invention. The eighth super-junction device of the present invention is a super-junction planar gate MOSFET device. The difference between the eighth device of the present invention and the device of the first embodiment of the present invention is that the gate dielectric layer 5 and the polysilicon gate 6 are planar structures , the polysilicon gate 6 covers part of the P well 7 and extends above the N-type thin layer, the source region 8 is self-aligned with one side of the polysilicon gate 6 and is covered by the polysilicon gate 6 The surface of the P well 7 is used to form a channel connecting the source region 8 and the N-type thin layer.

The manufacturing method of the eighth super junction device of the present invention includes the following steps:

Step 1, as shown in FIG. 5 , deposit a first silicon dioxide layer 31 , a second silicon nitride layer 32 and a third silicon dioxide layer 33 on the surface of an N-type silicon substrate 1 with higher resistivity in sequence; A photolithographic etching process sequentially forms a trench pattern mask on the third silicon dioxide layer 33 , the second silicon nitride layer 32 and the first silicon dioxide layer 31 . Preferably, the silicon substrate 1 has a resistivity of 20 ohm·cm to 40 ohm·cm, and a thickness of the silicon substrate 1 of 8 inches is 700 microns to 725 microns.

Step 2. As shown in FIG. 6, the silicon substrate 1 is etched to form a plurality of grooves by using the groove pattern mask as a mask; the middle region of the super junction device is the current flow region, and the terminal A protective structure surrounds the periphery of the current flow region; in the current flow region, the silicon substrate 1 between the trenches is in a thin layer structure and is made of silicon between the trenches. The substrate thin layer constitutes the first N-type thin layer 3; the third silicon dioxide layer 33 and the second silicon nitride layer 32 of the trench pattern mask are removed in sequence, and the first silicon dioxide layer The silicon layer 31 remains. Preferably, the depth of the grooves is 40 microns to 50 microns, the width of the grooves is 6 microns, and the distance between adjacent grooves is 1 micron.

Step 3, as shown in FIG. 7 , deposit and form a first N-type silicon epitaxial layer on the front side of the silicon substrate 1, and the first N-type silicon epitaxial layer is formed on the bottom and side surfaces of the trench; The first N-type silicon epitaxial layer on both sides of the first N-type thin layer 3 forms a second N-type thin layer 3a, each of the first N-type thin layers 3 plus the second N-type epitaxial layers on both sides thereof N-type thin layers 3a constitute corresponding N-type thin layers.

The resistivity of the second N-type thin layer 3a is lower than the resistivity of the silicon substrate 1, and the N-type doping of the first N-type thin layer 3 is formed by the N-type doping of the silicon substrate 1 itself. Impurities plus N-type impurities diffused in from the second N-type thin layer 3a.

Part or all of the first N-type thin layer 3 of the N-type thin layer includes a high-resistivity portion, and the N-type thin layer including the high-resistivity portion has the following characteristics: from the second N-type thin layer The N-type impurity diffused into the first N-type thin layer 3 by the N-type thin layer 3a does not spread over the entire width of the first N-type thin layer 3, and the resistivity of the silicon substrate 1 is as described above. The resistivity of the second N-type thin layer 3a is more than 10 times, the resistivity of the middle region of the first N-type thin layer 3 is equal to the resistivity of the silicon substrate 1, and the resistivity of the first N-type thin layer 3a is The middle region of layer 3 constitutes said high-resistivity portion.

Preferably, the widths of the N-type thin layers in the current flow region are all the same, and the first N-type thin layer 3 of all the N-type thin layers includes the high-resistivity portion. Alternatively, the N-type thin layer in the current flow region includes more than two kinds of widths, the N-type thin layer with the largest width includes the high-resistivity portion, and the N-type thin layer with a width smaller than the largest width The N-type thin layer includes or does not include the high-resistivity portion; the N-type thin layer that does not include the high-resistivity portion has a feature: Diffusion from the second N-type thin layer 3a into the first N-type thin layer N-type impurities in the thin layer 3 spread throughout the width of the first N-type thin layer 3, and the resistivity of the middle region of the first N-type thin layer 3 is lower than the resistance of the silicon substrate 1 Rate.

Preferably, the resistivity of the second N-type thin layer 3a is 0.97 ohm·cm, the impurity concentration is 5e15cm ^-3 , and the two second N-type thin layers located on both sides of each first N-type thin layer 3 The widths of the molded thin layers 3a are each 1.5 micrometers.

Step 4, as shown in FIG. 7 , deposit and form a second P-type silicon epitaxial layer on the front side of the silicon substrate 1, the second P-type silicon epitaxial layer is in contact with the first N-type silicon epitaxial layer and The trench is completely filled; both silicon and silicon oxide are removed from the top surface of the trench.

In the current flow region, the P-type thin layer 4 is composed of the second P-type silicon epitaxial layer filled in the trench, and the P-type thin layer 4 and the The N-type thin layers are arranged alternately.

Charge balance of at least the second N-type thin layer 3a and its adjacent P-type thin layer 4, including the N-type thin layer of the high-resistivity portion and its adjacent P-type thin layer 4 When the reverse bias voltage is connected between the N-type thin layer and the P-type thin layer 4, the high-resistivity portion of the N-type thin layer including the high-resistivity portion is not The P-type thin layer 4 is completely depleted laterally. For the N-type thin layer that does not include the high-resistivity portion, the part of the N-type thin layer and its adjacent P-type thin layer 4 can be balanced, and the N-type thin layer and the P-type thin layer When the reverse bias voltage is connected between the thin layers 4 , the N-type thin layer excluding the high-resistivity part can be completely depleted laterally by the P-type thin layer 4 .

When the device in Embodiment 8 of the present invention is turned on, the N-type thin layer, that is, the first N-type thin layer 3 and the second N-type thin layer 3a provide the current flow region of the device; when the device is turned off At this time, part of the N-type impurities in the N-type thin layer are depleted by the impurities in the P-type thin layer 4; or at least part of the N-type impurities in the second N-type thin layer 3a are all depleted by the impurities The impurities in the P-type thin layer 4 are depleted, and the sum of the N-type partial impurities in the second N-type thin layer 3a on both sides of the first N-type thin layer 3 is equal to that of the P-type thin layer 4 The absolute value of the difference of the sum of impurities in can not be greater than 20% of the sum of any one of them.

Preferably, the resistivity of the P-type thin layer 4 is 2.74 ohm·cm, and the impurity concentration is 5e15cm ^-3 ; the width of the P-type thin layer 4 is 3 microns, which is composed of two 1.5 micron The second P-type silicon epitaxial layer is formed after bonding in the middle of the trench.

Step 5, as shown in Figure 19, form a P well 7 on the top of each of the P-type thin layers 4, and each of the P-type wells 7 also extends to part of the top of the N-type thin layer; The top region of the N-type thin layer is the N-type conduction region 16 . Preferably, a step of performing N-type ion implantation in the N-type conduction region 16 is also included, and the N-type ion implantation can reduce the specific on-resistance of the device.

Step 6. As shown in FIG. 19 , deposit the gate dielectric layer 5 and the polysilicon gate 6 in sequence, and etch the polysilicon gate 6 and the gate dielectric layer 5 sequentially by photolithography, and the etched The gate dielectric layer 5 and the polysilicon gate 6 form the gate structure of the super junction planar gate MOSFET device; the polysilicon gate 6 covers the N-type thin layer and part of the P well 7 from the top, and is covered by The P well 7 covered by the polysilicon gate 6 is used to form a lateral channel.

Step 7, as shown in FIG. 19 , perform N+ ion implantation to form a source region 8 ; the source region 8 is formed on the top of the P well 7 and self-aligned with the polysilicon gate 6 .

Step 8. As shown in FIG. 19 , an interlayer film 10 is formed on the front surface of the silicon substrate 1 on which the source region 8 is formed; a contact hole 11 is formed by photolithography, and the contact hole 11 passes through the The interlayer film 10 is in contact with the source region 8 or the polysilicon gate 6; P+ ion implantation is performed to form a P-well lead-out region 9, and the P-well lead-out region 9 is located on the source region 8 in contact with the The bottom of the contact hole 11 , the P well lead-out region 9 is in contact with the P well 7 .

Step 9, as shown in FIG. 19 , depositing the front metal 12 and performing photolithography on the front metal 12 to form a source and a gate respectively;

Step ten, as shown in FIG. 19 , thinning the silicon substrate 1 from the back side.

Step eleven, as shown in FIG. 19 , perform back ion implantation to form an N-type region 2 , and the N-type region 2 is located at the bottom of the N-type thin layer and the P-type thin layer 4 . Preferably, the thickness of the N-type region 2 is 0.5 microns to 5 microns, which is obtained by controlling the thickness of the thinned back side of the silicon substrate 1. In the double arrow line EDC in FIG. 4, the boundary E , D are respectively the back and upper boundaries of the N-type region 2, and the boundary C is in the N-type thin layer. Since the thickness of the N-type region 2 is small, the doping of the N-type region 2 is realized by one-time ion implantation such as implanting phosphorus, the implantation energy is 50-500KEV, and the dose is higher than 5E14CM ^-2 .

Step twelve, as shown in FIG. 19 , activating the ions in the N-type region 2 . Preferably, the impurity in the N-type region 2 is activated by one laser annealing, one furnace tube annealing, or a combination of one laser annealing and one furnace tube annealing. After activation, the longitudinal distribution of the impurity concentration of the N-type region 2 is shown in Fig. 10a and Fig. 10b.

Step thirteen, as shown in FIG. 19 , perform back metallization to form the drain 13 .

The difference between the super-junction device in Embodiment 9 of the present invention and the super-junction device in Embodiment 8 of the present invention is that the super-junction device in Embodiment 9 of the present invention is a super-junction planar gate IGBT device, and a There is a P-type region consisting of a P+ region formed using backside ion implantation. The N-type region 2 becomes a field stop layer, and the P-type region becomes the collector region of the device; the whole forms an IGBT device. The structural features of the P-type region 14 in Embodiment 9 of the present invention are the same as those of the P-type region 4 of the super junction device in Embodiment 3 of the present invention.

The difference between the manufacturing method of the super junction device in the ninth embodiment of the present invention and the manufacturing method of the super junction device in the eighth embodiment of the present invention is that in step 11, after the back ion implantation is performed to form the N-type region 2, the back ion implantation is also included. The P-type region is formed.

In the above embodiments, only super junction MOSFET devices and IGBT devices are listed, and the P-N thin layer structure of the embodiments of the present invention is also applicable to power devices with super junction structures such as super junction high voltage diodes.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (20)

1. a super-junction device, super-junction device is formed in N-type silicon substrate, and the zone line of described super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; It is characterized in that:

Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer;

Described silicon substrate is formed with multiple groove, and each described N-type thin layer is made up of the first N-type thin layer and the second N-type thin layer all respectively; Described first N-type thin layer is made up of the silicon substrate thin layer between described groove, described second N-type thin layer forms by be filled in described groove and to be positioned at described first N-type thin layer both sides first N-type silicon epitaxy layer, described P type thin layer is made up of the second P-type silicon epitaxial loayer be filled in described groove, and the described second N-type thin layer of each described P type thin layer and its both sides contacts and filled completely by the described groove of correspondence;

The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;

The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,

The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;

The N-type region be made up of backside particulate injection region is formed bottom described N-type thin layer and described P type thin layer.

2. super-junction device as claimed in claim 1, is characterized in that: described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer of whole described N-type thin layer;

Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer from described second N-type thin layer and spread all in the width range of whole described first N-type thin layer, and the resistivity of described first N-type thin layer zone line is lower than the resistivity of described silicon substrate.

3. super-junction device as claimed in claim 1, it is characterized in that: described N-type region is made up of ground floor N-type region and second layer N-type region, described ground floor N-type region is bottom described N-type thin layer and described P type thin layer, described second layer N-type region is near the back side of described silicon substrate, the doping content of described second layer N-type region is greater than the doping content of described ground floor N-type region, the metal at the back side that the doping content of described second layer N-type region meets and is formed at described silicon substrate forms the condition of ohmic contact, and described first N-type region is as the resilient coating of described super-junction device.

4. super-junction device as claimed in claim 1, is characterized in that: the thickness of described N-type region is 0.5 micron ~ 5 microns.

5. super-junction device as claimed in claim 3, it is characterized in that: the thickness of described ground floor N-type region is 3 microns ~ 50 microns, the thickness of described second layer N-type region is 0.5 micron ~ 3 microns.

6. super-junction device as claimed in claim 1, is characterized in that: be also formed with the p type island region be made up of backside particulate injection region at the back side of described N-type region.

7. super-junction device as claimed in claim 1 or 2, is characterized in that: the described N-type thin layer comprising described high-resistivity portions in described current flowing district is distributed in one or more regions in described current flowing district.

8. super-junction device as claimed in claim 2, is characterized in that: the distributed areas of described N-type thin layer comprising described high-resistivity portions in described current flowing district and the region of described terminal protection structure do not adjoin.

9. super-junction device as claimed in claim 2, is characterized in that: the region comprising the distributed areas of the described N-type thin layer of described high-resistivity portions and the grid metal electrode figure of described super-junction device in described current flowing district does not adjoin.

10. a manufacture method for super-junction device, described super-junction device is super junction trench gate mosfet device, it is characterized in that, comprises the steps:

Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;

Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;

The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;

The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,

Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;

The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;

Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district;

Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside;

Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel;

Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region;

Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;

Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;

Step 11, carry out thinning from the back side to described silicon substrate;

Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer;

Step 13, the ion of described N-type region to be activated;

Step 14, carry out back face metalization formed drain electrode.

11. methods as claimed in claim 10, is characterized in that: the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 11 is thinning and step 2 is 0.5 micron ~ 40 microns.

12. methods as claimed in claim 10, is characterized in that: at least comprise a laser annealing in the activation technology in step 13.

13. methods as claimed in claim 10, is characterized in that: carry out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 7 advances to step one.

The manufacture method of 14. 1 kinds of super-junction devices, described super-junction device is super junction flat-grid MOSFET component, it is characterized in that, comprises the steps:

Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;

Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;

The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;

The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,

Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;

The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;

Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district;

Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel;

Step 7, carry out N+ ion implantation formed source region; Described source region be formed at described P trap top and and described polysilicon gate autoregistration;

Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;

Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;

Step 10, carry out thinning from the back side to described silicon substrate;

Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer;

Step 12, the ion of described N-type region to be activated;

Step 13, carry out back face metalization formed drain electrode.

15. methods as claimed in claim 14, is characterized in that: the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 10 is thinning and step 2 is 0.5 micron ~ 40 microns.

16. methods as claimed in claim 14, is characterized in that: at least comprise a laser annealing in the activation technology in step 12.

17. methods as claimed in claim 14, is characterized in that: carry out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 5 advances to step one.

18. methods as claimed in claim 14, is characterized in that: after the described P trap of step 5 is formed, before the described gate dielectric layer deposit of step 6, be also included in the step of carrying out N-type ion implantation in described N-type conducting district.

The manufacture method of 19. 1 kinds of super-junction devices, described super-junction device is super junction trench gate IGBT device, it is characterized in that, comprises the steps:

Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;

Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;

The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;

The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,

Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;

The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, the charge balance of described N-type thin layer and its contiguous described P type thin layer or imbalance, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, the first N-type thin layer of the complete having lateral depletion of whole described N-type thin layer or described N-type thin layer is not by the complete having lateral depletion of described P type thin layer;

Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district;

Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside;

Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel;

Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region;

Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;

Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;

Step 11, carry out thinning from the back side to described silicon substrate;

Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region;

Step 13, the ion of described N-type region and described p type island region to be activated;

Step 14, carry out back face metalization formed drain electrode.

The manufacture method of 20. 1 kinds of super-junction devices, described super-junction device is super junction flat-grid MOSFET component, it is characterized in that, comprises the steps:

Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;

Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;

The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;

The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,

Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;

The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;

Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district;

Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel;

Step 7, carry out N+ ion implantation formed source region; Described source region be formed at described P trap top and and described polysilicon gate autoregistration;

Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;

Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;

Step 10, carry out thinning from the back side to described silicon substrate;

Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region;

Step 12, the ion of described N-type region and described p type island region to be activated;

Step 13, carry out back face metalization formed drain electrode.