CN111180450B - A kind of semiconductor device and its manufacturing method, electronic device - Google Patents

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a semiconductor substrate, and forming a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer on the semiconductor substrate; patterning the mask layer and the control gate material layer to form a plurality of control gates which are mutually spaced; oxidizing the side wall of the control gate to form a protective layer on the side wall of the control gate; and etching the isolation insulating layer and the floating gate material layer by taking the control gate as a mask to form the floating gate. According to the preparation method of the semiconductor device, after the control gate is formed and before the floating gate material layer is etched, the protection layer is not formed through a deposition method, but the exposed side wall of the control gate is oxidized to form the protection layer, so that the side wall of the control gate is protected from being damaged in the subsequent process of etching the floating gate material layer, and meanwhile, electric leakage between the control gates can be avoided.

Description

A kind of semiconductor device and its manufacturing method, electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

With the development of semiconductor process technology, a flash memory with a faster access speed has been developed in the storage device. Flash memory has the characteristics that information can be stored, read and erased many times, and the stored information will not disappear after the power is turned off. A widely used non-volatile memory. On the other hand, NAND (NAND gate) flash memory is widely used in fields with high read/write requirements due to its large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2 GB, and the size is rapidly increasing. Solid state drives based on NAND flash memory chips have been developed and used as storage devices in portable computers. Therefore, in recent years, NAND flash memory is widely used as a storage device in embedded systems and also as a storage device in personal computer systems.

In the NAND preparation process, a stack of the floating gate material layer and the control gate material layer is first formed, and the floating gate material layer and the control gate material layer are patterned in turn. After the control gate material layer is patterned to form the control gate, the During the process of patterning the control gate material layer, sidewalls of the control gate may be damaged, which affects the performance and yield of the device. In addition, how to avoid leakage between control gates has also become a problem to be solved.

Therefore, it is necessary to propose a new fabrication method to solve the above problems.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In order to overcome the existing problems, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

providing a semiconductor substrate on which a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer are formed;

patterning the mask layer and the control gate material layer to form a plurality of control gates spaced apart from each other;

oxidizing the sidewall of the control gate to form a protective layer on the sidewall of the control gate;

Using the control gate as a mask, the isolation insulating layer and the floating gate material layer are etched to form a floating gate.

Optionally, the protective layer is formed through a SPA oxidation process or a rapid thermal annealing oxidation process.

Optionally, the control gate material layer uses silicon or polysilicon.

Optionally, the protective layer is not formed on the isolation insulating layer.

Optionally, a strip-shaped floating gate material layer is formed on the semiconductor substrate, and the mask layer and the control gate material layer are patterned so that the strip-shaped floating gate material layer extends in the direction of extension. A number of control gates spaced apart from each other are formed thereon.

Optionally, an isolation structure between the floating gate material layers is further formed in the semiconductor substrate to isolate the adjacent strip-shaped floating gate material layers.

Optionally, the protective layer is removed while or after etching the isolation insulating layer and the floating gate material layer.

Optionally, the semiconductor device is a NAND memory cell.

The present invention also provides a semiconductor device prepared by the above method.

The present invention also provides an electronic device including the above-mentioned semiconductor device.

In the preparation method of the semiconductor device provided by the present invention, after the control gate is formed and before the floating gate material layer is etched, the protective layer is not formed by a deposition method, but the sidewall of the exposed control gate is oxidized to form the protection layer to protect the sidewall of the control gate from being damaged during the subsequent etching process of the floating gate material layer, so that the obtained control gate has a good profile, and at the same time, leakage between the control gates can be avoided, further improving the Performance and yield of semiconductor devices.

Another aspect of the present invention provides a semiconductor device and an electronic device, the semiconductor device is manufactured by the above method, and the electronic device includes the above semiconductor device.

The semiconductor device and electronic device proposed by the present invention have similar advantages because they are prepared by the above method.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

FIG. 1 shows a flow chart of steps of a method for fabricating a semiconductor device according to an embodiment of the present invention;

2A-2C show a schematic cross-sectional view of the device obtained by a method for fabricating a semiconductor device;

FIG. 3 is a schematic diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, or to, the other elements or layers. adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

At present, in the NAND preparation process, a stack of the floating gate material layer and the control gate material layer is first formed, and the floating gate material layer and the control gate material layer are patterned in turn. After the control gate material layer is patterned to form the control gate, During the process of patterning the control gate material layer, damage may be caused to the sidewalls of the control gate, which affects the performance and yield of the device. In order to solve this problem, the applicant tried to deposit a protective layer on the sidewalls of the exposed polysilicon. However, as the size of the device continues to shrink, the spacing between the control gates is also getting smaller and smaller. Another problem arises after the upper deposition to form the protective layer, that is, leakage current occurs between the control gates.

In order to solve the problems existing in the current process, the present invention provides a manufacturing method of a semiconductor device for manufacturing a NAND flash memory.

As shown in Figure 1, the method includes:

Step S1: providing a semiconductor substrate on which a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer are formed;

Step S2: patterning the mask layer and the control gate material layer to form a plurality of control gates spaced apart from each other;

Step S3: oxidizing the sidewall of the control gate to form a protective layer on the sidewall of the control gate;

Step S4: Using the control gate as a mask, etching the isolation insulating layer and the floating gate material layer to form a floating gate.

After the control gate is formed, before etching the floating gate material layer, instead of forming a protective layer by deposition, the sidewall of the exposed control gate is oxidized to form a protective layer, so as to protect the sidewall of the control gate in the The floating gate material layer is no longer damaged in the subsequent etching process, so that the obtained control gate has a good outline, and meanwhile, leakage current between the control gates can be avoided, and the performance and yield of the semiconductor device can be further improved.

For a thorough understanding of the present invention, detailed structures and steps will be presented in the following description, so as to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2A to 2C .

First, as shown in FIG. 2A , a semiconductor substrate 200 is provided, a plurality of floating gate material layers 201 are formed on the semiconductor substrate 200 , and a plurality of floating gate material layers 201 are formed between adjacent floating gate material layers 201 extending downward to The shallow trench isolation structure 202 in the semiconductor substrate 200 is shown in FIG. 2A .

The semiconductor substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI) , silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

In one example, the method for forming the floating gate material layer 201 and the shallow trench isolation structure 202 includes the following steps A1 to A4:

Step A1 is performed to form a floating gate material layer and a mask layer on the semiconductor substrate.

Specifically, a floating gate material layer is formed on the semiconductor substrate, and the floating gate material layer may be a polysilicon layer to form a floating gate structure in a subsequent step.

The mask layer may be a hard mask layer, such as SiN, to protect the floating gate material layer from damage during the process of forming the shallow trench.

Step A2 is performed to pattern the mask layer, the floating gate material layer and the semiconductor substrate to form a plurality of strip-shaped floating gate material layers isolated from each other and shallow floating gates located between the strip-shaped floating gates groove.

Specifically, a dry etching process is performed to sequentially etch the hard mask layer, the floating gate material layer and the semiconductor substrate 200 to form shallow trenches. Specifically, a photoresist layer with a pattern can be formed on the hard mask layer, and the hard mask layer is dry-etched by using the photoresist layer as a mask, so as to transfer the pattern to the hard mask layer, and use the photoresist layer as a mask to dry-etch the hard mask layer. The photoresist layer and the hard mask layer are used as masks to etch the floating gate material layer and the semiconductor substrate 200 to form trenches, and to form strip-shaped strips isolated from each other by shallow trenches in the floating gate material layer. Floating gate material layer 201 .

The number of the floating gate structures is not limited to a certain numerical range.

Step A3 is performed to fill the trenches with isolation material to form a shallow trench isolation structure.

Specifically, an isolation material may be formed on the hard mask layer and in the trench, and the isolation material may be silicon oxide, silicon oxynitride and/or other existing low dielectric constant materials; perform a chemical mechanical polishing process and stop on the hard mask layer to form shallow trench isolation structures.

Finally, step A4 is performed to remove the hard mask layer. The method for removing the remaining hard mask layer may be a wet etching process. Since the etchant for removing the hard mask layer is well known in the art, it will not be described in detail.

Removing the oxide layer and the nitride layer results in a pattern with a shallow trench isolation structure, and optionally, this step further includes performing well and threshold voltage adjustments on the pattern.

作为后续氮化硅层的应力缓冲层；由于本实施例的半导体器件制作方法用于制作NAND器件的外围区域，因此，在所述衬垫氧化层之上还形成有浮栅材料层，其通过常规的CVD(化学气相沉积法)形成，厚度为

然后在浮栅材料层上形成硬掩膜层，示例性硬掩膜层为氮化硅层，其通过CVD方法形成，厚度为

在后续STI隔离材料填充中保护有源区，并可作为后续CMP的阻挡层；刻蚀所述硬掩膜层形成与STI结构对应的图案，然后以硬掩膜层为掩膜刻蚀栅极材料层、垫氧化层(pad oxide)和半导体衬底形成沟槽；在所述沟槽的侧壁和底部上形成衬垫氧化层，示例性地通过高温氧化层形成衬垫氧化层，作为后续隔离层填充时的生成层；在所述沟槽中填充隔离材料，比如硅的氧化物，然后执行平坦化，去除所述隔离材料位于硬掩膜层之上的部分，以形成浅沟槽隔离结构。接着，去除所述硬掩膜层。示例性，在本实施例中，通过湿法刻蚀工艺去除硬掩膜层，比如通过合适浓度的磷酸溶液去除硬掩膜层。In another embodiment of the present invention, a method for forming an STI (Shallow Trench Isolation Structure) exemplarily includes the following steps: forming a pad oxide layer on the semiconductor substrate, the pad oxide layer exemplarily is a silicon dioxide layer, which is formed by thermal oxidation and has a thickness of

As the stress buffer layer of the subsequent silicon nitride layer; since the semiconductor device fabrication method of this embodiment is used to fabricate the peripheral region of the NAND device, a floating gate material layer is also formed on the pad oxide layer, which passes through the pad oxide layer. Conventional CVD (Chemical Vapor Deposition) formation with a thickness of

A hard mask layer is then formed on the floating gate material layer, an exemplary hard mask layer is a silicon nitride layer, which is formed by a CVD method and has a thickness of

The active area is protected in the subsequent filling of the STI isolation material, and can be used as a barrier layer for the subsequent CMP; the hard mask layer is etched to form a pattern corresponding to the STI structure, and then the gate is etched using the hard mask layer as a mask A material layer, a pad oxide and a semiconductor substrate form a trench; a pad oxide is formed on the sidewalls and bottom of the trench, exemplarily by a high temperature oxide, as a follow-up Generation layer during isolation layer filling; the trenches are filled with isolation material, such as silicon oxide, and then planarization is performed to remove the portion of the isolation material above the hard mask layer to form shallow trench isolation structure. Next, the hard mask layer is removed. Exemplarily, in this embodiment, the hard mask layer is removed by a wet etching process, such as removing the hard mask layer by a phosphoric acid solution of a suitable concentration.

Next, as shown in FIGS. 2A and 2B, an isolation insulating layer 204, a control gate material layer 205 and a mask layer 206 are formed on the strip-shaped floating gate material layer;

The isolation insulating layer 204 can be selected from a common oxide or a stack of oxides, preferably ONO (oxide-nitride-oxide structured insulating gate dielectric layer).

The control gate material layer 205 may be a commonly used semiconductor material layer, such as silicon or polysilicon, and in a specific embodiment of the present invention, it is preferably polysilicon.

The polysilicon can be selected from decompression epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy and molecular beam epitaxy, and epitaxy is preferably selected in the present invention.

A hard mask layer (nitride hard mask layer) is selected for the mask layer, and the hard mask layer can be one or more of oxides, nitrides (SiN, BN and SiCN). In an embodiment of the invention, the hard mask layer is made of oxide, which can be formed by a deposition method or an epitaxy method, preferably a chemical vapor deposition (CVD) method or a selective epitaxial growth (SEG) method, and the thickness of the mask layer is 50 Å. -1000 angstroms.

Next, referring to FIG. 2A , the control gate material layer and the mask layer are patterned to form a plurality of control gates spaced apart from each other.

Specifically, in this step, the control gate material layer and the mask layer are patterned to form several control gates spaced apart from each other in the extending direction of the strip-shaped floating gate material layer.

As an alternative implementation manner, in another embodiment of the present invention, the control gate material layer and the mask layer are patterned to form a square control gate. Arrays of control gates spaced from each other are formed in the extending direction and in the direction perpendicular to the extending direction of the strip-shaped floating gate material layer.

Wherein, in this step, dry etching or wet etching can be used to etch the control gate material layer and the mask layer, and the isolation insulating layer 204 is used as a stop layer. Optionally, the control gate material layer and the mask layer may be etched by a method having a larger etching selectivity ratio than that of the isolation insulating layer 204 .

Next, as shown in FIG. 2B , the sidewalls of the control gates are oxidized to form a protective layer 207 on the sidewalls of the control gates to cover the sidewalls of the control gates.

Specifically, the protective layer is formed by a SPA (slot plane antenna) oxidation process or a thermal oxidation method.

Exemplarily, in the SPA process, oxygen-containing plasma may be generated at a process temperature of 300° C.˜500° C. under a microwave power of 1000 W˜4000 W to treat the surface layer of the sidewall of the control gate, so that the The surface layer of the sidewalls of the control gate is converted to an oxide of silicon, such as silicon dioxide. The processing time is determined according to the thickness of the silicon oxide layer to be formed. Exemplarily, in this embodiment, the oxygen-containing plasma is generated by using H ₂ /O ₂ gas with a ratio between 1% and 50%, The SPA oxidation process time is 10s˜300s, and the formed oxide layer 206 is formed.

Exemplarily, the protective layer may also be formed by a thermal oxidation method, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), etc. to form the protective layer. In an embodiment of the present invention, a protective layer 207 is deposited on the sidewall of the control gate by using rapid thermal annealing oxidation (RTO).

The method for forming the protective layer is not limited to the above two examples, and other methods may also be used.

Wherein, after the protective layer is formed on the sidewall of the control gate, in the subsequent etching process, the sidewall of the control gate is covered to prevent damage to the sidewall of the control gate during the etching, so as to keep the sidewall of the control gate from being damaged. good silhouette. In addition, since the protective layer is formed by an oxidation method, the gap between the control gates will not be reduced, and the leakage current between the control gates can be further avoided.

Wherein, the protective layer includes oxide but is not limited to oxide. When oxide is selected for the protective layer, the protective layer can be removed at the same time when the isolation insulating layer and the floating gate material layer are subsequently etched .

Optionally, in this step, the protective layer is not formed on the isolation insulating layer.

Next, as shown in FIG. 2C , using the control gate as a mask, the isolation insulating layer and the floating gate material layer are etched to form a floating gate.

Optionally, the protective layer is removed while or after etching the isolation insulating layer and the floating gate material layer.

Further, at least part of the hard mask layer and/or the isolation oxide in the shallow trench isolation structure is removed at the same time as or after the etching of the isolation insulating layer and the floating gate material layer.

In this step, using the control gate as a mask, the isolation insulating layer and the floating gate material layer exposed between the control gates are etched to form a floating gate.

Wherein, since the sidewall of the control gate is covered by the protective layer during the etching process, the sidewall of the control gate will not be damaged. Leakage between control gates can be further avoided.

So far, the process steps implemented by the method according to the embodiment of the present invention have been completed. It can be understood that the method for fabricating a semiconductor device in this embodiment not only includes the above steps, but may also include other required steps before, during or after the above steps, For example, the etching of the control gate/floating gate in the peripheral region and the fabrication of the storage region (cell) of the NAND device are all included in the scope of the fabrication method of the present embodiment.

It can be understood that, in the manufacturing method of the semiconductor device proposed by the present invention, after forming the control gate and before etching the floating gate material layer, a protective layer is formed on the sidewall of the exposed control gate to protect the sidewall of the control gate. The walls are no longer damaged during subsequent etching of the layer of floating gate material, so that the resulting control gate has a good profile. In addition, since the protective layer is formed by an oxidation method, the gap between the control gates will not be reduced, and the leakage current between the control gates can be further avoided, thereby further improving the performance and yield of the semiconductor device.

In addition, the present invention also provides a semiconductor device.

The semiconductor device includes:

semiconductor substrate;

A floating gate, an isolation insulating layer and a control gate on the semiconductor substrate.

Wherein the semiconductor substrate can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes multilayer structures composed of these semiconductors etc. or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Likewise, a conductive member may also be formed in the semiconductor substrate, and the conductive member may be a gate electrode, a source electrode or a drain electrode of a transistor, or a metal interconnection structure electrically connected to the transistor, and the like. In this embodiment, the constituent material of the semiconductor substrate is single crystal silicon.

The semiconductor device of the present embodiment is prepared by the above method. Since a protective layer is formed on the sidewall of the control gate during the etching process of the floating gate to prevent damage to the sidewall of the control gate, the control gate has a better profile. In addition, since the protective layer is formed by an oxidation method, the gap between the control gates will not be reduced, and the leakage current between the control gates can be further avoided, thereby further improving the performance and yield of the semiconductor device.

Yet another embodiment of the present invention provides an electronic device, including the above embodiments

The semiconductor device and the electronic assembly connected with the semiconductor device.

Wherein, the electronic component can be any electronic component such as a discrete device, an integrated circuit, or the like.

The electronic device in this embodiment may be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video camera, voice recorder, MP3, MP4, PSP, etc. , or any intermediate product including the semiconductor device.

Among them, FIG. 3 shows an example of a mobile phone. The exterior of the cellular phone 300 is provided with a display portion 302 included in a casing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

Since the electronic device of the embodiment of the present invention includes the above-mentioned semiconductor device, the electronic device also has similar advantages.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (9)

1. a preparation method of a semiconductor device, is characterized in that, comprises the following steps: providing a semiconductor substrate on which a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer are formed; patterning the mask layer and the control gate material layer to form a plurality of control gates spaced apart from each other; oxidizing the sidewall of the control gate to form a protective layer on the sidewall of the control gate; Using the control gate as a mask, etching the isolation insulating layer and the floating gate material layer to form a floating gate; The protective layer is removed. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the protective layer is formed by a SPA oxidation process or a rapid thermal annealing oxidation process. 3 . 3 . The method for fabricating a semiconductor device according to claim 1 , wherein the control gate material layer uses silicon. 4 . 4 . The method for fabricating a semiconductor device according to claim 1 , wherein the protective layer is not formed on the isolation insulating layer. 5 . 5 . The method for manufacturing a semiconductor device according to claim 1 , wherein a strip-shaped floating gate material layer is formed on the semiconductor substrate, and the mask layer and the control gate material layer are patterned. 6 . , so as to form several control gates spaced apart from each other in the extending direction of the strip-shaped floating gate material layer. 6 . The method for fabricating a semiconductor device according to claim 5 , wherein an isolation structure between the floating gate material layers is further formed in the semiconductor substrate to isolate the adjacent strips. 7 . shaped floating gate material layer. 7. The method for fabricating a semiconductor device according to claim 1, wherein the semiconductor device is a NAND memory cell. 8 . A semiconductor device, characterized in that, the semiconductor device is prepared by the method according to any one of claims 1 to 7 . 9. An electronic device comprising the semiconductor device of claim 8.

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