CN110648916B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, and an electronic device. The method includes: providing a substrate including an NMOS region and a PMOS region on which fins and dummy gates surrounding the fins are formed, wherein the The fin includes fin material layers and sacrificial layers stacked alternately from bottom to top; removing the dummy gate to form a groove and exposing the fin; removing the sacrificial layer exposed in the groove to The interval between the fins is a suspended part and a base part; a first work function layer is formed on the base part of the fin in the NMOS region and on the surface of the fin in the PMOS region; forming a second work function layer on the surface of the fin in the NMOS region and the PMOS region; filling the groove with a conductive material to form a metal gate. The method can suppress the generation of leakage current, and further improve the performance and yield of the FinFET device.

Description

A kind of semiconductor device and its manufacturing method, electronic device

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

With the increasing progress of semiconductor integrated circuit manufacturing technology, in the past few decades, in order to obtain higher performance circuits, the size of MOSFET has been continuously reduced, because the smaller MOSFET will reduce the channel length, so that the channel etc. The effective resistance is also reduced, allowing more current to pass through, and the smaller size of the MOSFET also means that the gate area is reduced, which in turn can reduce the equivalent gate capacitance.

The size reduction of MOSFET can bring many benefits, but at the same time it also causes many negative effects. As a result, the channel formed between the source/drain ion-doped regions is further reduced, and there is inevitably a relatively serious short-channel effect, and a large parasitic capacitance is formed in the source-drain region, resulting in a more The larger the leakage, the greater the power consumption, and the lower the ability to resist breakdown.

Compared with the existing planar transistors, FinFET devices have superior performance in terms of channel control and reducing short channel effects; the planar gate structure is arranged above the channel, and in the FinFET the gate surrounds the The above-mentioned fins are set, so the static electricity can be controlled from three sides, and the performance in static electricity control is also more prominent.

With the continuous development of CMOS technology, a multi-gate structure, such as a gate all around (GAA), has appeared in the semiconductor device manufacturing technology to enhance the performance and integration of the device. However, parasitic channels appear under the fins in the gate allaround (GAA), resulting in leakage current and performance degradation of the device.

In view of the existence of the above technical problems, it is necessary to propose a new method for manufacturing semiconductor devices.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

Aiming at the deficiencies in the prior art, the invention provides a method for manufacturing a semiconductor device, the method comprising:

A substrate is provided, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the fins include Fin material layers and sacrificial layers stacked alternately upward;

removing the dummy gate to form a groove and expose the fin;

removing the sacrificial layer exposed in the groove to separate the fins into a suspension portion and a base portion;

forming a first work function layer on a base portion of the fin in the NMOS region and on a surface of the fin in the PMOS region;

forming a second work function layer on surfaces of the fins of the NMOS region and the PMOS region;

The groove is filled with a conductive material to form a metal gate.

Optionally, the method for forming the first work function layer includes:

sequentially forming an interface layer, a gate dielectric layer and a first work function layer on the exposed surface of the fin;

removing the first work function layer on the surface of the floating part of the fin in the NMOS region and retaining the first work function layer on the surface of the base part of the fin in the NMOS region.

Optionally, the method for removing the first work function layer on the surface of the suspended portion of the fin in the NMOS region includes:

depositing a mask layer to cover the grooves in the NMOS region and the PMOS region;

patterning the mask layer to remove part of the mask layer in the NMOS region and expose at least the first work function layer on the surface of the suspended part of the fin;

removing the first work function layer on the surface of the suspended portion of the fin in the exposed NMOS region.

Optionally, the method further includes the step of removing the remaining mask layer.

Optionally, an isolation material layer filling the gaps between the fins is further formed on the semiconductor substrate, and the top of the isolation material layer is flush with the top of the base portion of the fins.

Optionally, the first work function layer is formed on the level of the base portion of the fin and on the isolation material layer.

The present invention also provides a semiconductor device, the semiconductor device comprising:

a substrate comprising an NMOS region and a PMOS region;

Fins formed in the NMOS region and the PMOS region, wherein the fins include a floating portion and a base portion that are spaced apart from each other in the region where the metal gate is formed;

Metal gate structures, including:

a first work function layer located on the level of the base portion in the NMOS region and the PMOS region and on the surface of the floating portion in the PMOS region;

a second work function layer on the first work function layer and on the surface of the floating portion of the fin in the NMOS region;

A conductive material covers the fin and fills the space between the suspension portion and the base portion.

Optionally, an interface layer and a gate dielectric layer are further formed on the surface of the fin.

Optionally, an isolation material layer filling the gaps between the fins is further formed on the semiconductor substrate, and the top of the isolation material layer is flush with the top of the base portion of the fins.

Optionally, the first work function layer is formed on the base portion of the fin and on the isolation material layer.

The present invention also provides an electronic device, which includes the above-mentioned semiconductor device.

According to the manufacturing method of the semiconductor device of the present invention, in order to solve the problem of parasitic channels in the FinFET device, a first work function layer is formed on the horizontal plane of the base part in the NMOS region and the PMOS region, Especially on the parasitic device in the NMOS region, and for the NMOS parasitic device, the first work function layer has a higher threshold voltage, thereby suppressing the generation of leakage current and further improving the performance and yield of the FinFET device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1A to FIG. 1J show a schematic structural view of a device obtained in the relevant steps of the manufacturing method of a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 3 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, detailed steps will be provided in the following description, so as to explain the technical solution proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

The current method for preparing FinFET devices includes the following steps:

A substrate is provided, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the fins include Fin material layers and sacrificial layers stacked alternately upward;

removing the dummy gate to form a groove and expose the fin;

removing the sacrificial layer exposed in the groove to separate the fins into a suspension portion and a base portion;

Formation of interfacial layer and high-K dielectric layer on the surface of the fin

The groove is filled with a conductive material to form a metal gate.

In the device prepared by the method, since the metal gate is a gate allaround (GAA), a parasitic device will be formed between the gate allaround and the base part, and the parasitic device will cause leakage current, so that the FinFET Device performance and reliability degrade.

In order to solve this problem, the present application provides a method for manufacturing a semiconductor device, the method comprising:

A substrate is provided, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the fins include Fin material layers and sacrificial layers stacked alternately upward;

removing the dummy gate to form a groove and expose the fin;

removing the sacrificial layer exposed in the groove to separate the fins into a suspension portion and a base portion;

forming a first work function layer on a horizontal surface of the base portion of the fin in the NMOS region;

forming a second work function layer on the surface of the fin in the NMOS region and the PMOS region;

The groove is filled with a conductive material to form a metal gate.

According to the manufacturing method of the semiconductor device of the present invention, in order to solve the problem of parasitic channels in the FinFET device, a first work function layer is formed on the horizontal plane of the base part in the NMOS region and the PMOS region, Especially on the parasitic device in the NMOS region, and for the NMOS parasitic device, the first work function layer has a higher threshold voltage, thereby suppressing the generation of leakage current and further improving the performance and yield of the FinFET device.

Embodiment one

In order to solve the foregoing technical problems and improve the performance of the device, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in FIG. 2 , the method mainly includes:

Step S1: providing a substrate, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the fins Including fin material layers and sacrificial layers stacked alternately from bottom to top;

Step S2: removing the dummy gate to form a groove and expose the fin;

Step S3: removing the sacrificial layer exposed in the groove, so as to separate the fin into a suspended part and a base part;

Step S4: forming a first work function layer on the base portion of the fin in the NMOS region and on the surface of the fin in the PMOS region;

Step S5: forming a second work function layer on the surface of the fin in the NMOS region and the PMOS region;

Step S6: filling the groove with a conductive material to form a metal gate.

Specifically, the manufacturing method of the semiconductor device of the present invention will be described in detail below with reference to FIGS. Schematic diagram of the structure.

First, step 1 is performed to provide a substrate, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the The fins include fin material layers and sacrificial layers stacked alternately from bottom to top.

Specifically, the method for forming the fins includes:

Step 1: Provide a semiconductor substrate, alternately deposit fin material layers and sacrificial layers on the semiconductor substrate, and then pattern the alternately deposited fin material layers and sacrificial layers to form on the semiconductor substrate fins;

Step 2: Depositing an isolation material layer to cover the fins;

Step 3: Etching back the isolation material layer to expose the fins at the target height;

Step 4: forming a dummy gate on the fin.

In the step 1, as shown in FIG. 1A, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI) are laminated.

Wherein the semiconductor substrate includes an NMOS region and a PMOS region, so as to form NMOS devices and PMOS devices in subsequent steps.

A plurality of fins 102 are formed on the semiconductor substrate in the NMOS region and the PMOS region, for example, several fins with the same height are formed in the active region and the surrounding region, and the widths of the fins are all the same, or the fins Divided into groups of fins with different widths.

Wherein, the fin material layer is selected from polysilicon, and the sacrificial layer is selected from SiGe.

Specifically, the method of forming the fins is not limited to a certain method, and an exemplary method of forming is given below: a hard mask layer is formed on the alternately deposited fin material layers 1021 and sacrificial layers 1022, and the fins are formed. The hard mask layer can adopt various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process, and the hard mask layer can be an oxide layer and a silicon nitride layer stacked from bottom to top, In this embodiment, the hard mask layer is selected from nitride; the hard mask layer is patterned to form a plurality of isolated fins for alternately depositing fin material layers and sacrificial layers to form fins thereon. In one embodiment, the patterning process is performed using a self-aligned double patterning (SADP) process; the fin material layer 1021 and the sacrificial layer 1022 are etched below the semiconductor substrate to form the fin 102 .

In the present invention, several fins include several rows and several columns to form a fin array, wherein the shape of the fin array is not limited to a certain one, for example, the fin array can be square, rectangular, circle or polygon etc.

Optionally, the method further includes the step of forming a liner layer to cover the surface of the semiconductor substrate, the sidewalls of the fins, and the sidewalls and top of the hard mask layer.

Specifically, in one embodiment, the liner layer is formed using an in-situ steam generation process (ISSG).

Wherein, the threshold voltage of the upper part of the fin can also be adjusted by adjusting the thickness of the liner layer.

In the step 2, an isolation material layer 103 is deposited to completely fill the gaps between the fins, as shown in FIG. 1A . In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer 103 may be oxide, such as high aspect ratio process (HARP) oxide, specifically, silicon oxide.

In the step 3, the isolation material layer 103 is etched back to the target height of the fin to form an isolation structure, the top surface of the isolation structure is lower than the top surface of the fin. Specifically, the isolation material layer 103 is etched back to expose part of the fins, thereby forming fins with a specific height, as shown in FIG. 1A .

In the step 4, a dummy gate across the fin is formed.

It should be pointed out that the term "straddling" used in the present invention, such as the dummy gate across the fin, means that a dummy gate structure is formed on the upper surface and side surfaces of part of the fin, and the dummy gate structure A gate structure is also formed on a portion of the surface of the semiconductor substrate.

In one example, a dummy gate dielectric layer and a dummy gate material layer may be sequentially deposited on a semiconductor substrate first.

The deposition method of the dummy gate material layer can be selected from methods such as chemical vapor deposition or atomic layer deposition.

The layer of gate material is then patterned to form a dummy gate surrounding the fin.

In this step, the gate structure material layer is patterned to form a surrounding dummy gate, specifically, a hard mask layer is formed on the gate structure material layer, wherein the mask layer includes an oxide layer One or more of the metal hard mask layer and the oxide hard mask layer, and then exposed and developed to form an opening, and then the gate structure material layer is etched using the mask stack as a mask to A surrounding dummy gate is formed.

Afterwards, optionally, an offset sidewall can also be formed on the sidewall of the dummy gate.

The method for forming the offset sidewall can be a conventional method, and is not limited to a certain one, so it will not be repeated here.

The method further includes: forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer being flush with the top surface of the dummy gate.

In one example, an interlayer dielectric layer covering the dummy gate is formed, and a chemical mechanical polishing step is performed to polish the interlayer dielectric layer until the top surface of the dummy gate is exposed.

Various suitable processes familiar to those skilled in the art can be used to form the interlayer dielectric layer, such as chemical vapor deposition process. The interlayer dielectric layer may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, for example Undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped Tetraethoxysilane (BTEOS). Its thickness is not limited to a certain value.

Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.

The top surface of the finally formed interlayer dielectric layer is flush with the top surface of the dummy gate.

Step 2 is performed to remove the dummy gate to form a groove and expose the fin.

Specifically, a photoresist layer is formed on the dummy gate, and the photoresist layer is exposed and developed to form a patterned photoresist layer.

Using the patterned photoresist layer as a mask, etch and remove the dummy gate on the fin, as shown in FIG. 1A .

Wherein, the method of dry etching or wet etching can be used to remove the gate material layer, preferably, dry etching can be used, and the process parameters of the dry etching include: the flow rate of the etching gas HBr is 20-500 sccm , the pressure is 2-40mTorr, the power is 100-2000W, where mTorr stands for millimeters of mercury, and sccm stands for cubic centimeters per minute.

Next, the patterned photoresist layer is removed.

The patterned photoresist layer may be removed using dry etching or wet etching or a combination thereof.

Dry etching can be an ashing method. The ashing method is to use a plasma gas containing oxygen or oxygen ions to remove the photoresist layer. The ashing process is generally carried out at a high temperature. For example, the ashing temperature can be 80~ 300°C.

The wet etching may use an etchant including SPM solution, and the SPM solution includes a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ).

The method may further include the step of removing the dummy gate dielectric layer.

A high etch selectivity to the gate dielectric layer may be used to achieve removal of the gate dielectric layer.

In one example, in this step, the remaining dummy gate dielectric layer is removed by wet method with dilute hydrofluoric acid DHF (including HF, H ₂ O ₂ and H ₂ O). Wherein, the concentration of DHF is not strictly limited, and HF:H ₂ O ₂ :H ₂ O=0.1-1.5:1:5 is preferred in the present invention.

Step 3 is performed, removing the sacrificial layer exposed in the groove, so as to separate the fins into a suspension part and a base part.

Specifically, as shown in FIG. 1B , in this step, the exposed sacrificial layer is removed, thereby forming a structure in which fin material layers and cavities are arranged alternately, so as to separate the fins into suspended portions and base portions.

Wherein, the sacrificial layer is removed by a method having a large etching selectivity ratio to the fin material layer. For example, dry etching or wet etching can be selected.

Executing step 4, forming a first work function layer on the horizontal surface of the base portion of the fin in the NMOS region.

Specifically, the method for forming the first work function layer includes:

Step 1: sequentially forming an interface layer, a gate dielectric layer and a first work function layer on the exposed surface of the fin;

Step 2: depositing a mask layer to cover the grooves in the NMOS region and the PMOS region;

Step 3: patterning the mask layer to remove part of the mask layer in the NMOS region and expose at least the first work function layer on the surface of the suspended part of the fin;

Step 4: removing the first work function layer on the surface of the suspended portion of the fin in the exposed NMOS region.

In the step 1, an interface layer 104 and a high-k dielectric layer 105 are formed on the exposed surface of the fin.

Wherein, the interface layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer or other suitable thin film layers.

The interfacial layer can be formed by suitable processes such as thermal oxidation, chemical oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

The thickness of the interface layer can be reasonably set according to actual process requirements, for example, the thickness of the interface layer can range from 5 angstroms to 10 angstroms.

Exemplarily, the interface layer may be formed by using a chemical oxidation method, and the material of the formed interface layer may include silicon oxide.

Especially use SC-1 or ozone (Ozone) treatment solution to chemically oxidize to form the interface layer.

In the example of using SC-1, SC-1 is composed of NH ₄ OH-H ₂ O ₂ -H ₂ O, and its ratio can be (1:1:5)-(1:2:7), the reaction The temperature can be 50-80 degrees Celsius.

In the example of using Ozone treatment solution, the reaction conditions include using O ₃ and deionized water, and the reaction can be carried out at normal temperature.

Subsequently, a high-k dielectric layer 105 is formed, wherein both the interface layer and the high-k dielectric layer surround the suspension portion and cover the horizontal plane of the base portion.

The k value (dielectric constant) of the high-k dielectric layer is usually above 3.9, and its constituent materials include hafnium oxide, hafnium oxide silicon, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium oxide silicon, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide or aluminum oxide. A suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) can be used to form the high-k dielectric layer.

The thickness of the high-k dielectric layer ranges from 10 angstroms to 30 angstroms, and other suitable thicknesses can also be used.

Subsequent steps also include forming a capping layer, a diffusion barrier layer, and the like on the high-k dielectric layer.

Then a first work function layer 106 is deposited, wherein the first work function layer is a PMOS work function layer such as TiN.

In the step 2, a mask layer 107 is applied to cover the grooves in the NMOS region and the PMOS region, as shown in FIG. 1E .

Wherein, the BARC layer is selected as the mask layer to facilitate removal and avoid damage to the fins.

In the step 3, photolithography is performed on the mask layer, for example, a photoresist layer is formed on the mask layer to cover the PMOS region, and then the photoresist layer is used as a mask to etch the mask layer, so as to remove part of the mask layer in the NMOS region and expose at least the first work function layer on the surface of the suspended portion of the fin, as shown in FIG. 1E , while retaining all The first work function layer on the surface of the base portion of the fin in the NMOS region has a higher threshold voltage for the NMOS parasitic device due to the retained first work function layer , thereby suppressing the generation of leakage current, and further improving the performance and yield of the FinFET device.

Optionally, in this step, the mask layer above the first work function layer in the groove of the NMOS region is removed, as shown in FIG. 1F , or part of the mask layer above the first work function layer is retained. The layer exposes at least all of the freestanding portions of the fins.

In the step 4, removing the exposed first work function layer on the surface of the suspended part of the fin in the NMOS region, so as to expose the high K of the surface of the suspended part of the fin in the NMOS region dielectric layer, as shown in Figure 1G.

Optionally, the method further includes a step of removing the photoresist layer and the mask layer to expose the groove, as shown in FIG. 1H .

Optionally, an ashing method is used to remove the photoresist layer and the mask layer.

Step five is performed, forming a second work function layer on the surface of the fin in the NMOS region and the PMOS region.

Specifically, the second work function layer 108 is formed on the first work function layer and on the high-K dielectric layer exposed in the NMOS region, as shown in FIG. 1I .

Wherein, the second work function layer 108 is an NMOS work function layer, such as TiAl.

Step 6 is performed to fill the groove with a conductive material to form a metal gate.

Specifically, as shown in FIG. 1J , the groove is filled with a conductive material, wherein the conductive material can be selected from various metal materials commonly used in the field, such as W, etc., and is not limited to a certain one.

So far, the detailed description of the manufacturing method of the semiconductor device of the present invention has been completed, and other process steps may be required for the manufacture of a complete device, which will not be repeated here.

Embodiment two

The present invention also provides a semiconductor device, which is prepared by the method described in the first embodiment.

The semiconductor device includes:

a substrate comprising an NMOS region and a PMOS region;

Fins formed in the NMOS region and the PMOS region, wherein the fins include a floating portion and a base portion that are spaced apart from each other in the region where the metal gate is formed;

Metal gate structures, including:

a first work function layer located on the level of the base portion in the NMOS region and the PMOS region and on the surface of the floating portion in the PMOS region;

a second work function layer located on the first work function layer and on the surface of the floating portion in the NMOS region;

A conductive material covers the fin and fills the space between the suspension portion and the base portion.

Wherein, as shown in FIG. 1H, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and germanium-on-insulator Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

The substrate includes an NMOS area and a PMOS area on which fins are formed.

A plurality of fins 102 are formed on the semiconductor substrate. For example, several fins with the same height are formed in the NOMS region and the PMOS region, and the widths of the fins are all the same, or the fins are divided into multiple fins with different widths. group of fins.

The device is also formed with a liner layer to cover the surface of the semiconductor substrate, the sidewalls of the fins, and the sidewalls and top of the hard mask layer.

Wherein, the threshold voltage of the upper part of the fin can also be adjusted by adjusting the thickness of the liner layer.

An isolation material layer 103 is also deposited on the substrate to a target height of the fins to form an isolation structure.

An interlayer dielectric layer is formed on the semiconductor substrate to fill gaps between the metal gate structures.

Various suitable processes familiar to those skilled in the art can be used to form the interlayer dielectric layer, such as chemical vapor deposition process. The interlayer dielectric layer may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, for example Undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped Tetraethoxysilane (BTEOS). Its thickness is not limited to a certain value.

An interface layer 104 and a high-k dielectric layer 105 are successively formed on the surface of the fin.

Wherein, the interface layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer or other suitable thin film layers.

The thickness of the interface layer can be reasonably set according to actual process requirements, for example, the thickness of the interface layer can range from 5 angstroms to 10 angstroms.

Wherein the interface layer and the high-k dielectric layer both surround the suspension part and cover the horizontal plane of the base part.

The k value (dielectric constant) of the high-k dielectric layer is usually above 3.9, and its constituent materials include hafnium oxide, hafnium oxide silicon, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium oxide silicon, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide or aluminum oxide. A suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) can be used to form the high-k dielectric layer.

The thickness of the high-k dielectric layer ranges from 10 angstroms to 30 angstroms, and other suitable thicknesses can also be used.

Wherein the first work function layer is a PMOS work function layer, such as TiN.

Wherein, the second work function layer 108 is an NMOS work function layer, such as TiAl.

The conductive material can be selected from various metal materials commonly used in the field, such as W, etc., and is not limited to a certain one.

The parasitic channel can be eliminated in the semiconductor device of the present invention, and the performance and yield of the device can be improved.

Embodiment Three

The present invention also provides an electronic device, including the semiconductor device described in Embodiment 2, and the semiconductor device is prepared according to the method described in Embodiment 1.

The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

Among them, FIG. 3 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

Since the electronic device includes the semiconductor device described in Embodiment 2, and the semiconductor device is prepared according to the method described in Embodiment 1, parasitic channels can be eliminated and the performance of the device can be improved.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (11)

1. A method for manufacturing a semiconductor device, characterized in that the method comprises: A substrate is provided, the substrate includes an NMOS region and a PMOS region, fins and dummy gates surrounding the fins are formed on the NMOS region and the PMOS region, wherein the fins include Fin material layers and sacrificial layers stacked alternately upward; removing the dummy gate to form a groove and expose the fin; removing the sacrificial layer exposed in the groove to separate the fins into a suspension portion and a base portion; forming a first work function layer on a base portion of the fin in the NMOS region and on a surface of the fin in the PMOS region, wherein the first work function layer is a PMOS work function layer; forming a second work function layer on surfaces of the fins of the NMOS region and the PMOS region; The groove is filled with a conductive material to form a metal gate. 2. The manufacturing method according to claim 1, wherein the method for forming the first work function layer comprises: sequentially forming an interface layer, a gate dielectric layer and a first work function layer on the exposed surface of the fin; removing the first work function layer on the surface of the floating part of the fin in the NMOS region and retaining the first work function layer on the surface of the base part of the fin in the NMOS region. 3. The manufacturing method according to claim 2, wherein the method for removing the first work function layer on the surface of the suspended portion of the fin in the NMOS region comprises: depositing a mask layer to cover the grooves in the NMOS region and the PMOS region; patterning the mask layer to remove part of the mask layer in the NMOS region and expose at least the first work function layer on the surface of the suspended part of the fin; removing the first work function layer on the surface of the suspended portion of the fin in the exposed NMOS region. 4. The manufacturing method according to claim 3, further comprising the step of removing the remaining mask layer. 5. The manufacturing method according to claim 1, wherein an isolation material layer filling the gaps between the fins is further formed on the substrate, and the top of the isolation material layer is in contact with the fins. flush with the top of the base portion. 6 . The manufacturing method according to claim 5 , wherein the first work function layer is formed on a level plane of the base portion of the fin and on the isolation material layer. 7. A semiconductor device, characterized in that the semiconductor device comprises: a substrate comprising an NMOS region and a PMOS region; Fins formed in the NMOS region and the PMOS region, wherein the fins include a floating portion and a base portion that are spaced apart from each other in the region where the metal gate is formed; Metal gate structures, including: The first work function layer is located on the horizontal plane of the base part in the NMOS region and the PMOS region and on the surface of the suspension part in the PMOS region, wherein the first work function layer is a PMOS work function layer layer; a second work function layer on the first work function layer and on the surface of the floating portion of the fin in the NMOS region; A conductive material covers the fin and fills the space between the suspension portion and the base portion. 8. The semiconductor device according to claim 7, wherein an interface layer and a gate dielectric layer are further formed on the surface of the fin. 9. The semiconductor device according to claim 7, characterized in that, an isolation material layer filling the gap between the fins is further formed on the substrate, and the top of the isolation material layer is in contact with the fins. flush with the top of the base portion. 10. The semiconductor device according to claim 9, wherein the first work function layer is formed on the base portion of the fin and on the isolation material layer. 11. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 7-10.

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