CN107785374B

CN107785374B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN107785374B
Application number: CN201610719827.7A
Authority: CN
Inventors: 陈卓凡; 张翼英
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-08-24
Filing date: 2016-08-24
Publication date: 2020-11-10
Anticipated expiration: 2036-08-24
Also published as: CN107785374A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein a silicon-containing bump array is formed on the semiconductor substrate; and forming a current blocking layer on the top of each silicon-containing bump. The manufacturing method can prevent the top end of the silicon-containing bump from forming a conductive tip by forming the current blocking layer on the top end of the silicon-containing bump, further relatively increase the critical dimension of the conductive part on the top of the silicon-containing bump, reduce leakage current and improve the performance of devices such as a programming window, durability, data retention and the like. The semiconductor device and the electronic apparatus have high performance.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices. NAND flash memory is widely used in the field where read/write requirements are high due to its large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2GB, and the size has rapidly increased. Solid state disks based on NAND flash memory chips have been developed and used as storage devices in portable computers. Therefore, in recent years, NAND flash memories are widely used as storage devices in embedded systems, and also as storage devices in personal computer systems.

As the critical dimensions of NAND flash memory cells shrink below 20nm, the critical dimensions of the Floating Gate (FG) get smaller and smaller, while at the same time the thickness of the interpoly dielectric (IPD), such as ONO (oxide-nitride-oxide), cannot be reduced all the time, e.g. it must maintain a thickness of about 10nm, under both factors, as shown in the dashed area of fig. 1, the critical dimensions of the top of the floating gate are very limited (in other words, the top of the floating gate forms a tip), which results in a very large leakage current in the IPD during programming, which in turn results in a very small maximum threshold voltage in the programming window and an increase in electron traps (traps) in the IPD, which will have an impact on device performance, e.g. programmability, endurance, data retention, etc.

Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can reduce the electric leakage of the top area of the polysilicon of the device and improve the performance and the durability of the device.

In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a silicon-containing bump array is formed on the semiconductor substrate; and forming a current blocking layer on the top of each silicon-containing bump.

Further, the step of forming an array of silicon-containing bumps on the semiconductor substrate comprises: forming a silicon-containing material layer and a patterned hard mask layer on the semiconductor substrate; and etching the silicon-containing material layer by taking the patterned hard mask layer as a mask to form a silicon-containing bump array.

Further, the patterned hard mask layer includes an oxide.

Further, a nitride stop layer is formed between the silicon-containing material layer and the patterned hard mask layer.

Further, the step of forming a current blocking layer on top of each of the silicon-containing bumps comprises: forming a filling layer for filling the silicon-containing bump array gaps; removing part of the filling layer to expose the top end of the silicon-containing bump; and forming a current barrier layer on the top of the silicon-containing bump.

Further, the current blocking layer is nitride.

Further, a nitrogen-containing plasma treatment is performed on the top of the silicon-containing bump to form the nitride.

Further, the nitrogen-containing plasma treatment is N2 or NH3 plasma treatment.

Further, the filling layer of the gap is an isolation structure oxide.

Further, before forming a filling layer for filling the silicon-containing bump array gap, the method further comprises the following steps: and etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form a groove for forming an isolation structure.

Further, the silicon-containing projection array is a polysilicon floating gate array.

Further, the silicon-containing projection array is a silicon-containing fin array.

According to the manufacturing method of the semiconductor device, the current blocking layer is formed on the top end of the silicon-containing bump, so that the top end of the silicon-containing bump can be prevented from forming a conductive tip, the critical dimension of a conductive part on the top of the silicon-containing bump is relatively increased, the leakage current is reduced, and the performance of the device such as a programming window, durability and data retention is improved.

Another aspect of the present invention provides a semiconductor device fabricated by the above method, the semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, wherein a silicon-containing bump array is formed on the semiconductor substrate, and a current blocking layer is formed at the top end of each silicon-containing bump.

Further, a gate dielectric layer and a control gate layer are formed on the silicon-containing bumps.

According to the semiconductor device provided by the invention, the current barrier layer is formed on the top end of the silicon-containing bump, so that the top end of the silicon-containing bump can be prevented from forming a conductive tip, the critical dimension of the conductive part on the top of the silicon-containing bump is relatively increased, the leakage current is reduced, and the device performances such as a programming window, durability, data retention and the like are improved.

A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.

The electronic device provided by the invention has similar advantages due to the semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 shows an SEM illustration of a NAND device fabricated in the current process;

FIG. 2 shows a flow chart of steps of a method of fabricating a semiconductor device according to the present invention;

fig. 3A to 3G are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;

fig. 5 shows a cross-sectional view of a semiconductor device according to an embodiment of the invention;

fig. 6 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As mentioned above, in the NAND flash memory cell in the current process, the top of the floating gate is smaller and smaller due to the reduction of the critical dimension of the top of the floating gate and the thickness of the inter-polysilicon dielectric (IPD) which cannot be reduced all the time, so that the tip is formed gradually, and the leakage is increased. The invention provides a manufacturing method of a semiconductor device, which is used for manufacturing a semiconductor device such as NAND and comprising a silicon-containing bump array, can reduce the top leakage of the silicon-containing bump array such as a floating gate array and improve the device performance. As shown in fig. 2, the method includes: step 201: providing a semiconductor substrate, wherein a silicon-containing bump array is formed on the semiconductor substrate; step 202: and forming a current blocking layer on the top of each silicon-containing bump.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3G and fig. 4.

First, as shown in fig. 3A, a semiconductor substrate 300 is provided, a floating gate array 302 is formed on the semiconductor substrate 300, trenches forming isolation structures are formed in the semiconductor substrate 300, and an isolation material 305 is filled in the gaps between the floating gate arrays 302 and the trenches.

Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.

The floating gate array 302 may be formed on the semiconductor substrate 300 by a method commonly used in the art, such as first forming a layer of floating gate material on the semiconductor substrate 300, which may be a semiconductor material such as polysilicon, and formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). A patterned hard mask layer 304 is then formed on the layer of floating gate material, illustratively in this embodiment, the patterned hard mask layer 304 is an oxide, illustratively PEOX (plasma enhanced oxide), which may be formed by plasma chemical vapor deposition. After the hard mask layer 304 is formed, it may be patterned by a conventional photolithography process to define a floating gate pattern. Next, the floating gate material layer is etched using the patterned hard mask layer 304 as a mask, thereby forming a floating gate array 302 on the semiconductor substrate 300.

After the floating gate array 302 is formed, the semiconductor substrate 300 is continuously etched using the patterned hard mask layer 304 as a mask, thereby forming a trench for forming an isolation structure in the semiconductor substrate. The gap between the trench and the floating gate array 302 is then filled with an isolation material 305, which isolation material 305 may be selected to have a suitable filling capability. Illustratively, in the present embodiment, the isolation material 305 is an oxide, which may be formed by a filling process such as HARP (high aspect ratio process), HDP (high density plasma), and the like, and will not be described herein again.

It will be appreciated that, by processing the above structure, any other desired structural layer, such as the gate oxide layer 301, which is formed between the semiconductor substrate 300 and the floating gate 302, may also be formed as desired. The gate oxide layer 301 is illustratively a silicon oxide layer, which can be formed by a method such as a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

Further, in the present embodiment, a stopper layer 303 is also formed between the hard mask layer 304 and the floating gate 302, and the stopper layer 303 is illustratively a nitride such as silicon nitride, which can be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like, which serves as a CMP (chemical mechanical polishing) stopper when the isolation material planarization is subsequently performed.

It is also understood that the number of floating gates is determined according to the design requirements and specifications of the device, and in the present embodiment, only 6 floating gates are schematically shown, which does not represent the actual number of floating gates.

Next, as shown in fig. 3B, a planarization operation is performed to remove the portion above the nitride layer 303.

In forming the isolation material 305, it is inevitably formed on top of the hard mask layer, so that the portion above the silicon nitride layer 303 is removed by a planarization operation such as CMP (chemical mechanical planarization), mechanical polishing, etc., i.e., the portion above the nitride layer 303 of the filling layer 305 is removed by performing the planarization operation with the nitride layer 303 as a stop layer.

It will be appreciated that the oxide layer 304, which is the hard mask layer, is removed as well when the planarization operation is performed.

Next, as shown in fig. 3C and 3D, a portion of the isolation material 305 is removed to expose the top of the floating gate 302.

Specifically, a portion of the isolation material 305 is removed by performing an etch back or recess etch (receive) to expose the top of the floating gate 302. The etch back or recess etch (receive) includes a wet etch or dry etch process. The wet etching process includes wet etching processes such as phosphoric acid, hydrofluoric acid, etc., including but not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.

Illustratively, in the present implementation, first, as shown in fig. 3C, a part of the isolation material 305 and a part of the nitride layer 303 are removed by dry etching. The dry etching process parameters comprise: the etching gas comprises CF4, CHF3, etc., the flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column. The amount of etching back depends on the amount of the top of the floating gate to be exposed, or the thickness of the top of the floating gate to be formed with the current blocking layer. Illustratively, in the present embodiment, the top of the floating gate 302 is exposed by etch-back

I.e. on top of the floating gate 302

Is not surrounded by the isolation material 305.

Then, as shown in fig. 3D, the remaining nitride layer 303 is removed by wet etching. Illustratively, in this embodiment, a hot phosphoric acid wet etch process is used to remove the remaining nitride layer 303.

Next, as shown in fig. 3E, a current blocking layer 306 is formed on top of the floating gate.

Illustratively, in the present embodiment, the current blocking layer 306 is a nitride, such as silicon nitride. Which may be formed by performing a nitrogen-containing plasma treatment on the top of the floating gate. The current blocking layer 306 is formed by treating the top of the floating gate 302 with, for example, N2 or NH3 plasma to convert the top of the floating gate 302 from polysilicon to silicon nitride.

Next, as shown in fig. 3F, a portion of the isolation material 305 is removed to expose the floating gate 302, and an isolation structure 307 is formed in the semiconductor substrate.

Specifically, a portion of the isolation material 305 is removed by performing an etch back (etch back) or recess etch (re), leaving only a portion of the isolation material 305 located at the bottom of the floating gate and in the trench, thereby exposing a substantial portion of the floating gate 302, and an isolation structure 307 is formed in the semiconductor substrate for isolating the respective floating gates 302. The etch back or recess etch (receive) includes a wet etch or dry etch process. The wet etching process includes a wet etching process such as hydrofluoric acid, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Illustratively, the process parameters of the dry etching include: the etching gas comprises CF4, CHF3, etc., the flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.

It will be appreciated that in this embodiment, only a portion of the isolation material 305 is removed, while the portion of the isolation material at the bottom of the floating gate remains, which may limit the formation of a subsequently formed inter-gate dielectric layer (the dielectric layer between the floating gate and the control gate) from being formed in an excessively deep region.

Finally, as shown in fig. 3G, a gate dielectric layer 308 is formed on the current blocking layer 306.

Specifically, a gate dielectric layer 308 is first formed on the current blocking layer 306 by a common process such as PVD, CVD, ALD, or the like. Preferably, the gate dielectric layer 308 is an ONO (oxide-nitride-oxide) structure, which has both good interface properties and a high dielectric constant.

Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps before, during or after the above steps, such as the step shown in fig. 3G, and the step of forming a control gate and the like, which are included in the method for manufacturing the embodiment.

As shown in fig. 4, the method for manufacturing a semiconductor device according to this embodiment includes the following steps:

step 401: providing a semiconductor substrate, forming a floating gate array on the semiconductor substrate, forming grooves forming isolation structures in the semiconductor substrate, and filling isolation materials in gaps among the floating gate array and the grooves;

step 402: performing a planarization operation to remove a portion of the isolation material above the stop layer;

step 403: removing part of the isolation material to expose the top of the floating gate;

step 404: forming a current blocking layer on the top of the floating gate;

step 405: removing part of the isolation material layer to expose the top of the floating gate and forming an isolation structure in the semiconductor substrate;

step 406: and forming a gate dielectric layer and a control gate on the current blocking layer.

According to the manufacturing method of the semiconductor device, the current blocking layer is formed on the top end of the floating gate, so that a conductive tip can be prevented from being formed on the top end of the floating gate, the critical dimension of a conductive part on the top of the floating gate is relatively increased, leakage current is reduced, and the performance of the device such as a programming window, durability and data retention performance is improved.

It is understood that although the floating gate array structure of the NAND device is illustrated in the present embodiment, the fabrication method of the present invention is not limited thereto, and may be applied to other devices for preventing the leakage on the top of the silicon-containing bump array, such as silicon-containing fin devices.

When applied to silicon-containing fin devices, the gaps between the fins may be filled with an isolation material in the isolation structure during the above-described fabrication steps, which may also be, but is not limited to, the above-described fabrication steps

Example two

The present invention also provides a semiconductor device manufactured by the above method, as shown in fig. 5, the semiconductor device including: the semiconductor substrate 500 has isolation structures 501 formed in the semiconductor substrate 500, a gate oxide layer 502 formed on the semiconductor substrate between the isolation structures, a floating gate 503 formed on the gate oxide layer 502, a current blocking layer 504 formed on the top of the floating gate 503, and a gate dielectric layer 505 formed on the sidewall of the floating gate 503 and on the top of the current blocking layer 504.

Wherein the semiconductor substrate 500 may be at least one of the following mentioned materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In the present embodiment, the constituent material of the semiconductor substrate 500 is monocrystalline silicon.

The isolation structure 501 may be implemented by using various suitable isolation structures such as STI (shallow trench isolation), and the isolation material may be selected from oxide, nitride, and the like. Illustratively, in the present embodiment, the isolation material is an oxide.

The gate oxide layer 502 is illustratively a silicon oxide layer, which can be formed by a method such as a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like. The floating gate 503 is made of polysilicon material, and a pattern is defined by a commonly used photolithography and etching process.

The current blocking layer 504 is made of a suitable dielectric material, such as an oxide, nitride, or the like. In the present embodiment, the current blocking layer 504 is made of silicon nitride, for example.

The gate dielectric layer 505 may be made of any suitable material, and will not be described herein.

In the semiconductor device of the embodiment, the current blocking layer is formed on the top end of the floating gate, so that a conductive tip is prevented from being formed on the top end of the floating gate, the critical dimension of a conductive part on the top of the floating gate is relatively increased, the leakage current is reduced, and the device performance such as a programming window, durability and data retention performance is improved.

EXAMPLE III

Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor device comprises a semiconductor substrate, wherein a silicon-containing bump array is formed on the semiconductor substrate, and a current blocking layer is formed at the top end of each silicon-containing bump.

Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.

The silicon-containing bump array is illustratively a polysilicon floating gate array or a silicon-containing fin.

The current blocking layer is made of a suitable dielectric material, such as an oxide, nitride, or the like. In the present embodiment, the current blocking layer is made of silicon nitride, for example.

The electronic component may be any electronic component such as a discrete device and an integrated circuit.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

Fig. 6 shows an example of a mobile phone. The exterior of the cellular phone 600 is provided with a display portion 602, operation buttons 603, an external connection port 604, a speaker 605, a microphone 606, and the like, which are included in a housing 601.

According to the electronic device provided by the embodiment of the invention, the current barrier layer is formed on the top end of the silicon-containing bump of the semiconductor device, so that the top end of the silicon-containing bump can be prevented from forming a conductive tip, the critical dimension of the conductive part on the top of the silicon-containing bump is relatively increased, the leakage current is reduced, and the device performance such as a programming window, durability and data retention performance is improved. The electronic device also has similar advantages.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate, wherein a silicon-containing bump array and a groove for forming an isolation structure are formed on the semiconductor substrate;

forming an isolation structure oxide filling the silicon-containing bump array gaps and trenches for forming isolation structures;

removing part of the filling layer to expose the top end of the silicon-containing bump;

performing a plasma treatment on the top of the silicon-containing bump to form a current blocking layer on the top of the silicon-containing bump;

and removing part of the filling layer to expose the silicon-containing bump, and forming an isolation structure in the semiconductor substrate.

2. The method of claim 1, wherein the step of forming an array of silicon-containing bumps on the semiconductor substrate comprises:

forming a silicon-containing material layer and a patterned hard mask layer on the semiconductor substrate;

etching the silicon-containing material layer by taking the patterned hard mask layer as a mask to form a silicon-containing bump array;

and etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form a groove for forming an isolation structure.

3. The method of claim 2, wherein the patterned hard mask layer comprises an oxide.

4. The method of claim 3, wherein a nitride stop layer is further formed between the silicon-containing material layer and the patterned hard mask layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the current blocking layer is a nitride.

6. The method according to claim 5, wherein a nitrogen-containing plasma treatment is performed on the top of the silicon-containing bump to form the nitride.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the nitrogen-containing plasma treatment is N2 or NH3 plasma treatment.

8. The method of claim 1, wherein the silicon-containing raised array is a polysilicon floating gate array.

9. The method of claim 1, wherein the array of silicon-containing bumps is an array of silicon-containing fins.