CN111161773B - Low-frequency clock duty cycle calibration circuit, calibration method and memory - Google Patents
Low-frequency clock duty cycle calibration circuit, calibration method and memory Download PDFInfo
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Abstract
The invention provides a low-frequency clock duty ratio calibration circuit, a calibration method and a memory. The decoding circuit is utilized to convert the setting codes of the low-frequency working frequency of the reaction memory in the mode register setting circuit of the memory into output signals, and the capacitance value of the duty ratio detection circuit is regulated through the output signals so as to meet the detection requirement, thereby improving the clock duty ratio calibration quality. The invention can calibrate the clock duty ratio in time for the current clock frequency when working at low frequency, has high accuracy and high speed of calibration, and ensures the clock quality of the memory; and the memory mode is utilized to carry out self-charging, so that the structure is simple and the cost is lower.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-frequency clock duty cycle calibration circuit and a memory, and also relates to a low-frequency clock duty cycle calibration method.
Background
In the dynamic random access memory, the duty ratio reaches 50%, so that the utilization efficiency of the clock level can be improved to the greatest extent, and the normal operation and the optimal performance of the system are guaranteed. However, in actual operation, the duty ratio of the clock circuit often deviates from 50%, and the clock duty ratio calibration circuit is a circuit designed for the problem.
The existing clock duty ratio calibration circuit adopts the comparison of the charge and discharge time of the capacitor and the electric quantity. Because the memory can work at a lower working frequency, the capacitor is fixed during design, when the clock frequency is changed, the lower clock frequency has longer charge and discharge time, and the charge and discharge time is prolonged, so that the clock quality is reduced due to insufficient capacitor connected to the duty ratio detection circuit; furthermore, the delay chain at low frequencies needs to be connected with a longer progression to match the longer period, so that the whole calibration time is increased due to the increased clock frequency.
Ideally, no matter how high the clock frequency of the memory is, the duty ratio of the internal clock signal of the memory needs to be adjusted in a time as fast as possible, so as to ensure the correctness of the read data of the whole memory.
Disclosure of Invention
The invention aims to provide a low-frequency clock duty ratio calibration circuit and a memory, which solve the problems of overlong calibration time and reduced calibration quality under low frequency.
Another object of the present invention is to provide a low frequency clock duty cycle calibration method.
According to one aspect of the present invention, there is provided a low frequency clock duty cycle calibration circuit comprising:
A signal adjustment circuit for receiving and adjusting a first clock signal of the memory to generate a second clock signal;
A duty ratio detection unit connected to the signal adjustment circuit for detecting a duty ratio of the second clock signal and feeding back a detection result to the signal adjustment circuit, the duty ratio detection unit including a duty ratio detection circuit having an adjustable capacitor;
a mode register including a set code reflecting a clock frequency at which the memory operates at a low frequency;
and the decoding circuit is connected with the duty ratio detection circuit and the mode register setting circuit to adjust the capacitance value of the adjustable capacitor in the duty ratio detection circuit according to the setting code.
In an exemplary embodiment of the invention, the mode register is an MR6 mode register.
In one exemplary embodiment of the invention, the signal conditioning circuit includes a delay chain for receiving and delaying the first clock signal to generate a conditioned clock signal, and a clock generator for receiving the first clock signal and the conditioned clock signal to generate a second clock signal.
In an exemplary embodiment of the invention, the duty cycle detection unit further comprises a counter, the counter being connected to the delay chain; the duty cycle detection circuit includes:
the clock signal receiving end is connected with the signal adjusting circuit and is used for receiving the second clock signal;
A main circuit including the tunable capacitor for detecting a duty ratio of the second clock signal by charging and discharging the tunable capacitor;
a detection signal receiving terminal for receiving a detection enable signal to control the charge and discharge of the main circuit capacitance element;
The latch circuit is connected with the counter and is used for receiving an addition and subtraction instruction formed by the enabling times of the clock signals in the main circuit and outputting the addition and subtraction instruction to the counter so as to transfer the counting result to the delay chain.
In an exemplary embodiment of the present invention, the tunable capacitor includes a plurality of tunable capacitance circuits connected in parallel, each of the tunable capacitance circuits including a capacitance element and a switching element connected in series with the capacitance element.
In an exemplary embodiment of the present invention, the capacitive elements are MOS transistors, and a gate of each MOS transistor is connected to the switching element.
In an exemplary embodiment of the present invention, the switching element includes a PMOS transistor and an NMOS transistor connected in parallel, a control signal received by the PMOS transistor is complementary to a control signal received by the NMOS transistor, and on and off signals of the switching element come from the decoding circuit.
In an exemplary embodiment of the present invention, the decoding circuit includes: and the first decoding circuit is connected with the setting circuit of the MR6 mode register and the adjustable capacitor of the duty ratio detection circuit and is used for converting the setting code into an output signal so as to adjust the on and off of each switching element in the adjustable capacitor.
In an exemplary embodiment of the present invention, the decoding circuit further includes: and the second decoding circuit is connected with the setting circuit of the MR6 mode register and the delay chain and is used for converting the setting code into an output signal so as to adjust the initial setting value of the delay chain.
In an exemplary embodiment of the present invention, the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector in a setting circuit of the memory MR6 mode register.
According to another aspect of the invention there is provided a memory comprising a low frequency clock duty cycle calibration circuit as claimed in any one of the preceding claims.
According to still another aspect of the present invention, there is provided a low frequency clock duty cycle calibration method including:
Receiving a first clock signal of the memory by using a signal adjusting circuit and adjusting the first clock signal to generate a second clock signal;
the decoding circuit is utilized to convert the setting codes of the clock frequency of the MR6 mode register of the memory, which reflects the low-frequency operation of the memory, into output signals, and the output signals adjust the capacitance value of the duty ratio detection circuit;
detecting the duty ratio of the second clock signal by using the duty ratio detection circuit after the capacitance is adjusted;
the signal adjusting circuit adjusts the first clock signal according to the duty ratio detection result.
In one exemplary embodiment of the present invention, the signal conditioning circuit includes a delay chain and a clock generator, the first clock signal being delayed by the delay chain to generate a conditioned clock signal; the first clock signal is received and a clock signal is adjusted by the clock generator to generate the second clock signal.
In an exemplary embodiment of the invention, the capacitance value of the duty cycle detection circuit is adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
In an exemplary embodiment of the present invention, the number of capacitive elements of the duty ratio detection circuit is controlled by a switching element connected in series with the capacitive elements, and on and off signals of the switching element are from the decoding circuit.
In an exemplary embodiment of the present invention, the decoding circuit includes a first decoding circuit by which the setting code is converted into an output signal to control on and off of the switching element.
In an exemplary embodiment of the present invention, the decoding circuit further includes a second decoding circuit; the calibration method further comprises: and converting the setting code into an output signal through the second decoding circuit so as to adjust the initial setting value of the delay chain to be half of the current period value of the clock.
In an exemplary embodiment of the present invention, the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector circuit in the memory mode register setting circuit.
According to the low-frequency clock duty ratio calibration circuit, the capacitance required by the duty ratio detection circuit is determined according to the setting codes of the mode register response low-frequency clock frequency setting circuit, and the calibration speed is improved by adjusting the capacitance value of the duty ratio detection circuit. On the one hand, the charge quantity of the duty cycle detection circuit can be adjusted according to the requirement, so that the charge quantity required by identifying the duty cycle of the clock can be timely achieved, the duty cycle of the clock can be accurately calibrated, and the clock quality is ensured; on the other hand, the capacitor in the duty ratio detection circuit is directly adjusted through the setting code of the self-contained reaction clock frequency of the memory mode register, so that the calibration can be performed aiming at the current clock frequency, and the calibration accuracy is higher and the calibration speed is higher; and the memory mode is utilized to carry out self-charging, so that the structure is simple and the cost is low.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a diagram of a conventional clock duty cycle calibration circuit;
FIG. 2 is a set code for tCCD_L in DDR 4;
FIG. 3 is a diagram of a low frequency clock duty cycle calibration circuit according to the present invention;
FIG. 4 is a circuit diagram of duty cycle detection of the present invention;
FIG. 5 is a timing diagram of a duty cycle detection circuit according to the present invention;
FIG. 6 is a schematic diagram of the structure of the tunable capacitor of FIG. 4;
FIG. 7 is a truth table of a decoding circuit of the low frequency clock duty cycle calibration circuit of the present invention;
FIG. 8 is a first flowchart of a low frequency clock duty cycle calibration method according to the present invention;
FIG. 9 is a second flowchart of a low frequency clock duty cycle calibration method according to the present invention.
In the figure, 1, a delay chain; 2. a clock generator; 3. a duty cycle detection circuit; 4. a counter; 5. a decoding circuit; 6. MR6 mode register.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the related art, a conventional clock duty calibration circuit includes: the signal adjusting circuit is used for receiving a first clock signal of the memory and adjusting the first clock signal into a second clock signal so as to maintain the duty ratio within an ideal range; the duty ratio detection unit is used for detecting the duty ratio of the second clock signal and transmitting the detection result to the signal adjustment circuit so as to assist the signal adjustment circuit to adjust the first clock signal and ensure that the duty ratio reaches an ideal adjustment result.
As shown in fig. 1, the signal adjusting circuit includes a delay chain 1 and a clock generator 2, and delays a first clock signal of the memory by the delay chain 1 to generate a delayed adjusted clock signal; the clock generator 2 is used to receive the first clock signal and the adjustment clock signal and to generate a second clock signal. The duty ratio detection unit comprises a duty ratio detection circuit 3 and a counter 4, wherein the duty ratio detection circuit 3 is connected with a signal output end of the clock generator 2, receives a second clock signal and detects the duty ratio of the second clock signal, counts by the counter 4, and transmits a counting result to the delay chain 1 so that the delay chain 1 delays the first clock signal.
Since the operating frequency of the DDR memory varies, the frequency is often reduced to a low frequency range (the low frequency refers to a transmission rate lower than or equal to 2400 Mb/s), and when the clock frequency becomes low, the amount of charge stored in the delay chain of the high frequency circuit and the capacitor in the duty cycle detection circuit needs to be adjusted accordingly. For example, when the clock transmission rate is changed from 3200Mb/s to be lower than 1333Mb/s, and when the delay time of the delay chain is 6.25p, the clock period is changed from 625ps to be greater than or equal to 1.5ns, the period is prolonged, which means that the number of the delay chains is increased from 50 to at least 120, and the delay chains of the access circuit are obviously more than the original ones, so that the whole calibration time is prolonged due to the increase of the number of the delay chains.
Therefore, the embodiment of the invention provides a low-frequency clock duty ratio calibration circuit which can quickly and accurately calibrate the clock duty ratio of a memory working in a low-frequency range and is suitable for the duty ratio calibration of a DDR memory when the clock frequency is low. The DDR memory may be DDR4 or DDR3 or DDR2.
The low-frequency clock duty calibration circuit of the present embodiment includes: the device comprises a signal adjusting circuit, a duty ratio detecting unit, a setting circuit in a mode register and a decoding circuit. The signal adjusting circuit is used for receiving and adjusting a first clock signal of the memory to generate a second clock signal; the duty ratio detection unit is connected with the signal adjustment circuit and is used for detecting the duty ratio of the second clock signal and feeding back a detection result to the signal adjustment circuit, and comprises a duty ratio detection circuit with an adjustable capacitor; a mode register setting circuit including a setting code reflecting a low frequency operating frequency of the memory; the decoding circuit is connected with the duty ratio detection circuit and the setting circuit in the mode register to adjust the capacitance value of the adjustable capacitor in the duty ratio detection circuit according to the setting code.
The principle of the calibration circuit of the invention is as follows: when the clock is operated at a low frequency, the period becomes longer, the discharge time in a unit period becomes longer, and as is known from q=i×t=c×u, the amount of storable charge in the capacitor of the duty cycle detection circuit needs to be increased accordingly, and the calibration time becomes longer. Therefore, if the clock frequency is known in advance, the period can be known, the minimum charge amount required by the detection circuit for identifying the clock duty ratio can be determined, so that the capacitance value in the access circuit can be determined, the stored charge amount in the circuit can be timely increased, and the clock calibration circuit can be timely calibrated, so that the clock quality is ensured. In the DDR memory, the data in the setting circuit of the mode register can directly reflect the working frequency range of the memory, so that the frequency information can be timely obtained at the initial stage of frequency conversion, and the capacitance in the duty ratio detection circuit is timely adjusted to change the total capacitance of the detection circuit, thereby ensuring that the duty ratio of the detection result is quickly adjusted to 50% +/-1%.
The low frequency clock duty cycle calibration circuit according to the embodiment of the present invention is described in detail below:
In the present exemplary embodiment, the mode register is an MR6 mode register. The data contained in the setting circuit of the MR6 mode register can directly reflect the frequency range in which the memory operates. For example, the MR6 mode register in the DDR4JEDEC standard (DDR 4JEDEC SPEC) has a number of cycles set to meet the standard requirement according to the need of tccd_l at different clock frequencies, as shown in fig. 2, so that the capacitance value in the access detection circuit can be determined from the set codes of tccd_l to speed up the calibration quality of the clock duty cycle.
Therefore, the charge quantity of the duty ratio detection circuit can be timely adjusted according to the change of the working frequency, so that the charge quantity required by identifying the duty ratio of the clock can be achieved as soon as possible, the accurate calibration of the duty ratio during low-frequency working is met, and the clock quality is ensured. Meanwhile, the set code of the self-contained reaction clock frequency of the memory mode register can accurately reflect the current frequency, the capacitor in the duty ratio detection circuit can be directly adjusted according to the set code, a more accurate calibration result can be obtained, an additional circuit module is not required to be added, and the calibration accuracy and speed are improved.
In this exemplary embodiment, as shown in fig. 3, the signal adjustment circuit may include a delay chain 1 and a clock generator 2, where the delay chain 1 receives and delays a first clock signal to obtain an adjusted clock signal, and a signal input terminal of the clock generator 2 receives the first clock signal and the adjusted clock signal to generate a second clock signal.
The clock duty ratio detection circuit 3 of the present invention may take various forms, for example, in the present exemplary embodiment, the duty ratio detection circuit diagram and the timing diagram are shown in fig. 4 and 5, the circuit is a circuit that is configured as a mirror image as a whole, and in the present exemplary embodiment, the duty ratio detection circuit 3 includes a clock signal receiving terminal, a main circuit, a detection signal receiving terminal, and a latch circuit, as shown in fig. 4, and is a circuit that is configured as a mirror image. The clock signal receiving end is connected with the signal output end of the clock generator and is used for receiving complementary signals MCLK and/MCLK to be detected, and the complementary signals are converted by a second clock signal generated by the clock generator. The main circuit is used for detecting the duty ratio of the second clock signal by charging and discharging the capacitor, the capacitor of the main circuit is an adjustable capacitor, and the capacitance value can be adjusted according to the set code of the low-frequency working frequency of the reaction memory in the setting circuit. The detection signal receiving end receives the detection enable signal EN to control the charging and discharging of the main circuit capacitance element. The latch circuit is connected with the counter, receives the addition and subtraction instructions INC and DEC formed by the enabling times of the MCLK and/or MCLK signals in the main circuit, and outputs UP and DN signals to be connected with the counter. The duty ratio calibration circuit also comprises a counter, the UP and DN signals output by the counter of the latch circuit are sent to the counter, the counter counts the UP and DN signals and sends the counting result to the delay chain, so that the delay chain can determine the number of delay units of the access circuit.
All signals of the detection circuit can be transmitted through the MOS tube, and when the working level changes, the corresponding signals can be connected with or disconnected from the circuit. For example, as shown in fig. 4, the clock signal receiving end includes an NMOS transistor for conducting the clock signals MCLK and/MCLK to the main circuit at the high level, and the detection signal receiving end includes a PMOS transistor for conducting the detection enable signal EN to the main circuit at the high level.
In the present exemplary embodiment, the tunable capacitor may include a plurality of tunable capacitance circuits connected in parallel, each of the tunable capacitance circuits including a capacitance element and a switching element connected in series with the capacitance element. The number of the capacitive elements connected to the detection circuit is controlled by controlling the on and off of the switching element, so that the capacitance value of the detection circuit is adjusted.
The adjustable capacitor can simultaneously comprise an unadjustable capacitance circuit and a plurality of adjustable capacitance circuits, so that the complexity of a circuit is reduced and the adjustment cost is reduced on the premise of meeting the adjustment requirement. The adjustable capacitor circuit can also only comprise a plurality of adjustable capacitor circuits, and the adjustment range is larger. Through the structure of this implementation adjustment capacitance, can directly design a plurality of capacitive elements at the beginning of test circuit design, according to the change of operating frequency adjust the number of incorporation circuit can, both can realize the adjustment of capacitance, can satisfy the regulation demand of bigger scope or more accuracy again. Even if the capacitor element fails, other capacitor elements can be used as the substitute, the whole circuit structure is not required to be replaced, and the cost is reduced.
For example, in fig. 6, the main circuit of the detection circuit includes a fixed capacitor M0 and three capacitive elements M1, M2 and M3 connected in parallel with the fixed capacitor (a and B in fig. 4 correspond to a and B in fig. 6), and a switching element is connected in series to each of M1, M2 and M3. The fixed capacitor M0 provides a basic capacitance value, three capacitive elements M1, M2, M3 are used for adjustment, and four capacitors are matched to realize adjustment of the total capacitance value.
This embodiment incorporates three adjustable capacitive circuits, while in other exemplary embodiments more adjustable capacitive circuits may be incorporated, or there may be only one or two adjustable capacitive circuits, each including a capacitive element and a switching element in series therewith. The plurality of adjustable capacitance circuits can adjust the capacitance of the detection circuit over a larger range to accommodate lower clock frequencies. Each capacitive element is independently controlled by a respective switching element, and different capacitive requirements can be achieved for more accurate calibration of the duty cycle. The capacitance values of the respective capacitance elements may be the same or different, and those skilled in the art may perform various combinations according to the adjustment accuracy and the range, which is not particularly limited by the present invention. The present invention is not limited to the size and number of capacitive elements.
In this exemplary embodiment, each capacitor element may be a MOS tube, which may be a PMOS tube, or may be an NMOS tube, where a gate of each MOS tube is connected to a switching element, and the switching element controls access of the MOS tube, and the MOS tube accessed to the detection circuit charges or discharges at the gate voltage, so as to implement duty ratio detection. In this exemplary embodiment, the MOS transistor may be a PMOS transistor or an NMOS transistor as long as it is matched with the circuit polarity. As shown in the figure, in the detection circuit of this embodiment, the fixed capacitor and the adjustable capacitor are PMOS transistors, the source and the drain of each capacitor are connected to the power supply terminal, and the gate is connected to the main circuit. Of course, the capacitive element may also be a normal capacitance.
In this exemplary embodiment, the switching element of the adjustable capacitor is formed by connecting a PMOS tube and an NMOS tube in parallel, two control ends of the PMOS tube and the NMOS tube respectively receive complementary switching control signals Ctl1 and/Ctl 1, one end of the PMOS tube and one end of the NMOS tube connected in parallel are connected to the adjustable capacitor, and the other end is connected to the main circuit, so as to realize charging or discharging of the capacitor when different level signals are conducted. The Ctl1 and/Ctl 1 signals come from the clock frequency detection unit, and the clock frequency detection unit generates control signals Ctl1 and/Ctl 1 to control the on and off of the switching element through the acquired setting codes, so that the capacitance value of the access detection circuit is changed.
In the present exemplary embodiment, the decoding circuit 5 may include a first decoding circuit that connects the MR6 mode register 6 setting circuit and the adjustable capacitor of the duty ratio detection circuit 3, acquires the setting code through the first decoding circuit, and converts the binary code thereof into an output signal for adjusting the on and off of each switching element in the adjustable capacitor.
In the present exemplary embodiment, the decoding circuit 5 may further include a second decoding circuit connected to the MR6 mode register 6 setting circuit and the delay chain 1 for converting the setting code into a pulse output signal to adjust an initial setting value of the delay chain. The working period of the memory can be acquired from the setting code of the tCCD_L, and the initial setting value of the delay chain is adjusted, so that the complicated adjusting process can be reduced, and the calibration time is further shortened.
In view of the simplicity of the structure, the first decoding circuit and the second decoding circuit of the present embodiment are each derived from a multiple-input multiple-output selector (3-8 decoder) in the existing MR6 mode register setting circuit of the memory, and the switching element adjustment signal and the delay chain adjustment signal are simultaneously generated by the selector. Fig. 7 is a truth table applied to the decoding circuit of the present example. Of course, those skilled in the art will recognize that other decoding circuits may be used to decode the set codes.
The embodiment of the invention also provides a memory, which comprises any one of the low-frequency clock duty ratio calibration circuits. The clock of the memory can always ensure that the duty ratio is 50+/-1%, so that the accuracy of data reading is higher.
The embodiment of the invention also provides a low-frequency clock duty cycle calibration method, referring to fig. 8, comprising the following steps:
Step S110, a signal adjusting circuit is utilized to receive a first clock signal of a memory and adjust the first clock signal to generate a second clock signal;
Step S210, the decoding circuit 5 is utilized to convert the setting codes of the low-frequency working frequency of the reaction memory in the MR6 mode register 6 setting circuit of the memory into output signals, and the capacitance value of the duty ratio detection circuit is regulated through the output signals;
Step S310, detecting the duty ratio of the second clock signal by using a duty ratio detection circuit after the capacitance is adjusted;
In step S410, the signal adjustment circuit performs the adjustment on the first clock signal according to the duty cycle detection result.
Through the steps, the setting code capable of directly reflecting the current low-frequency working frequency of the memory is obtained from the data of the MR6 mode register setting circuit of the memory, so that the capacitance in the duty ratio detection circuit is timely adjusted according to the setting code, the total capacitance of the detection circuit is increased, the detection requirement is met, and the duty ratio is adjusted to 50% +/-1% as soon as possible.
In step S110 of the present exemplary embodiment, the signal adjustment circuit may include a delay chain 1 and a clock generator 2, delaying a first clock signal by the delay chain 1 to generate an adjustment clock signal; the first clock signal is received by the clock generator 2 and the clock signal is adjusted to generate the second clock signal.
In step S210 of the present exemplary embodiment, the capacitance value of the duty cycle detection circuit 3 is adjustable, and the duty cycle detection circuit 3 may have various forms, and the capacitance value thereof may be adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
Further, whether or not the capacitive elements are connected in parallel to the duty ratio detection circuit is controlled by switching elements connected in series with the respective capacitive elements, and on and off signals of the switching elements come from the clock frequency detection unit.
Referring to fig. 9, in step S210 of the present exemplary embodiment, the clock frequency detecting unit includes a first decoding circuit by which a setting code is converted into an output signal to control on and off of the switching element.
The exemplary embodiment further includes step S510 of converting the setting code into an output signal by the second decoding circuit to adjust an initial setting value of the delay chain to half (T/2) of a current period value of the clock. The second decoding circuit belongs to the clock frequency detection unit. The T/2 is used as the initial value of the delay chain, so that the problem that the delay chain needs to be increased step by step to lengthen the whole calibration period is solved, the adjustment time can be shortened, and the duty ratio can be adjusted to about 50% as soon as possible. Of course, the initial value may be a value close to T/2.
Therefore, besides the delay accuracy is improved by increasing the capacitance value of the detection circuit, the delay speed is also improved, and the calibration quality of the calibration circuit is improved in two aspects.
Further, the first decoding circuit and the second decoding circuit each employ a multiple-input multiple-output selector circuit in the existing MR6 mode register setting circuit, and the switching element adjustment signal and the delay chain initial value adjustment signal are simultaneously generated by the selector circuit.
The circuit structure in this embodiment refers to the related description in the calibration circuit, and will not be described herein.
In the method of the invention, the first clock signal is regulated by the signal regulating circuit or the duty ratio is detected by the duty ratio detecting circuit, and the whole duty ratio calibration is a continuous cyclic process. Correspondingly, the work of the decoding circuit is continuously carried out, once the working frequency of the memory is reduced to low frequency, the decoding circuit can adjust the capacitance value of the duty ratio detection circuit according to the set codes, or adjust the initial value of the delay chain at the same time, so that the whole cycle calibration process always achieves higher quality, and the clock quality of the memory is always kept stable.
It will be appreciated by those skilled in the art that since the calibration process is performed cyclically and certain steps may be performed in any order, the above steps are described for convenience of description and are not the only limitations of the implementation process of the method of the present invention. For example, in addition to the above-described implementation of the steps, the signal adjustment circuit adjusts the clock signal and the decoding circuit adjusts the capacitance value simultaneously, or in a permuted order. The first decoding circuit can adjust the capacitance value and the second decoding circuit can adjust the initial value of the delay chain at the same time or change the sequence.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (13)
1. A low frequency clock duty cycle calibration circuit, comprising:
A signal adjustment circuit for receiving and adjusting a first clock signal of the memory to generate a second clock signal;
A duty ratio detection unit connected to the signal adjustment circuit for detecting a duty ratio of the second clock signal and feeding back a detection result to the signal adjustment circuit, the duty ratio detection unit including a duty ratio detection circuit having an adjustable capacitor;
A mode register including a set code reflecting a clock frequency of the memory low frequency operation, the mode register being an MR6 mode register;
the decoding circuit is connected with the duty ratio detection circuit and the mode register to adjust the capacitance value of an adjustable capacitor in the duty ratio detection circuit according to the setting code;
The signal adjustment circuit comprises a delay chain and a clock generator, wherein the delay chain is used for receiving and delaying the first clock signal to generate an adjustment clock signal, and the clock generator is used for receiving the first clock signal and the adjustment clock signal to generate a second clock signal;
the duty ratio detection unit further comprises a counter, and the counter is connected with the delay chain; the duty ratio detection circuit is a mirror image setting circuit, and comprises:
The clock signal receiving end is connected with the signal output end of the clock generator and is used for receiving the second clock signal;
A main circuit including the tunable capacitor for detecting a duty ratio of the second clock signal by charging and discharging the tunable capacitor;
a detection signal receiving terminal for receiving a detection enable signal to control the charge and discharge of the main circuit capacitance element;
the latch circuit is connected with the counter and is used for receiving an addition and subtraction instruction formed by the enabling times of the clock signal in the main circuit and outputting a pulse signal to the counter so as to transmit a counting result to the delay chain.
2. The low frequency clock duty cycle calibration circuit of claim 1, wherein the adjustable capacitor comprises a plurality of adjustable capacitance circuits connected in parallel, each of the adjustable capacitance circuits comprising a capacitance element and a switching element in series with the capacitance element.
3. The low frequency clock duty cycle calibration circuit of claim 2, wherein the capacitive elements are MOS transistors, a gate of each MOS transistor being connected to the switching element.
4. The low frequency clock duty cycle calibration circuit of claim 3, wherein the switching element comprises a PMOS transistor and an NMOS transistor connected in parallel, the control signal received by the PMOS transistor is complementary to the control signal received by the NMOS transistor, and the on and off signals of the switching element are from the decoding circuit.
5. The low frequency clock duty cycle calibration circuit of claim 1, wherein the decoding circuit comprises:
And the first decoding circuit is connected with the setting circuit of the MR6 mode register and the adjustable capacitor of the duty ratio detection circuit and is used for converting the setting code into an output signal so as to adjust the on and off of each switching element in the adjustable capacitor.
6. The low frequency clock duty cycle calibration circuit of claim 1, wherein the decoding circuit comprises:
and the second decoding circuit is connected with the setting circuit of the MR6 mode register and the delay chain and is used for converting the setting code into an output signal so as to adjust the initial setting value of the delay chain.
7. The low frequency clock duty cycle calibration circuit of claim 5 or 6, wherein either the first decoding circuit or the second decoding circuit employs a multiple-input multiple-output selector circuit in the MR6 mode register setting circuit.
8. A memory comprising the low frequency clock duty cycle calibration circuit of any one of claims 1 to 7.
9. A method for calibrating a duty cycle of a low frequency clock, comprising:
Receiving a first clock signal of the memory by using a signal adjusting circuit and adjusting the first clock signal to generate a second clock signal;
the method comprises the steps that a decoding circuit is utilized to convert setting codes of clock frequency of low-frequency work of a reaction memory in a setting circuit of an MR6 mode register of the memory into output signals, and the capacitance value of a duty ratio detection circuit is adjusted through the output signals;
detecting the duty ratio of the second clock signal by using the duty ratio detection circuit after the capacitance is adjusted;
The signal adjusting circuit adjusts the first clock signal according to the duty ratio detection result;
the signal adjusting circuit comprises a delay chain and a clock generator, and delays the first clock signal through the delay chain to generate an adjusting clock signal; receiving, by the clock generator, the first clock signal and adjusting the clock signal to generate the second clock signal;
the decoding circuit further comprises a second decoding circuit; the calibration method further comprises:
And converting the setting code into an output signal through the second decoding circuit so as to adjust the initial setting value of the delay chain to be half of the current period value of the clock.
10. The method according to claim 9, wherein the capacitance value of the duty cycle detection circuit is adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
11. The method according to claim 10, wherein the number of the capacitive elements connected in parallel to the duty detection circuit is controlled by a switching element connected in series with the capacitive elements, and the on and off signals of the switching element are from the decoding circuit.
12. The clock duty cycle calibration method of claim 11, wherein the decoding circuit further comprises a first decoding circuit by which the setting code is converted into an output signal to control on and off of the switching element.
13. The method of claim 12, wherein the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector circuit in the memory MR6 mode register setting circuit.
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| CN114420187B (en) * | 2020-10-28 | 2023-09-08 | 长鑫存储技术有限公司 | Calibration circuit, memory and calibration method |
| CN113364434B (en) * | 2021-06-23 | 2024-03-01 | 中国科学院微电子研究所 | Duty cycle calibration circuit and method |
| CN115941401A (en) * | 2022-10-27 | 2023-04-07 | 长鑫存储技术有限公司 | Data receiving circuit and semiconductor device |
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| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| CN209199607U (en) * | 2018-11-08 | 2019-08-02 | 长鑫存储技术有限公司 | Low-frequency clock duty-ratio calibrating circuit and memory |
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| JP4086855B2 (en) * | 2005-04-15 | 2008-05-14 | エルピーダメモリ株式会社 | Duty detection circuit and control method thereof |
| US7298193B2 (en) * | 2006-03-16 | 2007-11-20 | International Business Machines Corporation | Methods and arrangements to adjust a duty cycle |
| KR20090121469A (en) * | 2008-05-22 | 2009-11-26 | 주식회사 하이닉스반도체 | Semiconductor memory device |
| KR101024261B1 (en) * | 2008-11-10 | 2011-03-29 | 주식회사 하이닉스반도체 | Duty ratio correction circuit and delay locked loop circuit including the same |
| KR101016555B1 (en) * | 2008-12-09 | 2011-02-24 | 숭실대학교산학협력단 | Duty cycle and phase error correction circuit arrangement and method |
| KR20170045768A (en) * | 2015-10-19 | 2017-04-28 | 에스케이하이닉스 주식회사 | Duty cycle detection circuit |
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| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| CN209199607U (en) * | 2018-11-08 | 2019-08-02 | 长鑫存储技术有限公司 | Low-frequency clock duty-ratio calibrating circuit and memory |
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