CN111161784B - Full-band clock duty cycle calibration circuit, calibration method and memory - Google Patents
Full-band clock duty cycle calibration circuit, calibration method and memory Download PDFInfo
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Abstract
The invention provides a full-band clock duty cycle calibration circuit, a calibration method and a memory. The decoding circuit is utilized to convert the setting codes of the full-band working frequency of the reaction memory in the mode register setting circuit of the memory into output signals, and the capacitance value of the duty ratio detection circuit is regulated through the output signals so as to meet the detection requirement, thereby improving the clock duty ratio calibration quality. The invention can calibrate the clock duty ratio in time for the current clock frequency when working in the full frequency band, has high accuracy and high speed of calibration, ensures the clock quality of the memory, and has simple structure and lower cost by utilizing the self-powered circuit of the memory mode.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a full-band clock duty cycle calibration circuit and a memory, and also relates to a full-band clock duty cycle calibration method.
Background
In the dynamic random access memory, the duty ratio reaches 50%, so that the utilization efficiency of the clock level can be improved to the greatest extent, and the normal operation and the optimal performance of the system are guaranteed. However, in actual operation, the duty ratio of the clock circuit often deviates from 50%, and the clock duty ratio calibration circuit is a circuit designed for the problem.
The existing clock duty ratio calibration circuit adopts the comparison of the charge and discharge time of the capacitor and the electric quantity. Because the memory may work at a higher or lower working frequency, the capacitor is fixed during design, when the clock frequency is changed, the higher clock frequency has shorter charge and discharge time, the lower clock frequency has longer charge and discharge time, and the lower clock frequency has lower clock quality and full frequency band due to insufficient capacitor connected to the clock duty detection circuit.
Ideally, no matter how high the clock frequency of the memory is, the duty ratio of the internal clock signal of the memory needs to be adjusted in a time as fast as possible, so as to ensure the correctness of the read data of the whole memory.
Disclosure of Invention
The invention aims to provide a full-band clock duty cycle calibration circuit and a memory, which solve the problems of overlong calibration time and reduced calibration quality under full-band rate.
Another object of the present invention is to provide a full band clock duty cycle calibration method.
According to one aspect of the present invention, there is provided a full band clock duty cycle calibration circuit comprising:
a signal adjustment circuit for receiving and adjusting a first clock signal of the memory to generate a second clock signal;
A duty ratio detection unit connected to the signal adjustment circuit for detecting a duty ratio of the second clock signal and feeding back a detection result to the signal adjustment circuit, the duty ratio detection unit including a duty ratio detection circuit having an adjustable capacitor;
A mode register including a set code reflecting the clock frequency of the full band operation of the memory;
and the decoding circuit is connected with the duty ratio detection circuit and the mode register setting circuit to adjust the capacitance value of the adjustable capacitor in the duty ratio detection circuit according to the setting code.
In an exemplary embodiment of the invention, the mode registers include an MR6 mode register and an MR2 mode register.
In one exemplary embodiment of the invention, the signal conditioning circuit comprises a first delay chain, a second delay chain, a third delay chain and a clock generator, wherein the first delay chain is used for receiving and delaying the first clock signal to generate a first conditioning clock signal, the second delay chain is used for receiving and delaying the first conditioning clock signal to generate a second conditioning clock signal, the third delay chain is used for receiving and delaying the second conditioning clock signal to generate a third conditioning clock signal, or the clock generator is used for receiving the first clock signal and the third conditioning clock signal to generate a second clock signal.
In an exemplary embodiment of the present invention, the duty ratio detection unit further includes a first counter, a second counter, and a third counter, the three counters and the three delay chains are connected in one-to-one correspondence, and the duty ratio detection circuit includes:
the clock signal receiving end is connected with the signal adjusting circuit and is used for receiving the second clock signal;
a main circuit including the tunable capacitor for detecting a duty ratio of the second clock signal by charging and discharging the tunable capacitor;
A detection signal receiving terminal for receiving a detection enable signal to control the charge and discharge of the main circuit capacitance element;
And the latch circuit is connected with the three counters and is used for receiving an addition and subtraction instruction formed by the enabling times of the clock signals in the main circuit and outputting the addition and subtraction instruction to the three counters so as to transfer the counting result to the corresponding delay chain.
In an exemplary embodiment of the present invention, the tunable capacitor includes a plurality of tunable capacitance circuits connected in parallel, each of the tunable capacitance circuits including a capacitance element and a switching element connected in series with the capacitance element.
In an exemplary embodiment of the present invention, the capacitive elements are MOS transistors, and a gate of each MOS transistor is connected to the switching element.
In an exemplary embodiment of the present invention, the switching element includes a PMOS transistor and an NMOS transistor connected in parallel, a control signal received by the PMOS transistor is complementary to a control signal received by the NMOS transistor, and on and off signals of the switching element come from the decoding circuit.
In an exemplary embodiment of the invention, the decoding circuit comprises a first decoding circuit, an adjustable capacitor, a second decoding circuit and a third decoding circuit, wherein the first decoding circuit is respectively connected with the setting circuit of the MR6 mode register, the setting circuit of the MR2 mode register and the duty ratio detection circuit and is used for converting the setting codes into output signals so as to adjust the on and off states of all switching elements in the adjustable capacitor.
In an exemplary embodiment of the present invention, the decoding circuit further includes a second decoding circuit connected to the setting circuit of the MR6 mode register, the setting circuit of the MR2 mode register, the first delay chain, the second delay chain, and the third delay chain, respectively, for converting the setting codes into output signals to adjust initial setting values of the three delay chains.
In an exemplary embodiment of the present invention, the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector in a setting circuit of the memory MR6 mode register and MR2 mode register.
According to another aspect of the invention there is provided a memory comprising a full band clock duty cycle calibration circuit as claimed in any one of the preceding claims.
According to still another aspect of the present invention, there is provided a full band clock duty cycle calibration method, comprising:
receiving a first clock signal of the memory by using a signal adjusting circuit and adjusting the first clock signal to generate a second clock signal;
The decoding circuit is utilized to convert the setting codes of the clock frequency of the full-frequency or high-frequency work of the reaction memory in the setting circuit of the MR6 mode register or the MR2 mode register of the memory into output signals, and the output signals adjust the capacitance value of the duty ratio detection circuit;
Detecting the duty ratio of the second clock signal by using the duty ratio detection circuit after the capacitance is adjusted;
The signal adjusting circuit adjusts the first clock signal according to the duty ratio detection result.
In one exemplary embodiment of the invention, the signal conditioning circuit comprises a first delay chain, a second delay chain, a third delay chain and a clock generator, wherein the first delay chain delays the first clock signal to generate a first conditioning clock signal, the second delay chain delays the first conditioning clock signal to generate a second conditioning clock signal, the third delay chain delays the second conditioning clock signal to generate a third conditioning clock signal, or the clock generator receives the first clock signal and the third conditioning clock signal to generate the second clock signal.
In an exemplary embodiment of the invention, the capacitance value of the duty cycle detection circuit is adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
In an exemplary embodiment of the present invention, the number of capacitive elements of the duty ratio detection circuit is controlled by a switching element connected in series with the capacitive elements, and on and off signals of the switching element are from the decoding circuit.
In an exemplary embodiment of the present invention, the decoding circuit includes a first decoding circuit by which the setting code is converted into an output signal to control on and off of the switching element.
In an exemplary embodiment of the invention, the decoding circuit further comprises a second decoding circuit, and the calibration method further comprises converting the setting codes into output signals by the second decoding circuit to adjust initial setting values of the three delay chains to be half of the current period value of the clock.
In an exemplary embodiment of the present invention, the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector circuit in the memory MR6 mode register and MR2 mode register setting circuit.
According to the full-band clock duty ratio calibration circuit, the capacity required by the duty ratio detection circuit is determined according to the setting codes of the mode register response full-band clock frequency setting circuit, and the calibration speed is improved by adjusting the capacity value of the duty ratio detection circuit. On one hand, the charge quantity of the duty ratio detection circuit can be adjusted according to the requirement, so that the charge quantity required by identifying the clock duty ratio can be timely achieved, the clock duty ratio can be accurately calibrated, the clock quality is ensured, on the other hand, the capacitor in the duty ratio detection circuit is directly adjusted through the setting code of the self-contained reaction clock frequency of the memory mode register, the current clock frequency can be calibrated, the calibration accuracy is higher and the calibration speed is higher, and the memory mode self-powered circuit is utilized, so that the structure is simple, and the cost is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a diagram of a conventional clock duty cycle calibration circuit;
FIG. 2 is a set code of CWL in DDR 4;
FIG. 3 is a set code for tCCD_L in DDR 4;
FIG. 4 is a diagram of a full band clock duty cycle calibration circuit according to the present invention;
FIG. 5 is a circuit diagram of duty cycle detection of the present invention;
FIG. 6 is a timing diagram of a duty cycle detection circuit according to the present invention;
FIG. 7 is a schematic diagram of the structure of the tunable capacitor of FIG. 5;
FIG. 8 is a first flowchart of a full band clock duty cycle calibration method according to the present invention;
FIG. 9 is a second flowchart of a full band clock duty cycle calibration method according to the present invention.
In the figure, 1-1 part of a first delay chain, 1-2 parts of a second delay chain, 1-3 parts of a third delay chain, 2 parts of a clock generator, 3 parts of a duty ratio detection circuit, 4-1 parts of a first counter, 4-2 parts of a second counter, 4-3 parts of a third counter, 5 parts of a decoding circuit, 6 parts of an MR2 mode register and 7 parts of an MR6 mode register.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the related art, the conventional clock duty ratio calibration circuit comprises a signal adjustment circuit and a duty ratio detection unit, wherein the signal adjustment circuit is used for receiving a first clock signal of a memory and adjusting the first clock signal into a second clock signal so as to maintain the duty ratio within an ideal range, and the duty ratio detection unit is used for detecting the duty ratio of the second clock signal and transmitting the detection result to the signal adjustment circuit so as to assist the signal adjustment circuit to adjust the first clock signal and ensure that the duty ratio reaches the ideal adjustment result.
As shown in fig. 1, the signal adjusting circuit comprises a delay chain 1 and a clock generator 2, wherein the delay chain 1 is used for delaying a first clock signal of a memory to generate a delayed adjusting clock signal, and the clock generator 2 is used for receiving the first clock signal and the adjusting clock signal and generating a second clock signal. The duty ratio detection unit comprises a duty ratio detection circuit 3 and a counter 4, wherein the duty ratio detection circuit 3 is connected with a signal output end of the clock generator 2, receives a second clock signal and detects the duty ratio of the second clock signal, counts by the counter 4, and transmits a counting result to the delay chain 1 so that the delay chain 1 delays the first clock signal.
When the operating frequency of the DDR memory is increased to a high frequency range (the high frequency finger transmission rate referred to by the present invention is greater than 2400 Mb/s), corresponding adjustments need to be made to the amount of charge stored in the capacitor of the delay chain and the duty cycle detection circuit of the low frequency circuit. For example, in the high frequency range, when the clock transmission rate is changed from 1600Mb/s to 3200Mb/s, the final constant duty ratio is 50% ± 1%, and when the delay time of the delay chain is 6.25p, the clock period is changed from 1.25ns to 625ps, the period is shortened, which means that the number of delay chains is reduced from 100 to about 50, and the delay chains of the access circuit are obviously much less than the original delay chains, so that the whole calibration time is inaccurate due to the change of the number of delay chains.
When the operating frequency of the DDR memory is reduced to a low frequency range (the low frequency referred to by the present invention means that the transmission rate is lower than or equal to 2400 Mb/s), corresponding adjustments are required to be made for the amount of charge stored in the capacitor of the delay chain and the duty cycle detection circuit of the high frequency circuit. For example, when the clock transmission rate is changed from 3200Mb/s to be lower than 1333Mb/s, and when the delay time of the delay chain is 6.25p, the clock period is changed from 625ps to be greater than or equal to 1.5ns, the period is prolonged, which means that the number of the delay chains is increased from 50 to at least 120, and the delay chains of the access circuit are obviously more than the original ones, so that the whole calibration time is prolonged due to the increase of the number of the delay chains.
Therefore, the embodiment of the invention provides a full-band clock duty ratio calibration circuit which can quickly and accurately calibrate the clock duty ratio of a memory working in a high-frequency range and a low-frequency range and is suitable for calibrating the duty ratio of a DDR memory when the clock frequency is high or low. The DDR memory may be DDR4 or DDR3 or DDR2.
The full-band clock duty cycle calibration circuit of the present embodiment includes a signal adjustment circuit, a duty cycle detection unit, a mode register setting circuit, and a decoding circuit. The signal adjusting circuit is used for receiving and adjusting a first clock signal of the memory to generate a second clock signal, the duty ratio detecting unit is connected with the signal adjusting circuit and used for detecting the duty ratio of the second clock signal and feeding back a detection result to the signal adjusting circuit, the duty ratio detecting unit comprises a duty ratio detecting circuit with an adjustable capacitor, the mode register setting circuit comprises a setting code for reflecting the full-band working frequency of the memory, and the decoding circuit is connected with the duty ratio detecting circuit and the setting circuit in the mode register to adjust the capacitance value of the adjustable capacitor in the duty ratio detecting circuit according to the setting code.
The principle of the calibration circuit is that when the clock works at high frequency, the period is shortened, the discharge time in the unit period is shortened, as can be seen from Q=I×T=C×U, the storable charge quantity of the capacitor in the duty ratio detection circuit is correspondingly reduced, and once the charge quantity is redundant, the detection time is prolonged, so that the calibration time is prolonged. Therefore, if the clock frequency is known in advance, the period can be known, the charge amount required by the detection circuit for identifying the clock duty ratio can be determined, so that the capacitance value in the access circuit can be determined, the stored charge amount in the circuit can be timely reduced, and the clock calibration circuit can be timely calibrated, so that the clock quality is ensured. Similarly, when the clock operates at a low frequency, the period becomes longer, the discharge time in the unit period becomes longer, and as is clear from q=i×t=c×u, the amount of storable charge in the capacitor in the duty detection circuit needs to be increased accordingly, and the calibration time becomes longer. Therefore, if the clock frequency is known in advance, the period can be known, the minimum charge amount required by the detection circuit for identifying the clock duty ratio can be determined, so that the capacitance value in the access circuit can be determined, the stored charge amount in the circuit can be timely increased, and the clock calibration circuit can be timely calibrated, so that the clock quality is ensured. In the DDR memory, the data in the setting circuit of the mode register can directly reflect the working frequency range of the memory, so that the frequency information can be timely obtained at the initial stage of frequency conversion, and the capacitance in the duty ratio detection circuit is timely adjusted to change the total capacitance of the detection circuit, thereby ensuring that the duty ratio of the detection result is quickly adjusted to 50% +/-1%.
The full-band clock duty cycle calibration circuit according to the embodiment of the present invention is described in detail below:
In the present exemplary embodiment, the mode registers include an MR6 mode register reflecting a low frequency operation clock frequency and an MR2 mode register reflecting a high frequency operation clock frequency. The data contained in the setting circuits of the MR6 mode register and the MR2 mode register can directly reflect the frequency range in which the memory operates. For example, the MR2 mode register in DDR4JEDEC standard (DDR 4JEDEC SPEC) has a number of cycles set to meet the standard requirements according to the requirements of CWL (CAS Write Latency) at different clock frequencies, as shown in FIG. 2. The MR6 mode register has a number of cycles set to meet the standard requirements according to the need for tccd_l at different clock frequencies, as shown in fig. 3. Obviously, combining the information of tccd_l and CWL together for combined coding can cover all the effective operating frequencies of DRAM. In this way, the time of iteration can be reduced in the selection of the capacitance value for storing charge in the duty cycle detection circuit, thereby realizing rapid and accurate clock duty cycle adjustment.
Therefore, the charge quantity of the duty ratio detection circuit can be timely adjusted according to the change of the working frequency, so that the charge quantity can be increased or reduced to the charge quantity required by identifying the duty ratio of the clock as soon as possible, the accurate calibration of the duty ratio in the full-band working process is met, and the clock quality is ensured. Meanwhile, the set code of the self-contained reaction clock frequency of the memory mode register can accurately reflect the current frequency, the capacitor in the duty ratio detection circuit can be directly adjusted according to the set code, a more accurate calibration result can be obtained, an additional circuit module is not required to be added, and the calibration accuracy and speed are improved.
In this exemplary embodiment, as shown in fig. 4, the signal adjustment circuit may include a first delay chain 1-1, a second delay chain 1-2, a third delay chain 1-3, and a clock generator 2, where the first delay chain 1-1 receives and delays a first clock signal to obtain the first adjustment clock signal, the second delay chain 1-2 receives and delays the first adjustment clock signal to generate a second adjustment clock signal, the third delay chain 1-3 receives and delays the second adjustment clock signal to generate a third adjustment clock signal or bypasses the third adjustment clock signal, and the signal input terminal of the clock generator 2 receives the first clock signal and the third adjustment clock signal to generate the second clock signal. The three delay chains all receive detection results from the duty ratio detection circuit, and the clock signals are adjusted step by step according to the detection results in different amplitudes and precision. As shown in the figure, the detection results of the detection circuit are respectively transmitted to three delay chains through three counters, specifically, the first counter 4-1 transmits the duty ratio detection results to the first delay chain 1-1, the second counter 4-2 transmits the duty ratio detection results to the second delay chain 1-2, and the third counter 4-3 transmits the duty ratio detection results to the third delay chain 1-3, wherein the delay length of the first delay chain 1-1 is 200-3200ps, the delay length of the second delay chain 1-2 is 0-200ps, and the delay length of the third delay chain 1-3 is 0-16 ps. In addition, the three delay chains can be matched to adjust clock signals with different frequencies. When the clock signal operating frequency is lower than or equal to 1600Mb/s, only the first delay chain and the second delay chain can be used, and the third delay chain is used as a bypass function, and when the clock signal operating frequency is higher than 1600Mb/s, three delay chains can be used together. The corresponding relation between the delay length and the precision of the delay chain and the corresponding opened delay chains with different working frequencies refer to tables 1 and 2.
TABLE 1 delay chain delay length and precision
| Delay chain sequence number | Delay length of delay chain | Delay chain |
| 1 | 200~3200 | 187.5p |
| 2 | 0~200 | 12.5 |
| 3 | 0~16 | 1 |
Table 2 delay chains corresponding to different operating frequencies
The clock duty ratio detection circuit 3 of the present invention may take various forms, for example, in the present exemplary embodiment, the duty ratio detection circuit diagram and the timing diagram are shown in fig. 5 and 6, the circuit as a whole is a circuit provided as a mirror image, and in the present exemplary embodiment, the duty ratio detection circuit 3 includes a clock signal receiving end, a main circuit, a detection signal receiving end, and a latch circuit, as shown in fig. 4, and is a circuit provided as a mirror image. The clock signal receiving end is connected with the signal output end of the clock generator and is used for receiving complementary signals MCLK and/MCLK to be detected, and the complementary signals are converted by a second clock signal generated by the clock generator. The main circuit is used for detecting the duty ratio of the second clock signal by charging and discharging the capacitor, the capacitor of the main circuit is an adjustable capacitor, and the capacitance value can be adjusted according to the set code of the full-band working frequency of the reaction memory in the setting circuit. The detection signal receiving end receives the detection enable signal EN to control the charging and discharging of the main circuit capacitance element. The latch circuit is connected with the counter, receives the addition and subtraction instructions INC and DEC formed by the enabling times of the MCLK and/or MCLK signals in the main circuit, and outputs UP and DN signals to be connected with the counter. The duty ratio calibration circuit also comprises a counter, the UP and DN signals output by the counter of the latch circuit are sent to the counter, the counter counts the UP and DN signals and sends the counting result to the delay chain, so that the delay chain can determine the number of delay units of the access circuit.
All signals of the detection circuit can be transmitted through the MOS tube, and when the working level changes, the corresponding signals can be connected with or disconnected from the circuit. For example, as shown in fig. 4, the clock signal receiving end includes an NMOS transistor for conducting the clock signals MCLK and/MCLK to the main circuit at the high level, and the detection signal receiving end includes a PMOS transistor for conducting the detection enable signal EN to the main circuit at the high level.
In the present exemplary embodiment, the tunable capacitor may include a plurality of tunable capacitance circuits connected in parallel, each of the tunable capacitance circuits including a capacitance element and a switching element connected in series with the capacitance element. The number of the capacitive elements connected to the detection circuit is controlled by controlling the on and off of the switching element, so that the capacitance value of the detection circuit is adjusted.
The adjustable capacitor can simultaneously comprise an unadjustable capacitance circuit and a plurality of adjustable capacitance circuits, so that the complexity of a circuit is reduced and the adjustment cost is reduced on the premise of meeting the adjustment requirement. The adjustable capacitor circuit can also only comprise a plurality of adjustable capacitor circuits, and the adjustment range is larger. Through the structure of this implementation adjustment capacitance, can directly design a plurality of capacitive elements at the beginning of test circuit design, according to the change of operating frequency adjust the number of incorporation circuit can, both can realize the adjustment of capacitance, can satisfy the regulation demand of bigger scope or more accuracy again. Even if the capacitor element fails, other capacitor elements can be used as the substitute, the whole circuit structure is not required to be replaced, and the cost is reduced.
For example, in fig. 7, the main circuit of the detection circuit includes a fixed capacitor M0 and three capacitive elements M1, M2 and M3 connected in parallel with the fixed capacitor (a and B in fig. 4 correspond to a and B in fig. 6), and a switching element is connected in series to each of M1, M2 and M3. The fixed capacitor M0 provides a basic capacitance value, three capacitive elements M1, M2, M3 are used for adjustment, and four capacitors are matched to realize adjustment of the total capacitance value.
This embodiment incorporates three adjustable capacitive circuits, while in other exemplary embodiments more adjustable capacitive circuits may be incorporated, or there may be only one or two adjustable capacitive circuits, each including a capacitive element and a switching element in series therewith. The plurality of adjustable capacitance circuits can adjust the capacitance of the detection circuit in a larger range to accommodate higher clock frequencies. Each capacitive element is independently controlled by a respective switching element, and different capacitive requirements can be achieved for more accurate calibration of the duty cycle. The capacitance values of the respective capacitance elements may be the same or different, and those skilled in the art may perform various combinations according to the adjustment accuracy and the range, which is not particularly limited by the present invention. The present invention is not limited to the size and number of capacitive elements.
In this exemplary embodiment, each capacitor element may be a MOS tube, which may be a PMOS tube, or may be an NMOS tube, where a gate of each MOS tube is connected to a switching element, and the switching element controls access of the MOS tube, and the MOS tube accessed to the detection circuit charges or discharges at the gate voltage, so as to implement duty ratio detection. In this exemplary embodiment, the MOS transistor may be a PMOS transistor or an NMOS transistor as long as it is matched with the circuit polarity. As shown in the figure, in the detection circuit of this embodiment, the fixed capacitor and the adjustable capacitor are PMOS transistors, the source and the drain of each capacitor are connected to the power supply terminal, and the gate is connected to the main circuit. Of course, the capacitive element may also be a normal capacitance.
In this exemplary embodiment, the switching element of the adjustable capacitor is formed by connecting a PMOS tube and an NMOS tube in parallel, two control ends of the PMOS tube and the NMOS tube respectively receive complementary switching control signals Ctl1 and/Ctl 1, one end of the PMOS tube and one end of the NMOS tube connected in parallel are connected to the adjustable capacitor, and the other end is connected to the main circuit, so as to realize charging or discharging of the capacitor when different level signals are conducted. The Ctl1 and/Ctl 1 signals come from the clock frequency detection unit, and the clock frequency detection unit generates control signals Ctl1 and/Ctl 1 to control the on and off of the switching element through the acquired setting codes, so that the capacitance value of the access detection circuit is changed.
In the present exemplary embodiment, the decoding circuit 5 may include a first decoding circuit that is respectively connected to the setting circuit of the MR6 mode register 7, the setting circuit of the MR2 mode register 6, and the adjustable capacitor of the duty detection circuit 3, and the setting code is obtained by the first decoding circuit, and the binary code thereof is converted into an output signal for adjusting the on and off of each switching element in the adjustable capacitor. The MR2 and MR6 mode registers may share one decoding circuit, or may each use one decoding circuit, which is not particularly limited by the present application.
In the present exemplary embodiment, the decoding circuit 5 may further include a second decoding circuit connected to the setting circuit of the MR6 mode register 7, the MR2 mode register 6 setting circuit, and the first delay chain 1-1, the second delay chain 1-2, and the third delay chain 1-3, respectively, for converting the setting code into the output signal to adjust the initial setting values of the three delay chains. The working period of the memory can be acquired from the setting codes of the CWL and the tCCD_L, and the initial setting values of the three delay chains are adjusted, so that the complicated adjustment process can be reduced, and the calibration time is further reduced.
In view of the simplicity of the structure, the first decoding circuit and the second decoding circuit of the present embodiment are each derived from a multiple-input multiple-output selector (3-8 decoder) in the existing MR6 mode register and MR2 mode register setting circuit of the memory, and the switching element adjustment signal and the delay chain adjustment signal are simultaneously generated by the selector.
The embodiment of the invention also provides a memory, which comprises any one of the full-band clock duty cycle calibration circuits. The clock of the memory can always ensure that the duty ratio is 50+/-1%, so that the accuracy of data reading is higher.
The embodiment of the invention also provides a full-band clock duty cycle calibration method, referring to fig. 8, including:
step S110, a signal adjusting circuit is utilized to receive a first clock signal of a memory and adjust the first clock signal to generate a second clock signal;
Step S210, the decoding circuit 5 is utilized to convert the setting codes of the high-frequency or low-frequency working frequency of the reaction memory in the MR6 mode register 7 or MR2 mode register 6 setting circuit of the memory into output signals, and the capacitance value of the duty ratio detection circuit is regulated through the output signals;
step S310, detecting the duty ratio of the second clock signal by using a duty ratio detection circuit after the capacitance is adjusted;
in step S410, the signal adjustment circuit performs the adjustment on the first clock signal according to the duty cycle detection result.
Through the steps, the setting codes capable of directly reflecting the current full-band working frequency of the memory are obtained from the data of the MR6 mode register 7 and the MR2 mode register setting circuit of the memory, so that the capacitance in the duty ratio detection circuit is timely adjusted according to the setting codes, the total capacitance of the detection circuit is increased or reduced, and the detection requirement is ensured to be met. When the working frequency is at a high frequency, the decoding circuit adjusts the capacitance value according to the setting circuit of the MR2 mode register, and when the working frequency is at a low frequency, the decoding circuit adjusts the capacitance value according to the setting circuit of the MR7 mode register, thereby ensuring that the duty ratio can be adjusted to 50% +/-1% as soon as possible, whether at the low frequency or the high frequency.
In step S110 of the present exemplary embodiment, the signal adjustment circuit may include a first delay chain 1-1, a second delay chain 1-2, a third delay chain 1-3, and a clock generator 2, where the first delay chain 1 delays the first clock signal to generate the first adjustment clock signal, the second delay chain 1-2 receives and delays the first adjustment clock signal to generate the second adjustment clock signal, the third delay chain 1-3 receives and delays the second adjustment clock signal to generate the third adjustment clock signal, or as a bypass, and the clock generator 2 receives the first clock signal and the third adjustment clock signal to generate the second clock signal.
In step S210 of the present exemplary embodiment, the capacitance value of the duty cycle detection circuit 3 is adjustable, and the duty cycle detection circuit 3 may have various forms, and the capacitance value thereof may be adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
Further, whether or not the capacitive elements are connected in parallel to the duty ratio detection circuit is controlled by switching elements connected in series with the respective capacitive elements, and on and off signals of the switching elements come from the clock frequency detection unit.
In step S210 of the present exemplary embodiment, the clock frequency detecting unit includes a first decoding circuit, by which the setting code is converted into an output signal to control on and off of the switching element.
Referring to fig. 9, the present exemplary embodiment further includes step S510 of converting the setting code into an output signal by the second decoding circuit to adjust initial setting values of the three delay chains to be half (T/2) of the current period value of the clock. The second decoding circuit belongs to the clock frequency detection unit. The T/2 is used as the initial values of the three delay chains, so that the problem that the three delay chains need to be increased step by step to lengthen the whole calibration period is solved, the adjustment time can be shortened, and the duty ratio can be adjusted to about 50% as soon as possible. Of course, the initial value may be a value close to T/2.
Thus, in addition to improving delay accuracy by reducing or increasing the capacitance value of the detection circuit, delay speed is improved, and calibration quality of the calibration circuit is improved in two aspects.
Further, the first decoding circuit and the second decoding circuit may each employ a multiple-input multiple-output selector circuit in the existing MR6 mode register and MR2 mode register setting circuit, with which the switching element adjustment signal and the delay chain initial value adjustment signal are simultaneously generated.
The circuit structure in this embodiment refers to the related description in the calibration circuit, and will not be described herein.
In the method of the invention, the first clock signal is regulated by the signal regulating circuit or the duty ratio is detected by the duty ratio detecting circuit, and the whole duty ratio calibration is a continuous cyclic process. Correspondingly, the work of the decoding circuit is continuously carried out, once the working frequency of the memory is increased to high frequency or reduced to low frequency, the decoding circuit can adjust the capacitance value of the duty ratio detection circuit according to the set codes, or adjust the initial value of the delay chain at the same time, thereby realizing the higher quality all the time in the whole cycle calibration process and keeping the quality of the memory clock stable all the time.
It will be appreciated by those skilled in the art that since the calibration process is performed cyclically and certain steps may be performed in any order, the above steps are described for convenience of description and are not the only limitations of the implementation process of the method of the present invention. For example, in addition to the above-described implementation of the steps, the signal adjustment circuit adjusts the clock signal and the decoding circuit adjusts the capacitance value simultaneously, or in a permuted order. The first decoding circuit can adjust the capacitance value and the second decoding circuit can adjust the initial value of the delay chain at the same time or change the sequence.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc., and the terms "comprising" and "having" are intended to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (12)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| CN208861671U (en) * | 2018-11-08 | 2019-05-14 | 长鑫存储技术有限公司 | Full Band Clock Duty Cycle Calibration Circuit and Memory |
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| CN101629978B (en) * | 2008-12-26 | 2012-10-03 | 四川和芯微电子股份有限公司 | Method and circuit for realizing real-time monitoring for duty ratio |
| KR101290192B1 (en) * | 2011-10-28 | 2013-07-30 | 고려대학교 산학협력단 | High-Speed Duty Cycle Correction Circuit |
| US9369118B2 (en) * | 2014-07-11 | 2016-06-14 | Kabushiki Kaisha Toshiba | Duty cycle correction circuit and semiconductor device |
| CN105162435A (en) * | 2015-08-28 | 2015-12-16 | 西安启微迭仪半导体科技有限公司 | Clock duty cycle adjustment circuit with wide adjustment range |
| KR20170045768A (en) * | 2015-10-19 | 2017-04-28 | 에스케이하이닉스 주식회사 | Duty cycle detection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| CN208861671U (en) * | 2018-11-08 | 2019-05-14 | 长鑫存储技术有限公司 | Full Band Clock Duty Cycle Calibration Circuit and Memory |
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