CN111161773A - Low-frequency clock duty ratio calibration circuit, calibration method and memory - Google Patents
Low-frequency clock duty ratio calibration circuit, calibration method and memory Download PDFInfo
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Abstract
The invention provides a low-frequency clock duty ratio calibration circuit, a calibration method and a memory. The setting code reflecting the low-frequency working frequency of the memory in the mode register setting circuit of the memory is converted into an output signal by using the decoding circuit, and the capacitance value of the duty ratio detection circuit is adjusted by the output signal to meet the detection requirement, so that the clock duty ratio calibration quality is improved. The invention can calibrate the clock duty ratio in time for the current clock frequency when working at low frequency, has high calibration accuracy and high calibration speed, and ensures the clock quality of the memory; and the memory mode self-contained circuit is utilized, the structure is simple, and the cost is lower.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-frequency clock duty ratio calibration circuit and a memory, and further relates to a low-frequency clock duty ratio calibration method.
Background
In the dynamic random access memory, the duty ratio reaches 50%, so that the utilization efficiency of the clock level can be improved to the maximum extent, and the normal operation and the optimal performance of the system are guaranteed. However, in actual operation, the duty ratio of the clock circuit often deviates from 50%, and the clock duty ratio calibration circuit is a type of circuit designed for the problem.
The existing clock duty ratio calibration circuit compares the charge and discharge time and the electric quantity of a capacitor. Because the memory may work at a lower working frequency, the capacitance is fixed during design, when the clock frequency changes, the lower clock frequency has longer charging and discharging time, and the longer charging and discharging time causes the clock quality to be reduced because the capacitance connected to the duty ratio detection circuit is insufficient; furthermore, the delay chain at low frequencies requires the access of a longer number of stages to match the longer period, so that the overall calibration time becomes longer as the clock frequency becomes higher.
Ideally, no matter how high or low the clock frequency of the memory is, the duty ratio of the internal clock signal in the memory needs to be adjusted as fast as possible, so as to ensure the correctness of the read data of the whole memory.
Disclosure of Invention
The invention aims to provide a low-frequency clock duty ratio calibration circuit and a memory, which solve the problems of overlong calibration time and reduced calibration quality under low frequency.
The invention also aims to provide a low-frequency clock duty ratio calibration method.
According to an aspect of the present invention, there is provided a low frequency clock duty cycle calibration circuit, comprising:
the signal adjusting circuit is used for receiving and adjusting a first clock signal of the memory to generate a second clock signal;
the duty ratio detection unit is connected with the signal adjusting circuit and is used for detecting the duty ratio of the second clock signal and feeding back a detection result to the signal adjusting circuit, and the duty ratio detection unit comprises a duty ratio detection circuit with an adjustable capacitor;
a mode register including a setting code reflecting a clock frequency of the low frequency operation of the memory;
and the decoding circuit is connected with the duty ratio detection circuit and the mode register setting circuit so as to adjust the capacitance value of an adjustable capacitor in the duty ratio detection circuit according to the setting code.
In an exemplary embodiment of the present invention, the mode register is an MR6 mode register.
In an exemplary embodiment of the invention, the signal conditioning circuit includes a delay chain for receiving and delaying the first clock signal to generate a conditioned clock signal and a clock generator for receiving the first clock signal and the conditioned clock signal to generate a second clock signal.
In an exemplary embodiment of the present invention, the duty ratio detection unit further includes a counter, and the counter is connected to the delay chain; the duty ratio detection circuit includes:
a clock signal receiving end connected to the signal adjusting circuit for receiving the second clock signal;
a main circuit including the tunable capacitor, for detecting a duty ratio of the second clock signal by charging and discharging the tunable capacitor;
the detection signal receiving end receives a detection enabling signal to control the charging and discharging of the main circuit capacitive element;
and the latch circuit is connected with the counter and used for receiving an addition and subtraction instruction formed by the enabling times of the clock signal in the main circuit and outputting the addition and subtraction instruction to the counter so as to forward a counting result to the delay chain.
In an exemplary embodiment of the invention, the tunable capacitor comprises a plurality of tunable capacitance circuits connected in parallel, each of the tunable capacitance circuits comprising a capacitive element and a switching element connected in series with the capacitive element.
In an exemplary embodiment of the present invention, the capacitor element is an MOS transistor, and a gate of each of the MOS transistors is connected to the switching element.
In an exemplary embodiment of the present invention, the switching element includes a PMOS transistor and an NMOS transistor connected in parallel, a control signal received by the PMOS transistor is complementary to a control signal received by the NMOS transistor, and the on and off signals of the switching element are from the decoding circuit.
In an exemplary embodiment of the present invention, the decoding circuit includes: and the first decoding circuit is connected with the setting circuit of the MR6 mode register and the adjustable capacitor of the duty ratio detection circuit and is used for converting the setting code into an output signal so as to adjust the on and off of each switching element in the adjustable capacitor.
In an exemplary embodiment of the present invention, the decoding circuit further includes: and the second decoding circuit is connected with the setting circuit of the MR6 mode register and the delay chain and is used for converting the setting code into an output signal so as to adjust the initial setting value of the delay chain.
In an exemplary embodiment of the invention, the first decoding circuit or the second decoding circuit both adopt a multiple-input multiple-output selector in the setting circuit of the memory MR6 mode register.
According to another aspect of the invention, there is provided a memory comprising the low frequency clock duty cycle calibration circuit of any one of the above.
According to still another aspect of the present invention, there is provided a low frequency clock duty cycle calibration method, including:
receiving a first clock signal of a memory by using a signal adjusting circuit, and adjusting the first clock signal to generate a second clock signal;
a decoding circuit is utilized to convert the setting code of the clock frequency reflecting the low-frequency work of the memory in the setting circuit of the MR6 mode register of the memory into an output signal, and the output signal regulates the capacitance value of the duty ratio detection circuit;
detecting the duty ratio of the second clock signal by using the duty ratio detection circuit after the capacitor is adjusted;
and the signal adjusting circuit adjusts the first clock signal according to the duty ratio detection result.
In an exemplary embodiment of the invention, the signal conditioning circuit comprises a delay chain through which the first clock signal is delayed to generate a conditioned clock signal, and a clock generator; receiving, by the clock generator, the first clock signal and an adjusted clock signal to generate the second clock signal.
In an exemplary embodiment of the present invention, the capacitance value of the duty ratio detection circuit is adjusted by controlling the number of capacitive elements connected in parallel to the duty ratio detection circuit.
In an exemplary embodiment of the present invention, the number of the capacitive elements of the duty detection circuit is controlled by a switching element connected in series with the capacitive element, and on and off signals of the switching element are supplied from the decoding circuit.
In an exemplary embodiment of the present invention, the decoding circuit includes a first decoding circuit, and the setting code is converted into an output signal by the first decoding circuit to control on and off of the switching element.
In an exemplary embodiment of the present invention, the decoding circuit further includes a second decoding circuit; the calibration method further comprises: and converting the setting code into an output signal through the second decoding circuit so as to adjust the initial setting value of the delay chain to be half of the current period value of the clock.
In an exemplary embodiment of the present invention, the first decoding circuit or the second decoding circuit each employs a multiple-input multiple-output selector circuit in the memory mode register setting circuit.
The low-frequency clock duty ratio calibration circuit determines the capacitance required by the duty ratio detection circuit according to the setting code of the mode register reaction low-frequency clock frequency setting circuit, and improves the calibration speed by adjusting the capacitance value of the duty ratio detection circuit. On one hand, the charge quantity of the duty ratio detection circuit can be adjusted according to the requirement, so that the charge quantity required by identifying the clock duty ratio can be timely reached, the clock duty ratio can be accurately calibrated, and the clock quality is ensured; on the other hand, the capacitor in the duty ratio detection circuit is directly adjusted through the setting code of the self reaction clock frequency of the memory mode register, the current clock frequency can be calibrated, and the calibration accuracy is higher and the calibration speed is higher; and the self-contained circuit of the memory mode is utilized, the structure is simple, and the cost is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a diagram of a conventional clock duty cycle calibration circuit;
FIG. 2 shows the setting code of tCCD _ L in DDR 4;
FIG. 3 is a circuit diagram of the calibration of the duty cycle of the low frequency clock according to the present invention;
FIG. 4 is a circuit diagram of duty cycle detection according to the present invention;
FIG. 5 is a timing diagram of the duty cycle detection circuit of the present invention;
FIG. 6 is a schematic diagram of the tunable capacitor of part A of FIG. 4;
FIG. 7 is a truth table of the decoding circuit of the calibration circuit for duty cycle of low frequency clock according to the present invention;
FIG. 8 is a first flowchart of a low frequency clock duty cycle calibration method according to the present invention;
FIG. 9 is a second flowchart of the calibration method of the duty cycle of the low frequency clock according to the present invention.
In the figure, 1, a delay chain; 2. a clock generator; 3. a duty ratio detection circuit; 4. a counter; 5. a decoding circuit; 6. MR6 mode register.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
In the related art, a conventional clock duty calibration circuit includes: the signal adjusting circuit is used for receiving a first clock signal of the memory and adjusting the first clock signal into a second clock signal, so that the duty ratio is maintained in an ideal range; the duty ratio detection unit is used for detecting the duty ratio of the second clock signal and transmitting the detection result to the signal adjusting circuit so as to assist the signal adjusting circuit to adjust the first clock signal and ensure that the duty ratio reaches an ideal adjusting result.
As shown in fig. 1, the signal adjusting circuit includes a delay chain 1 and a clock generator 2, and the delay chain 1 is used to delay a first clock signal of the memory to generate a delayed adjusting clock signal; a clock generator 2 is used to receive the first clock signal and the adjusted clock signal and to generate a second clock signal. The duty ratio detection unit comprises a duty ratio detection circuit 3 and a counter 4, wherein the duty ratio detection circuit 3 is connected with the signal output end of the clock generator 2, receives the second clock signal and detects the duty ratio of the second clock signal, then the counter 4 is used for counting, and the counting result is transmitted to the delay chain 1 so that the delay chain 1 can delay the first clock signal.
Since the operating frequency of the DDR memory changes, the frequency is often reduced to a low frequency range (the low frequency referred to in the present invention means a transmission rate lower than or equal to 2400Mb/s), and when the clock frequency becomes low, the charge amount of the capacitor reserve in the delay chain and the duty ratio detection circuit of the high frequency circuit needs to be adjusted accordingly. For example, when the clock transmission rate is changed from 3200Mb/s to lower than 1333Mb/s, the delay time of the delay chain is 6.25p, the clock period is changed from 625ps to greater than or equal to 1.5ns, and the longer period means that the number of the delay chains is increased from the original 50 to at least 120, and the delay chains of the access circuit are obviously more than the original, so that the whole calibration time is longer because the number of the delay chains is larger.
Therefore, the embodiment of the invention provides a low-frequency clock duty ratio calibration circuit, which can quickly and accurately calibrate the clock duty ratio of a memory working in a low-frequency range and is suitable for duty ratio calibration of a DDR memory when the clock frequency becomes low. The DDR memory may be DDR4 or DDR3 or DDR 2.
The low frequency clock duty ratio calibration circuit of the present embodiment includes: the circuit comprises a signal adjusting circuit, a duty ratio detection unit, a mode register setting circuit and a decoding circuit. The signal adjusting circuit is used for receiving and adjusting a first clock signal of the memory to generate a second clock signal; the duty ratio detection unit is connected with the signal adjusting circuit and is used for detecting the duty ratio of the second clock signal and feeding back a detection result to the signal adjusting circuit, and the duty ratio detection unit comprises a duty ratio detection circuit with an adjustable capacitor; the mode register setting circuit comprises a setting code reflecting the low-frequency working frequency of the memory; the decoding circuit is connected with the duty ratio detection circuit and the setting circuit in the mode register so as to adjust the capacitance value of the adjustable capacitor in the duty ratio detection circuit according to the setting code.
The principle of the calibration circuit of the invention is as follows: when the clock operates at a low frequency, the period is long, the discharge time in the unit period is long, and as can be seen from Q ═ I × T ═ C × U, the amount of electric charge storable in the capacitor in the duty ratio detection circuit needs to be increased correspondingly, and the calibration time is prolonged. Therefore, if the clock frequency is known in advance, the period can be known, the minimum charge quantity required by the identification clock duty ratio in the detection circuit can be determined, the capacitance value in the access circuit can be determined, the stored charge quantity in the circuit can be increased in time, and the clock calibration circuit can be ensured to calibrate in time to ensure the clock quality. In the DDR memory, data in a setting circuit of a mode register can directly reflect the working frequency range of the memory, so that frequency information can be obtained in time at the initial stage of frequency conversion, the capacitance in a duty ratio detection circuit is adjusted in time, the total capacitance of the detection circuit is changed, and the duty ratio of a detection result is adjusted to 50 +/-1% as soon as possible.
The following describes a low-frequency clock duty ratio calibration circuit according to an embodiment of the present invention in detail:
in the present exemplary embodiment, the mode register is the MR6 mode register. The data contained in the setting circuit of the MR6 mode register can directly reflect the frequency range in which the memory operates. For example, the MR6 mode register in DDR4JEDEC standard (DDR4JEDECSPEC) is set to meet the cycle number required by the standard according to the requirements of tCCD _ L at different clock frequencies, as shown in fig. 2, so that the capacitance value connected into the detection circuit can be determined from the setting codes of different tCCD _ L to speed up the calibration quality of the clock duty ratio.
Therefore, the charge quantity of the duty ratio detection circuit can be timely adjusted according to the change of the working frequency, so that the charge quantity required by clock duty ratio identification can be reached as soon as possible, the duty ratio can be accurately calibrated during low-frequency working, and the clock quality is ensured. Meanwhile, the setting code of the self-contained reaction clock frequency of the memory mode register can accurately reflect the current frequency, the capacitor in the duty ratio detection circuit is directly adjusted according to the current frequency, a more accurate calibration result can be obtained, an additional circuit module is not needed, and the calibration accuracy and speed are improved.
In the present exemplary embodiment, as shown in fig. 3, the signal adjusting circuit may include a delay chain 1 and a clock generator 2, the delay chain 1 receives the first clock signal and delays it to obtain an adjusted clock signal, and a signal input terminal of the clock generator 2 receives the first clock signal and the adjusted clock signal to generate the second clock signal.
The clock duty detection circuit 3 of the present invention may have various forms, for example, in the present exemplary embodiment, a duty detection circuit diagram and a timing chart are shown in fig. 4 and 5, the circuit is a circuit arranged as a mirror as a whole, and in the present exemplary embodiment, as shown in fig. 4, the duty detection circuit 3 includes a clock signal receiving terminal, a main circuit, a detection signal receiving terminal and a latch circuit, and the circuit is arranged as a mirror. The clock signal receiving end is connected with the signal output end of the clock generator and is used for receiving complementary signals MCLK and/MCLK to be detected, and the signals are converted from a second clock signal generated by the clock generator. The main circuit is used for detecting the duty ratio of the second clock signal by charging and discharging a capacitor, the capacitor of the main circuit is an adjustable capacitor, and the capacitance value can be adjusted according to a setting code which reflects the low-frequency working frequency of the memory in the setting circuit. The detection signal receiving end receives a detection enable signal EN to control the charging and discharging of the main circuit capacitance element. The latch circuit is connected with the counter, receives the addition and subtraction commands INC and DEC formed by the enabling times of the MCLK and/MCLK signals in the main circuit, and outputs UP and DN signals to the counter. The duty ratio calibration circuit also comprises a counter, the UP and DN signals output by the latch circuit counter are sent to the counter, the counter counts the UP and DN signals and sends the counting result to the delay chain, and the delay chain determines the number of delay units of the access circuit.
All signals of the detection circuit can be transmitted through the MOS tube, and when the working level changes, the corresponding signals can be connected or disconnected with the circuit. For example, as shown in fig. 4, the clock signal receiving terminal includes an NMOS transistor for conducting the clock signals MCLK and/MCLK to the main circuit at a high level, and the detection signal receiving terminal includes a PMOS transistor for conducting the detection enable signal EN to the main circuit at a high level.
In the present exemplary embodiment, the tunable capacitor may include a plurality of tunable capacitance circuits connected in parallel, each tunable capacitance circuit including a capacitance element and a switching element connected in series with the capacitance element. The number of the capacitance elements connected into the detection circuit is controlled by controlling the on and off of the switch elements, so that the capacitance value of the detection circuit is adjusted.
The adjustable capacitor can simultaneously comprise an unadjustable capacitor circuit and a plurality of adjustable capacitor circuits, so that the complexity of the circuit is reduced on the premise of meeting the adjustment requirement, and the adjustment cost is reduced. The adjustable capacitor circuit can only comprise a plurality of adjustable capacitor circuits, and the adjustment range is larger. Through this implementation structure adjustment capacitance value, can directly design a plurality of capacitive element at the beginning of test circuit design, according to operating frequency's change adjustment merge into the circuit the number can, both can realize the adjustment of capacitance value, can satisfy more extensive or more accurate adjustment demand again. Even if the capacitor element has a fault, other capacitor elements can be used as substitutes, the whole circuit structure does not need to be replaced, and the cost is reduced.
For example, in fig. 6, the main circuit of the detection circuit includes a fixed capacitor M0 and three capacitive elements M1, M2 and M3 (a and B in fig. 4 correspond to a and B in fig. 6) connected in parallel with the fixed capacitor, and M1, M2 and M3 are each connected in series with a switching element. The fixed capacitor M0 provides a basic capacitance, the three capacitor elements M1, M2, M3 are used for adjustment, and the four capacitors are used together to adjust the total capacitance.
This embodiment incorporates three tunable capacitance circuits, while in other exemplary embodiments, more tunable capacitance circuits may be incorporated, or only one or two tunable capacitance circuits, each including a capacitive element and a switching element in series therewith. The plurality of adjustable capacitance circuits can adjust the capacitance of the detection circuit in a larger range to adapt to a lower clock frequency. Each capacitive element is independently controlled by a respective switching element, and different capacitance requirements can be realized so as to calibrate the duty ratio more accurately. The capacitance values of the capacitance elements may be the same or different, and those skilled in the art may make various combinations according to the requirements of the adjustment precision and range, and the present invention does not specially limit the present invention. The present invention does not limit the size or number of the capacitor elements.
In this exemplary embodiment, each capacitive element may be an MOS transistor, which may be a PMOS transistor or an NMOS transistor, a gate of each MOS transistor is connected to a switching element, the switching element controls the connection of the MOS transistor, and the MOS transistor connected to the detection circuit is charged or discharged at a gate voltage, so as to implement duty ratio detection. In the present exemplary embodiment, the MOS transistor may be a PMOS transistor or an NMOS transistor as long as the polarity of the MOS transistor is matched with that of the circuit. As shown in the figure, in the detection circuit of this embodiment, the fixed capacitor and the adjustable capacitor are both PMOS transistors, the source and the drain of each capacitor are both connected to the power source, and the gate is both connected to the main circuit. Of course, the capacitive element may also be a common capacitor.
In the exemplary embodiment, the switching element of the adjustable capacitor is formed by connecting a PMOS transistor and an NMOS transistor in parallel, two control ends of the PMOS transistor and the NMOS transistor respectively receive complementary switch control signals Ctl1 and/Ctl 1, one end of the parallel connection of the PMOS transistor and the NMOS transistor is connected to the adjustable capacitor, and the other end of the parallel connection of the PMOS transistor and the NMOS transistor is connected to the main circuit, so as to charge or discharge the capacitor when signals with different levels are conducted. The Ctl1 and/Ctl 1 signals come from a clock frequency detection unit, and the clock frequency detection unit generates control signals Ctl1 and/Ctl 1 to control the on and off of the switching element through the acquired setting codes, so that the capacitance value of the access detection circuit is changed.
In the present exemplary embodiment, the decoding circuit 5 may include a first decoding circuit, the first decoding circuit is connected to the MR6 mode register 6 setting circuit and the adjustable capacitor of the duty ratio detection circuit 3, the setting code is obtained by the first decoding circuit, and the binary code thereof is converted into an output signal for adjusting the on and off of each switching element in the adjustable capacitor.
In the present exemplary embodiment, the decoding circuit 5 may further include a second decoding circuit, and the second decoding circuit is connected to the MR6 mode register 6 setting circuit and the delay chain 1, and is configured to convert the setting code into a pulse output signal, so as to adjust the initial setting value of the delay chain. Because the working period of the memory can be obtained from the setting code of the tCCD _ L, the initial setting value of the delay chain is adjusted, the fussy adjusting process can be reduced, and the calibration time is further reduced.
In view of the simple structure, the first decoding circuit and the second decoding circuit of the present embodiment are both from a multiple-input multiple-output selector (3-8 decoder) in the memory existing MR6 mode register setting circuit, and the switching element adjustment signal and the delay chain adjustment signal are simultaneously generated by the selector. Fig. 7 is a truth table applied to the decoding circuit of the present example. Of course, those skilled in the art will recognize that other decoding circuits may be used to decode the set code.
The embodiment of the invention also provides a memory, which comprises any one of the low-frequency clock duty ratio calibration circuits. The clock of the memory can always ensure that the duty ratio is 50% + -1%, so that the correctness of reading data is higher.
The embodiment of the present invention further provides a method for calibrating a duty ratio of a low-frequency clock, which, with reference to fig. 8, includes:
step S110, receiving a first clock signal of the memory by using a signal adjusting circuit, and adjusting the first clock signal to generate a second clock signal;
step S210, a decoding circuit 5 is used for converting the setting code of the low-frequency working frequency of the reaction memory in the MR6 mode register 6 setting circuit of the memory into an output signal, and the capacitance value of the duty ratio detection circuit is adjusted through the output signal;
step S310, detecting the duty ratio of a second clock signal by using a duty ratio detection circuit after the capacitor is adjusted;
in step S410, the signal adjusting circuit performs the adjustment on the first clock signal according to the duty ratio detection result.
Through the steps, the setting code capable of directly reflecting the current low-frequency working frequency of the memory is obtained from the data of the MR6 mode register setting circuit of the memory, so that the capacitance in the duty ratio detection circuit is adjusted in time according to the setting code to increase the total capacitance of the detection circuit, the detection requirement is ensured to be met, and the duty ratio is adjusted to 50% +/-1% as soon as possible.
In step S110 of the present exemplary embodiment, the signal adjusting circuit may include a delay chain 1 and a clock generator 2, and delay the first clock signal by the delay chain 1 to generate an adjusted clock signal; the first clock signal is received by the clock generator 2 and the adjusted clock signal is used to generate a second clock signal.
In step S210 of the present exemplary embodiment, the capacitance value of the duty ratio detection circuit 3 is adjustable, and the duty ratio detection circuit 3 may have various forms, and the capacitance value thereof may be adjusted by controlling the number of capacitive elements connected in parallel to the duty ratio detection circuit.
Further, whether or not the capacitance elements are connected in parallel to the duty ratio detection circuit is controlled by switching elements connected in series to the respective capacitance elements, and on and off signals of the switching elements are from the clock frequency detection unit.
Referring to fig. 9, in step S210 of the present exemplary embodiment, the clock frequency detecting unit includes a first decoding circuit, and the setting code is converted into an output signal by the first decoding circuit to control the on and off of the switching element.
The exemplary embodiment further includes step S510 of converting the setting code into an output signal through a second decoding circuit to adjust the initial setting value of the delay chain to be half (T/2) of the current period value of the clock. The second decoding circuit belongs to the clock frequency detection unit. The T/2 is used as the initial value of the delay chain, the defect that the whole calibration period is lengthened due to the fact that the delay chain needs to be increased step by step is avoided, the adjusting time can be shortened, and the duty ratio can be adjusted to be about 50% as soon as possible. Of course, the initial value may be a value close to T/2.
Therefore, the time delay accuracy is improved by increasing the capacitance value of the detection circuit, the time delay speed is also improved, and the calibration quality of the calibration circuit is improved from two aspects.
Further, the first decoding circuit and the second decoding circuit each employ a multiple-input multiple-output selector circuit in the memory-existing MR6 mode register setting circuit, with which the switching element adjustment signal and the delay chain initial value adjustment signal are simultaneously generated.
The circuit structures related in this embodiment refer to the related descriptions in the calibration circuit, and are not described herein again.
In the method of the invention, the adjustment of the first clock signal by the signal adjusting circuit or the detection of the duty ratio by the duty ratio detecting circuit are continuously carried out, so that the whole duty ratio calibration is a continuous and cyclic process. Correspondingly, the work of the decoding circuit is continuously carried out, once the working frequency of the memory is reduced to low frequency, the decoding circuit can adjust the capacitance value of the duty ratio detection circuit according to the set code or adjust the initial value of the delay chain at the same time, and therefore the whole cyclic calibration process can always achieve high quality, and the clock quality of the memory can always be kept stable.
It will be understood by those skilled in the art that since the calibration process is performed in a loop, and some steps may not be in a sequential order, the above steps are described for convenience of description and are not the only limitations to the implementation of the method of the present invention. For example, in addition to the above step implementation, the clock signal adjustment circuit and the capacitance adjustment circuit may be performed simultaneously, or in a reversed order. The capacitance value adjustment of the first decoding circuit and the initial value adjustment of the delay chain of the second decoding circuit can be carried out simultaneously or the sequence can be changed.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (18)
1. A low frequency clock duty cycle calibration circuit, comprising:
the signal adjusting circuit is used for receiving and adjusting a first clock signal of the memory to generate a second clock signal;
the duty ratio detection unit is connected with the signal adjusting circuit and is used for detecting the duty ratio of the second clock signal and feeding back a detection result to the signal adjusting circuit, and the duty ratio detection unit comprises a duty ratio detection circuit with an adjustable capacitor;
a mode register including a setting code reflecting a clock frequency of the low frequency operation of the memory;
and the decoding circuit is connected with the duty ratio detection circuit and the mode register so as to adjust the capacitance value of an adjustable capacitor in the duty ratio detection circuit according to the setting code.
2. The low frequency clock duty cycle calibration circuit of claim 1, wherein the mode register is an MR6 mode register.
3. The low frequency clock duty cycle calibration circuit of claim 2, wherein the signal adjustment circuit comprises a delay chain to receive the first clock signal and delay it to generate an adjusted clock signal, and a clock generator to receive the first clock signal and the adjusted clock signal to generate a second clock signal.
4. The low frequency clock duty cycle calibration circuit of claim 3, wherein the duty cycle detection unit further comprises a counter, the counter being connected to the delay chain; the duty ratio detection circuit includes:
a clock signal receiving end connected to the signal adjusting circuit for receiving the second clock signal;
a main circuit including the tunable capacitor, for detecting a duty ratio of the second clock signal by charging and discharging the tunable capacitor;
the detection signal receiving end receives a detection enabling signal to control the charging and discharging of the main circuit capacitive element;
and the latch circuit is connected with the counter and used for receiving an addition and subtraction instruction formed by the enabling times of the clock signal in the main circuit and outputting a pulse signal to the counter so as to transmit a counting result to the delay chain.
5. The low frequency clock duty cycle calibration circuit of claim 4, wherein the adjustable capacitor comprises a plurality of adjustable capacitance circuits connected in parallel, each of the adjustable capacitance circuits comprising a capacitive element and a switching element in series with the capacitive element.
6. The low-frequency clock duty cycle calibration circuit according to claim 5, wherein the capacitive element is an MOS transistor, and a gate of each MOS transistor is connected to the switching element.
7. The calibration circuit of claim 6, wherein the switching element comprises a PMOS transistor and an NMOS transistor connected in parallel, the PMOS transistor receives a control signal complementary to a control signal received by the NMOS transistor, and the on and off signals of the switching element are from the decoding circuit.
8. The low frequency clock duty cycle calibration circuit of claim 3, wherein the decoding circuit comprises:
and the first decoding circuit is connected with the setting circuit of the MR6 mode register and the adjustable capacitor of the duty ratio detection circuit and is used for converting the setting code into an output signal so as to adjust the on and off of each switching element in the adjustable capacitor.
9. The low frequency clock duty cycle calibration circuit of claim 3, wherein the decoding circuit further comprises:
and the second decoding circuit is connected with the setting circuit of the MR6 mode register and the delay chain and is used for converting the setting code into an output signal so as to adjust the initial setting value of the delay chain.
10. The calibration circuit for duty cycle of low frequency clock according to claim 8 or 9, wherein the first decoding circuit or the second decoding circuit employs a multiple input multiple output selector circuit in the setting circuit of the MR6 mode register.
11. A memory comprising the low frequency clock duty cycle calibration circuit of any one of claims 1 to 10.
12. A method for calibrating a duty cycle of a low frequency clock, comprising:
receiving a first clock signal of a memory by using a signal adjusting circuit, and adjusting the first clock signal to generate a second clock signal;
a decoding circuit is utilized to convert the setting code of the clock frequency reflecting the low-frequency work of the memory in the setting circuit of the MR6 mode register of the memory into an output signal, and the capacitance value of the duty ratio detection circuit is adjusted through the output signal;
detecting the duty ratio of the second clock signal by using the duty ratio detection circuit after the capacitor is adjusted;
and the signal adjusting circuit adjusts the first clock signal according to the duty ratio detection result.
13. The clock duty cycle calibration method of claim 12, wherein the signal adjustment circuit comprises a delay chain and a clock generator, the first clock signal being delayed by the delay chain to generate an adjusted clock signal; receiving, by the clock generator, the first clock signal and an adjusted clock signal to generate the second clock signal.
14. The clock duty cycle calibration method according to claim 13, wherein the capacitance value of the duty cycle detection circuit is adjusted by controlling the number of capacitive elements connected in parallel to the duty cycle detection circuit.
15. The clock duty cycle calibration method according to claim 14, wherein the number of the capacitive elements connected in parallel to the duty detection circuit is controlled by a switching element connected in series with the capacitive element, and an on/off signal of the switching element is supplied from the decoding circuit.
16. The clock duty cycle calibration method according to claim 15, wherein the decoding circuit includes a first decoding circuit, and the setting code is converted into an output signal by the first decoding circuit to control the switching element to be turned on and off.
17. The clock duty cycle calibration method of claim 16, wherein the decoding circuit further comprises a second decoding circuit; the calibration method further comprises:
and converting the setting code into an output signal through the second decoding circuit so as to adjust the initial setting value of the delay chain to be half of the current period value of the clock.
18. The clock duty cycle calibration method according to claim 17, wherein the first decoding circuit or the second decoding circuit adopts a multiple-input multiple-output selector circuit in the memory MR6 mode register setting circuit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113364434A (en) * | 2021-06-23 | 2021-09-07 | 中国科学院微电子研究所 | Duty ratio calibration circuit and method |
| CN114420187A (en) * | 2020-10-28 | 2022-04-29 | 长鑫存储技术有限公司 | Calibration circuit, memory and calibration method |
| CN115941401A (en) * | 2022-10-27 | 2023-04-07 | 长鑫存储技术有限公司 | Data receiving circuit and semiconductor device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060232311A1 (en) * | 2005-04-15 | 2006-10-19 | Elpida Memory, Inc. | Duty detection circuit and method for controlling the same |
| US20070216457A1 (en) * | 2006-03-16 | 2007-09-20 | Agarwal Kanak B | Methods and arrangements to adjust a duty cycle |
| KR20090121469A (en) * | 2008-05-22 | 2009-11-26 | 주식회사 하이닉스반도체 | Semiconductor memory device |
| KR20100052079A (en) * | 2008-11-10 | 2010-05-19 | 주식회사 하이닉스반도체 | Duty cycle correction circuit and delay locked loop circuit including the same |
| KR20100066236A (en) * | 2008-12-09 | 2010-06-17 | 숭실대학교산학협력단 | Duty-cycle and phase error correction circuit device and method for thereof |
| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| US20170111036A1 (en) * | 2015-10-19 | 2017-04-20 | SK Hynix Inc. | Duty cycle detector circuit |
| CN209199607U (en) * | 2018-11-08 | 2019-08-02 | 长鑫存储技术有限公司 | Low-frequency clock duty-ratio calibrating circuit and memory |
-
2018
- 2018-11-08 CN CN201811326930.0A patent/CN111161773B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060232311A1 (en) * | 2005-04-15 | 2006-10-19 | Elpida Memory, Inc. | Duty detection circuit and method for controlling the same |
| US20070216457A1 (en) * | 2006-03-16 | 2007-09-20 | Agarwal Kanak B | Methods and arrangements to adjust a duty cycle |
| KR20090121469A (en) * | 2008-05-22 | 2009-11-26 | 주식회사 하이닉스반도체 | Semiconductor memory device |
| KR20100052079A (en) * | 2008-11-10 | 2010-05-19 | 주식회사 하이닉스반도체 | Duty cycle correction circuit and delay locked loop circuit including the same |
| KR20100066236A (en) * | 2008-12-09 | 2010-06-17 | 숭실대학교산학협력단 | Duty-cycle and phase error correction circuit device and method for thereof |
| US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
| US20170111036A1 (en) * | 2015-10-19 | 2017-04-20 | SK Hynix Inc. | Duty cycle detector circuit |
| CN209199607U (en) * | 2018-11-08 | 2019-08-02 | 长鑫存储技术有限公司 | Low-frequency clock duty-ratio calibrating circuit and memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420187A (en) * | 2020-10-28 | 2022-04-29 | 长鑫存储技术有限公司 | Calibration circuit, memory and calibration method |
| CN114420187B (en) * | 2020-10-28 | 2023-09-08 | 长鑫存储技术有限公司 | Calibration circuit, memory and calibration method |
| CN113364434A (en) * | 2021-06-23 | 2021-09-07 | 中国科学院微电子研究所 | Duty ratio calibration circuit and method |
| CN113364434B (en) * | 2021-06-23 | 2024-03-01 | 中国科学院微电子研究所 | Duty cycle calibration circuit and method |
| CN115941401A (en) * | 2022-10-27 | 2023-04-07 | 长鑫存储技术有限公司 | Data receiving circuit and semiconductor device |
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|---|---|
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