CN111063731B - CNT-IGZO thin film heterojunction bipolar transistor and preparation method and application thereof - Google Patents

Abstract

The invention discloses a CNT-IGZO thin film heterojunction bipolar transistor, a preparation method and application thereof, wherein the CNT-IGZO thin film heterojunction bipolar transistor comprises an IGZO layer and a CNT thin film covered on the surface of the IGZO layer; the preparation method comprises the steps of adopting a radio frequency magnetron sputtering method to prepare an IGZO layer as a channel material, and adopting a solution drop coating method to deposit a CNT film on the surface of the IGZO layer. The upper surface of the IGZO prepared by the radio frequency magnetron sputtering method is very flat, the roughness is less than 0.2nm, and the P-type CNT film is directly deposited on the surface of the IGZO, so that the P-type organic semiconductor can be close to the electrical property of the N-type oxide semiconductor, and compared with the prior art, the electrical property of the bipolar transistor is effectively improved, large-area array can be realized, and the method has a great application prospect.

Description

CNT-IGZO thin film heterojunction bipolar transistor and its preparation method and application

technical field

The invention belongs to the technical field of electronic devices, and in particular relates to a CNT-IGZO thin film heterojunction bipolar transistor and its preparation method and application.

Background technique

With the development of semiconducting carbon nanotube purification technology, semiconducting carbon nanotubes with high purity can now be obtained. High-purity carbon nanotubes exhibit p-type characteristics at room temperature and have high hole mobility; in addition, Due to its good flexibility and simple large-area preparation method, semiconducting carbon nanotubes have good application prospects in flexible and transparent logic circuits.

Forming complementary p-channel and n-channel inverter transistors in logic circuits is the most efficient and energy-saving design method. However, for semiconducting carbon nanotubes, due to their narrow bandgap (about 1.5eV ), so that holes are used as the main carriers to transport at room temperature. Therefore, there are few n-type carbon nanotubes, and a small amount of n-type semiconducting carbon nanotubes, because they need to go through a series of processing Packaging processing and lower test temperature, its performance such as low mobility is difficult to match, so we need to find n-type semiconductor materials with matching performance.

Oxide semiconductors have high mobility, and have the advantages of low-temperature preparation, low cost, and good uniformity, which fully meet the needs of logic circuits. Carbon nanotubes and oxide semiconductors combine the advantages of simple heterojunction processing technology and diverse methods, low cost, easy packaging, compatibility with flexible substrates, and can be processed at room temperature and mass-produced in large areas. In the logic circuit, the process flow can be reduced and the cost can be reduced, which can fully meet people's increasing demand for new electronic products.

The existing technology has realized the preparation of large-area arrays of indium gallium zinc oxide and semiconducting carbon nanotube heterostructure bipolar transistors at room temperature, providing theoretical and experimental support for subsequent applications in CMOS circuits. However, in the prior art, SWCNT/IGZO heterojunction bipolar transistors have been prepared by the solution method. Due to the low purity of the CNTs used, the performance is relatively poor, and the mobility of the IGZO prepared by the solution method is also very low, so the performance of the bipolar transistor prepared by it is poor, and it uses Al as the source and drain electrodes of the device, which causes a large contact resistance between the electrode and IGZO, which in turn affects the performance of the device.

Based on this, the present invention is proposed.

Contents of the invention

Aiming at the deficiencies in the prior art, the invention provides a CNT-IGZO thin film heterojunction bipolar transistor and its preparation method and application.

To achieve the above object, the present invention adopts the following technical solutions:

A CNT-IGZO thin film heterojunction bipolar transistor comprises an IGZO layer and a CNT thin film covering the surface of the IGZO layer.

In the above technical solution, the IGZO layer is prepared by radio frequency magnetron sputtering, and the roughness of the surface of the IGZO layer in contact with the CNT thin film is less than 0.2 nm.

In the above technical solution, the thickness of the CNT thin film is less than 5 nm, preferably 1-3 nm.

In the above technical solution, the thickness of the IGZO layer is 12-30 nm, preferably 15-24 nm, more preferably 20 nm.

Further, in a preferred embodiment, the CNT-IGZO thin film heterojunction bipolar transistor includes a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT film, a metal source electrode and a metal drain electrode, The silicon dioxide layer and the IGZO layer are sequentially arranged on the heavily doped P-type silicon wafer from bottom to top, the metal source electrode and the metal drain electrode cover the surface of the IGZO layer, and the CNT film covers the surface of the IGZO layer between the metal source electrode and the metal drain electrode.

Specifically, in the above technical solution, the thickness of the silicon dioxide layer is 250-360 nm, preferably 300 nm.

Specifically, in the above technical solution, the metal source electrode and the metal drain electrode are Ti/Au electrodes;

Preferably, in the above technical solution, the size of the metal source electrode and the metal drain electrode is 250 μm*250 μm.

Another aspect of the present invention also provides the preparation method of the above-mentioned CNT-IGZO thin film heterojunction bipolar transistor, comprising:

S1, using the radio frequency magnetron sputtering method to prepare the IGZO layer as the channel material;

S2. Depositing a CNT film on the surface of the IGZO layer by a solution drop coating method.

Specifically, in a preferred embodiment, step S1 is specifically, under the conditions that the power is 50-150W, the deposition pressure is 0.6-0.75Pa, and the deposition atmosphere is a mixture of argon and oxygen with a volume ratio of 12:1 , RF magnetron sputtering IGZO layer and annealing at 280-325°C for 50-75min in an oxygen atmosphere.

Specifically, in a preferred embodiment, step S2 is specifically, using ultraviolet lithography-evaporation to make a patterned metal electrode array, and then spin-coating PMMA glue, the specific parameters are, spin-coating 4- After 6s, spin coating at 2600-3250rpm for 50-75s, and develop the pattern at the channel, then drop-coat CNT solution, and get it after acetone degumming treatment.

Another aspect of the present invention also provides the application of the above-mentioned CNT-IGZO thin film heterojunction bipolar transistor or the above-mentioned preparation method in the preparation of optoelectronic devices.

Advantages of the present invention:

In the present invention, the upper surface of the IGZO prepared by radio frequency magnetron sputtering method is very smooth, and its roughness is less than 0.2nm, and the P-type CNT film is directly deposited on the IGZO surface, so that the P-type organic semiconductor can be combined with the N-type oxide semiconductor Compared with the prior art, the electrical performance of the bipolar transistor is effectively improved, and a large-area array can be realized, which has great application prospects.

Description of drawings

Fig. 1 is the structural representation of CNT-IGZO thin film heterojunction bipolar transistor in the embodiment of the present invention;

Fig. 2 is a transfer and output graph of a CNT-IGZO thin film heterojunction bipolar transistor in an embodiment of the present invention.

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

The following examples are used to illustrate the present invention, but are not used to limit the protection scope of the present invention, and the protection scope of the present invention is as the criterion with claims.

Unless otherwise specified, the experimental reagents and materials used in the examples of the present invention are all commercially available.

If not specified, the technical means used in the embodiments of the present invention are conventional means well known to those skilled in the art.

In the following examples, the high-purity carbon nanotube solution (toluene as a solvent) was provided by the group of Teacher Zhao Jianwen of Suzhou Institute of Nanotechnology, with a purity of 99%; the IGZO target was a commercially available product, purchased from Zhongjin Xinyan Company; the optical microscope was purchased from Leica company, the model is DM4000M; the electron beam evaporation coating system (O-50B) was purchased from Chongwen Technology Co., Ltd.; the vacuum probe station was purchased from Lake Shore Company; the model of magnetron sputtering equipment was ACS-4000-C4, which was purchased from ULVAC company; scanning electron/focused ion beam dual-beam system (SEM/FIB) was purchased from Holland and American FEI company.

Example

RF magnetron sputtering sputtering power is 50-150W, the ratio of argon to oxygen is 12:1, sputtering gas is 0.6-0.75Pa, prepare 20nm IGZO active layer, and anneal at 300℃ for 1 hour in oxygen atmosphere . On the preparation of the IGZO semiconductor active layer, drop-coat the high-purity semiconductor-type carbon nanotube solution. The specific process includes, using ultraviolet lithography technology to expose the electrode pattern on the IGZO film, and finally patterning it through the developer; on the patterned substrate Conduct electron beam evaporation, first evaporate 5nm titanium as the adhesion layer, then evaporate 30nm gold as the source electrode and drain electrode, after the evaporation is completed, remove the glue to obtain a patterned metal electrode array; spin-coat PMMA glue, at 500rpm Spin coating at 3000rpm for 5s, then spin coating at 3000rpm for 60s, and obtain the pattern of the channel by developing, then drop-coat CNT solution, and get it after acetone degelling treatment. Among them, the electrode size is 250 microns*250 microns, and the channel The length is 40 microns and the channel width is 500 microns.

As shown in Figure 1, its structure includes a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT film, a metal source electrode and a metal drain electrode, and the silicon dioxide layer and the IGZO layer are arranged in sequence from bottom to top. On the heavily doped P-type silicon wafer, the metal source electrode and the metal drain electrode cover the surface of the IGZO layer, and the CNT film covers the surface of the IGZO layer between the metal source electrode and the metal drain electrode.

The device was electrically characterized in a vacuum probe station, and the results are shown in Figure 2.

Figures 2.a and 2.b are the transfer curves of bipolar transistors in hole and electron enhancement modes, respectively. The transfer curve shows a typical V-shaped bipolar field effect transfer characteristic relationship, from which it can be seen that the gate voltage corresponding to the p-n turning point changes with the bias voltage applied across the source and drain. This change can explain is the transition between actual source-drain and nominal source-drain electrodes. Figures 2.c and 2.d are the output characteristic curves of bipolar transistors in the electron and hole enhancement modes, respectively, from which it can be seen that at a lower positive gate voltage, the transistor shows a diode-like curve characteristic, and the source-drain The current increases exponentially with the source-drain voltage, which is typical for bipolar transistors.

From the results of comprehensive analysis of the transfer characteristics and output characteristic curves of the four corresponding transistors in Fig. 2, it can be seen that the CNT-IGZO thin film heterojunction bipolar transistor prepared in the embodiment of the present invention finally exhibits bipolar characteristics, and the corresponding The on-state current, that is, the carrier mobility, is much higher than that reported in the literature.

Finally, the above are only preferred implementations of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (14)

1. The CNT-IGZO thin film heterojunction bipolar transistor is characterized by comprising an IGZO layer and a CNT thin film covered on the surface of the IGZO layer;

the IGZO layer is prepared by a radio frequency magnetron sputtering method, and the roughness of the surface of the IGZO layer, which is in contact with the CNT film, is less than 0.2nm.

2. The CNT-IGZO thin film heterojunction bipolar transistor of claim 1, wherein the CNT thin film has a thickness of less than 5 a nm a.

3. The CNT-IGZO thin film heterojunction bipolar transistor of claim 2, wherein the CNT thin film has a thickness of 1-3nm.

4. The CNT-IGZO thin film heterojunction bipolar transistor of claim 1, wherein the thickness of the IGZO layer is 12-30 nm.

5. The CNT-IGZO thin film heterojunction bipolar transistor of claim 4, wherein the thickness of the IGZO layer is 15-24 nm.

6. The CNT-IGZO thin film heterojunction bipolar transistor of claim 5, wherein the thickness of the IGZO layer is 20nm.

7. The CNT-IGZO thin film heterojunction bipolar transistor of any of claims 1-6, comprising a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT thin film, a metal source electrode and a metal drain electrode, wherein the silicon dioxide layer and the IGZO layer are sequentially disposed on the heavily doped P-type silicon wafer from bottom to top, the metal source electrode and the metal drain electrode are covered on the surface of the IGZO layer, and the CNT thin film is covered on the surface of the IGZO layer between the metal source electrode and the metal drain electrode.

8. The CNT-IGZO thin film heterojunction bipolar transistor of claim 7, wherein the thickness of the silicon dioxide layer is 250-360 nm.

9. The CNT-IGZO thin film heterojunction bipolar transistor of claim 8, wherein the thickness of the silicon dioxide layer is 300 a nm a.

10. The CNT-IGZO thin film heterojunction bipolar transistor of claim 7, wherein the metal source electrode and the metal drain electrode are Ti/Au electrodes.

11. The CNT-IGZO thin film heterojunction bipolar transistor of claim 10, wherein the metal source electrode and the metal drain electrode are 250 μιη in size.

12. The method for manufacturing the CNT-IGZO thin film heterojunction bipolar transistor as claimed in any one of claims 1 to 11, comprising:

s1, adopting a radio frequency magnetron sputtering method to prepare an IGZO layer as a channel material;

s2, depositing a CNT film on the surface of the IGZO layer by adopting a solution dripping method.

13. The method according to claim 12, wherein,

step S1 is specifically that under the conditions that the power is 50-150W, the deposition air pressure is 0.6-0.75Pa, the deposition atmosphere is the mixed gas of argon and oxygen with the volume ratio of 12:1, the radio frequency magnetron sputtering IGZO layer is carried out, and the annealing is carried out for 50-75min under the oxygen atmosphere at 280-325 ℃;

and/or, the step S2 is specifically to prepare a patterned metal electrode array by ultraviolet lithography-evaporation, spin-coat PMMA glue, spin-coat the patterned metal electrode array at 480-550rpm for 4-6S, spin-coat the patterned metal electrode array at 2600-3250rpm for 50-75S, obtain a pattern at a channel by development, then drip-coat a CNT solution, and remove the glue by acetone.

14. Use of the CNT-IGZO thin film heterojunction bipolar transistor of any of claims 1-11 or the method of preparation of any of claims 12-13 in the preparation of an optoelectronic device.

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